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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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10
passes/techmap/shregmap.cc
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@ -72,12 +72,12 @@ struct ShregmapTechGreenpak4 : ShregmapTech
bool fixup(Cell *cell, dict<int, SigBit> &taps)
{
auto D = cell->getPort(ID::D);
auto C = cell->getPort(ID::C);
auto D = cell->getPort(TW::D);
auto C = cell->getPort(TW::C);
auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
auto newcell = cell->module->addCell(NEW_TWINE, ID(GP_SHREG));
newcell->setPort(ID(nRST), State::S1);
newcell->setPort(ID::CLK, C);
newcell->setPort(TW::CLK, C);
newcell->setPort(ID(IN), D);
int i = 0;
@ -142,7 +142,7 @@ struct ShregmapWorker
// so that it can be identified as another chain
// (omitting this common flop)
// Link: https://github.com/YosysHQ/yosys/pull/1085
Wire *wire = module->addWire(NEW_ID);
Wire *wire = module->addWire(NEW_TWINE);
module->connect(wire, d_bit);
sigmap.add(wire, d_bit);
sigbit_chain_next.insert(std::make_pair(wire, cell));