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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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38
passes/techmap/extract_fa.cc
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@ -89,7 +89,7 @@ struct ExtractFaWorker
ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
{
SigBit y = sigmap(SigBit(cell->getPort(ID::Y)));
SigBit y = sigmap(SigBit(cell->getPort(TW::Y)));
log_assert(driver.count(y) == 0);
driver[y] = cell;
}
@ -281,8 +281,8 @@ struct ExtractFaWorker
void assign_new_driver(SigBit bit, SigBit new_driver)
{
Cell *cell = driver.at(bit);
if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) {
cell->setPort(ID::Y, module->addWire(NEW_ID));
if (sigmap(cell->getPort(TW::Y)) == SigSpec(bit)) {
cell->setPort(TW::Y, module->addWire(NEW_TWINE));
module->connect(bit, new_driver);
}
}
@ -394,20 +394,20 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
Cell *cell = module->addCell(NEW_TWINE, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", cell);
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
cell->setPort(TW::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(TW::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(TW::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEW_TWINE);
Y = module->addWire(NEW_TWINE);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
cell->setPort(TW::X, X);
cell->setPort(TW::Y, Y);
facache[fakey] = make_tuple(X, Y, cell);
}
@ -501,20 +501,20 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
Cell *cell = module->addCell(NEW_TWINE, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", cell);
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::C, State::S0);
cell->setPort(TW::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(TW::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(TW::C, State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEW_TWINE);
Y = module->addWire(NEW_TWINE);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
cell->setPort(TW::X, X);
cell->setPort(TW::Y, Y);
}
if (func2.at(key).count(xor2_func)) {