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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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10
passes/techmap/dfflibmap.cc
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@ -505,7 +505,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0)
cell_list.push_back(cell);
if (cell->type == ID($_NOT_))
notmap[sigmap(cell->getPort(ID::A))].insert(cell);
notmap[sigmap(cell->getPort(TW::A))].insert(cell);
}
std::map<std::string, int> stats;
@ -536,11 +536,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
} else
if (port.second == 'q') {
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->addWire(NEW_ID, GetSize(old_sig));
sig = module->addWire(NEW_TWINE, GetSize(old_sig));
if (has_q && has_qn) {
for (auto &it : notmap[sigmap(old_sig)]) {
module->connect(it->getPort(ID::Y), sig);
it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig)));
module->connect(it->getPort(TW::Y), sig);
it->setPort(TW::Y, module->addWire(NEW_TWINE, GetSize(old_sig)));
}
} else {
module->addNotGate(NEW_ID, sig, old_sig);
@ -554,7 +554,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
} else
if (port.second == 0) {
sig = module->addWire(NEW_ID);
sig = module->addWire(NEW_TWINE);
} else
log_abort();
new_cell->setPort("\\" + port.first, sig);