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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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10
passes/techmap/demuxmap.cc
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@ -50,17 +50,17 @@ struct DemuxmapPass : public Pass {
if (cell->type != ID($demux))
continue;
SigSpec sel = cell->getPort(ID::S);
SigSpec data = cell->getPort(ID::A);
SigSpec out = cell->getPort(ID::Y);
int width = GetSize(cell->getPort(ID::A));
SigSpec sel = cell->getPort(TW::S);
SigSpec data = cell->getPort(TW::A);
SigSpec out = cell->getPort(TW::Y);
int width = GetSize(cell->getPort(TW::A));
for (int i = 0; i < 1 << GetSize(sel); i++) {
if (width == 1 && data == State::S1) {
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]);
module->design->merge_src(eq_cell, cell);
} else {
Wire *eq = module->addWire(NEW_ID);
Wire *eq = module->addWire(NEW_TWINE);
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq);
module->design->merge_src(eq_cell, cell);
RTLIL::Cell *mux = module->addMux(NEW_ID,