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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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10
passes/techmap/clkbufmap.cc
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@ -261,21 +261,21 @@ struct ClkbufmapPass : public Pass {
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype, module, wire, i);
cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_ID);
cell = module->addCell(NEW_TWINE, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_TWINE);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, module, wire, i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
RTLIL::Cell *cell2 = module->addCell(NEW_TWINE, RTLIL::escape_id(inpad_celltype));
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
} else {
cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit);
cell = cell2;
}
iwire = module->addWire(NEW_ID);
iwire = module->addWire(NEW_TWINE);
cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
}
if (iwire)
@ -294,7 +294,7 @@ struct ClkbufmapPass : public Pass {
if (!input_bits.empty()) {
// This is an input port and some buffers were inserted -- we need
// to create a new input wire and transfer attributes.
Wire *new_wire = module->addWire(NEW_ID, wire);
Wire *new_wire = module->addWire(NEW_TWINE, wire);
for (int i = 0; i < wire->width; i++) {
SigBit wire_bit(wire, i);