mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-15 03:35:40 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
Download patch file Download diff file Expand all files Collapse all files

60
passes/techmap/abc.cc
View file

@ -476,8 +476,8 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_y);
@ -490,9 +490,9 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@ -526,10 +526,10 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@ -548,10 +548,10 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_c = cell->getPort(TW::C);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@ -570,11 +570,11 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_c = cell->getPort(TW::C);
RTLIL::SigSpec sig_d = cell->getPort(TW::D);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@ -1568,7 +1568,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
cell_stats[c->type.unescape()]++;
if (c->type.in(ID(ZERO), ID(ONE))) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
RTLIL::IdString name_y = remap_name(c->getPort(TW::Y).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
connect(assign_map, module, conn);
@ -1576,8 +1576,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
}
if (c->type == ID(BUF)) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
RTLIL::IdString name_a = remap_name(c->getPort(ID::A).as_wire()->name);
RTLIL::IdString name_y = remap_name(c->getPort(TW::Y).as_wire()->name);
RTLIL::IdString name_a = remap_name(c->getPort(TW::A).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = module->wire(name_a);
connect(assign_map, module, conn);
@ -1678,7 +1678,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.pol_ce = en_polarity;
ff.sig_ce = en_sig;
}
RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
RTLIL::Const init = mapped_initvals(c->getPort(TW::Q));
if (had_init)
ff.val_init = init;
else
@ -1697,8 +1697,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.sig_srst = srst_sig;
ff.val_srst = init;
}
ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
ff.sig_d = module->wire(remap_name(c->getPort(TW::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(TW::Q).as_wire()->name));
RTLIL::Cell *cell = ff.emit();
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
design->select(module, cell);
@ -1729,7 +1729,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.pol_ce = en_polarity;
ff.sig_ce = en_sig;
}
RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
RTLIL::Const init = mapped_initvals(c->getPort(TW::Q));
if (had_init)
ff.val_init = init;
else
@ -1746,17 +1746,17 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.sig_srst = srst_sig;
ff.val_srst = init;
}
ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
ff.sig_d = module->wire(remap_name(c->getPort(TW::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(TW::Q).as_wire()->name));
RTLIL::Cell *cell = ff.emit();
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
design->select(module, cell);
continue;
}
if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(ID::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(ID::Y).as_wire()->name));
if (c->type == ID($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(TW::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(TW::Y).as_wire()->name));
connect(assign_map, module, RTLIL::SigSig(my_a, my_y));
continue;
}

104
passes/techmap/abc9_ops.cc
View file

@ -132,7 +132,7 @@ void check(RTLIL::Design *design, bool dff_mode)
log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", derived_module);
found = true;
SigBit Q = derived_cell->getPort(ID::Q);
SigBit Q = derived_cell->getPort(TW::Q);
log_assert(GetSize(Q.wire) == 1);
if (!Q.wire->port_output)
@ -209,7 +209,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
if (derived_module->get_bool_attribute(ID::abc9_flop)) {
for (auto derived_cell : derived_module->cells())
if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
SigBit Q = derived_cell->getPort(ID::Q);
SigBit Q = derived_cell->getPort(TW::Q);
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
@ -344,10 +344,10 @@ void prep_bypass(RTLIL::Design *design)
// For these new input ports driven by the replaced
// cell, then create a new simple-path specify entry:
// (input => output) = 0
auto specify = bypass_module->addCell(NEW_ID, ID($specify2));
specify->setPort(ID::EN, State::S1);
specify->setPort(ID::SRC, src);
specify->setPort(ID::DST, dst);
auto specify = bypass_module->addCell(NEW_TWINE, ID($specify2));
specify->setPort(TW::EN, State::S1);
specify->setPort(TW::SRC, src);
specify->setPort(TW::DST, dst);
specify->setParam(ID::FULL, 0);
specify->setParam(ID::SRC_WIDTH, GetSize(src));
specify->setParam(ID::DST_WIDTH, GetSize(dst));
@ -371,11 +371,11 @@ void prep_bypass(RTLIL::Design *design)
for (auto cell : inst_module->cells()) {
if (cell->type != ID($specify2))
continue;
auto EN = cell->getPort(ID::EN).as_bit();
auto EN = cell->getPort(TW::EN).as_bit();
SigBit newEN;
if (!EN.wire && EN != State::S1)
continue;
auto SRC = cell->getPort(ID::SRC);
auto SRC = cell->getPort(TW::SRC);
for (const auto &c : SRC.chunks())
if (c.wire && !c.wire->port_input) {
SRC = SigSpec();
@ -383,7 +383,7 @@ void prep_bypass(RTLIL::Design *design)
}
if (SRC.empty())
continue;
auto DST = cell->getPort(ID::DST);
auto DST = cell->getPort(TW::DST);
for (const auto &c : DST.chunks())
if (c.wire && !c.wire->port_output) {
DST = SigSpec();
@ -405,7 +405,7 @@ void prep_bypass(RTLIL::Design *design)
}
sig = std::move(new_sig);
};
auto specify = bypass_module->addCell(NEW_ID, cell);
auto specify = bypass_module->addCell(NEW_TWINE, cell);
specify->rewrite_sigspecs(rw);
}
bypass_module->fixup_ports();
@ -415,7 +415,7 @@ void prep_bypass(RTLIL::Design *design)
// original cell, but with additional inputs taken from the
// replaced cell
auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
auto bypass_cell = map_module->addCell(NEW_ID, cell->type.str() + "_$abc9_byp");
auto bypass_cell = map_module->addCell(NEW_TWINE, cell->type.str() + "_$abc9_byp");
for (const auto &conn : cell->connections()) {
auto port = map_module->wire(conn.first);
if (cell->input(conn.first)) {
@ -493,7 +493,7 @@ void prep_dff_submod(RTLIL::Design *design)
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
log_assert(!dff_cell);
dff_cell = cell;
Q = cell->getPort(ID::Q);
Q = cell->getPort(TW::Q);
log_assert(GetSize(Q.wire) == 1);
}
else if (cell->type.in(ID($specify3), ID($specrule)))
@ -503,17 +503,17 @@ void prep_dff_submod(RTLIL::Design *design)
// Add an always-enabled CE mux that drives $_DFF_[NP]_.D so that:
// (a) flop box will have an output
// (b) $_DFF_[NP]_.Q will be present as an input
SigBit D = module->addWire(NEW_ID);
module->addMuxGate(NEW_ID, dff_cell->getPort(ID::D), Q, State::S0, D);
dff_cell->setPort(ID::D, D);
SigBit D = module->addWire(NEW_TWINE);
module->addMuxGate(NEW_ID, dff_cell->getPort(TW::D), Q, State::S0, D);
dff_cell->setPort(TW::D, D);
// Rewrite $specify cells that end with $_DFF_[NP]_.Q
// to $_DFF_[NP]_.D since it will be moved into
// the submodule
for (auto cell : specify_cells) {
auto DST = cell->getPort(ID::DST);
auto DST = cell->getPort(TW::DST);
DST.replace(Q, D);
cell->setPort(ID::DST, DST);
cell->setPort(TW::DST, DST);
}
design->scratchpad_set_bool("abc9_ops.prep_dff_submod.did_something", true);
@ -593,7 +593,7 @@ void break_scc(RTLIL::Module *module)
for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
Wire *w = module->addWire(NEW_TWINE, GetSize(c.second));
I.append(w);
O.append(c.second);
c.second = w;
@ -603,11 +603,11 @@ void break_scc(RTLIL::Module *module)
if (!I.empty())
{
auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER));
auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER));
log_assert(GetSize(I) == GetSize(O));
cell->setParam(ID::WIDTH, GetSize(I));
cell->setPort(ID::I, std::move(I));
cell->setPort(ID::O, std::move(O));
cell->setPort(TW::I, std::move(I));
cell->setPort(TW::O, std::move(O));
}
}
@ -681,7 +681,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto rhs = cell->getPort(i.first.name);
if (offset >= rhs.size())
continue;
auto O = module->addWire(NEW_ID);
auto O = module->addWire(NEW_TWINE);
#ifndef NDEBUG
if (ys_debug(1)) {
@ -695,9 +695,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
}
auto box = module->addCell(NEW_ID, r.first->second);
box->setPort(ID::I, rhs[offset]);
box->setPort(ID::O, O);
auto box = module->addCell(NEW_TWINE, r.first->second);
box->setPort(TW::I, rhs[offset]);
box->setPort(TW::O, O);
rhs[offset] = O;
cell->setPort(i.first.name, rhs);
}
@ -819,7 +819,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
Wire *w = module->addWire(NEW_TWINE, GetSize(c.second));
I.append(w);
O.append(c.second);
c.second = w;
@ -828,11 +828,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
if (!I.empty()) {
auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER));
auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER));
log_assert(GetSize(I) == GetSize(O));
cell->setParam(ID::WIDTH, GetSize(I));
cell->setPort(ID::I, std::move(I));
cell->setPort(ID::O, std::move(O));
cell->setPort(TW::I, std::move(I));
cell->setPort(TW::O, std::move(O));
// Rebuild topo ordering after inserting the additional breakers.
toposort.emplace();
@ -891,7 +891,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
auto &holes_cell = r.first->second;
if (r.second) {
if (box_module->get_bool_attribute(ID::whitebox)) {
holes_cell = holes_module->addCell(NEW_ID, cell->type);
holes_cell = holes_module->addCell(NEW_TWINE, cell->type);
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc -noopt");
@ -1270,8 +1270,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// $_DFF_[NP]_ cells since flop box already has all the information
// we need to reconstruct them
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
SigBit Q = cell->getPort(ID::Q);
module->connect(Q, cell->getPort(ID::D));
SigBit Q = cell->getPort(TW::Q);
module->connect(Q, cell->getPort(TW::D));
module->remove(cell);
auto Qi = initmap(Q);
auto it = Qi.wire->attributes.find(ID::init);
@ -1295,8 +1295,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// Short out $_FF_ cells since the flop box already has
// all the information we need to reconstruct cell
if (dff_mode && mapped_cell->type == ID($_FF_)) {
SigBit D = mapped_cell->getPort(ID::D);
SigBit Q = mapped_cell->getPort(ID::Q);
SigBit D = mapped_cell->getPort(TW::D);
SigBit Q = mapped_cell->getPort(TW::Q);
if (D.wire)
D.wire = module->wire(remap_name(D.wire->name));
Q.wire = module->wire(remap_name(Q.wire->name));
@ -1308,15 +1308,15 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
toposort.node(mapped_cell->name);
if (mapped_cell->type == ID($_NOT_)) {
RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
RTLIL::SigBit a_bit = mapped_cell->getPort(TW::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(TW::Y);
bit_users[a_bit].insert(mapped_cell->name);
// Ignore inouts for topo ordering
if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
bit_drivers[y_bit].insert(mapped_cell->name);
if (!a_bit.wire) {
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
mapped_cell->setPort(TW::Y, module->addWire(NEW_TWINE));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@ -1344,7 +1344,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::SigBit(module->wire(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wire(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort(ID::A)].push_back(cell);
bit2sinks[cell->getPort(TW::A)].push_back(cell);
cell_stats[ID($lut)]++;
}
else
@ -1560,8 +1560,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
if (it == not2drivers.end())
continue;
RTLIL::Cell *driver_lut = it->second;
RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
RTLIL::SigBit a_bit = not_cell->getPort(TW::A);
RTLIL::SigBit y_bit = not_cell->getPort(TW::Y);
RTLIL::Const driver_mask;
a_bit.wire = module->wire(remap_name(a_bit.wire->name));
@ -1577,7 +1577,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// Push downstream LUTs past inverter
for (auto sink_cell : jt->second) {
SigSpec A = sink_cell->getPort(ID::A);
SigSpec A = sink_cell->getPort(TW::A);
RTLIL::Const mask = sink_cell->getParam(ID::LUT);
int index = 0;
for (; index < GetSize(A); index++)
@ -1594,7 +1594,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
i += 1 << (index+1);
}
A[index] = y_bit;
sink_cell->setPort(ID::A, A);
sink_cell->setPort(TW::A, A);
sink_cell->setParam(ID::LUT, mask);
}
@ -1610,7 +1610,7 @@ clone_lut:
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
auto cell = module->addLut(NEW_ID,
driver_lut->getPort(ID::A),
driver_lut->getPort(TW::A),
y_bit,
driver_mask);
for (auto &bit : cell->connections_.at(ID::A)) {
@ -1636,7 +1636,7 @@ static void replace_zbufs(Design *design)
for (auto cell : mod->cells()) {
if (cell->type != ID($buf))
continue;
auto &sig = cell->getPort(ID::A);
auto &sig = cell->getPort(TW::A);
for (int i = 0; i < GetSize(sig); ++i) {
if (sig[i] == State::Sz) {
zbufs.push_back(cell);
@ -1646,20 +1646,20 @@ static void replace_zbufs(Design *design)
}
for (auto cell : zbufs) {
auto sig = cell->getPort(ID::A);
auto sig = cell->getPort(TW::A);
for (int i = 0; i < GetSize(sig); ++i) {
if (sig[i] == State::Sz) {
Wire *w = mod->addWire(NEW_ID);
Cell *ud = mod->addCell(NEW_ID, ID($tribuf));
Wire *w = mod->addWire(NEW_TWINE);
Cell *ud = mod->addCell(NEW_TWINE, ID($tribuf));
ud->set_bool_attribute(ID::aiger2_zbuf);
ud->setParam(ID::WIDTH, 1);
ud->setPort(ID::Y, w);
ud->setPort(ID::EN, State::S0);
ud->setPort(ID::A, State::S0);
ud->setPort(TW::Y, w);
ud->setPort(TW::EN, State::S0);
ud->setPort(TW::A, State::S0);
sig[i] = w;
}
}
cell->setPort(ID::A, sig);
cell->setPort(TW::A, sig);
}
mod->bufNormalize();
@ -1680,7 +1680,7 @@ static void restore_zbufs(Design *design)
to_remove.push_back(cell);
for (auto cell : to_remove) {
SigSpec sig_y = cell->getPort(ID::Y);
SigSpec sig_y = cell->getPort(TW::Y);
mod->addBuf(NEW_ID, Const(State::Sz, GetSize(sig_y)), sig_y);
mod->remove(cell);
}

6
passes/techmap/aigmap.cc
View file

@ -108,7 +108,7 @@ struct AigmapPass : public Pass {
SigBit A = sigs.at(node.left_parent);
SigBit B = sigs.at(node.right_parent);
if (nand_mode && node.inverter) {
bit = module->addWire(NEW_ID);
bit = module->addWire(NEW_TWINE);
auto gate = module->addNandGate(NEW_ID, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
@ -119,7 +119,7 @@ struct AigmapPass : public Pass {
if (and_cache.count(key))
bit = and_cache.at(key);
else {
bit = module->addWire(NEW_ID);
bit = module->addWire(NEW_TWINE);
auto gate = module->addAndGate(NEW_ID, A, B, bit);
if (select_mode)
new_sel.insert(gate->name);
@ -128,7 +128,7 @@ struct AigmapPass : public Pass {
}
if (node.inverter) {
SigBit new_bit = module->addWire(NEW_ID);
SigBit new_bit = module->addWire(NEW_TWINE);
auto gate = module->addNotGate(NEW_ID, bit, new_bit);
bit = new_bit;
if (select_mode)

54
passes/techmap/alumacc.cc
View file

@ -89,7 +89,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_eq() {
if (GetSize(cached_eq) == 0)
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(ID::X), false, alu_cell->src_ref());
cached_eq = alu_cell->module->ReduceAnd(NEW_ID, alu_cell->getPort(TW::X), false, alu_cell->src_ref());
return cached_eq;
}
@ -101,7 +101,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_cf() {
if (GetSize(cached_cf) == 0) {
cached_cf = alu_cell->getPort(ID::CO);
cached_cf = alu_cell->getPort(TW::CO);
log_assert(GetSize(cached_cf) >= 1);
cached_cf = alu_cell->module->Not(NEW_ID, cached_cf[GetSize(cached_cf)-1], false, alu_cell->src_ref());
}
@ -110,7 +110,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_of() {
if (GetSize(cached_of) == 0) {
cached_of = {alu_cell->getPort(ID::CO), alu_cell->getPort(ID::CI)};
cached_of = {alu_cell->getPort(TW::CO), alu_cell->getPort(TW::CI)};
log_assert(GetSize(cached_of) >= 2);
cached_of = alu_cell->module->Xor(NEW_ID, cached_of[GetSize(cached_of)-1], cached_of[GetSize(cached_of)-2]);
}
@ -119,7 +119,7 @@ struct AlumaccWorker
RTLIL::SigSpec get_sf() {
if (GetSize(cached_sf) == 0) {
cached_sf = alu_cell->getPort(ID::Y);
cached_sf = alu_cell->getPort(TW::Y);
cached_sf = cached_sf[GetSize(cached_sf)-1];
}
return cached_sf;
@ -162,7 +162,7 @@ struct AlumaccWorker
Macc::term_t new_term;
n->cell = cell;
n->y = sigmap(cell->getPort(ID::Y));
n->y = sigmap(cell->getPort(TW::Y));
n->users = 0;
for (auto bit : n->y)
@ -170,7 +170,7 @@ struct AlumaccWorker
if (cell->type.in(ID($pos), ID($neg)))
{
new_term.in_a = sigmap(cell->getPort(ID::A));
new_term.in_a = sigmap(cell->getPort(TW::A));
new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_term.do_subtract = cell->type == ID($neg);
n->macc.terms.push_back(new_term);
@ -178,12 +178,12 @@ struct AlumaccWorker
if (cell->type.in(ID($add), ID($sub)))
{
new_term.in_a = sigmap(cell->getPort(ID::A));
new_term.in_a = sigmap(cell->getPort(TW::A));
new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_term.do_subtract = false;
n->macc.terms.push_back(new_term);
new_term.in_a = sigmap(cell->getPort(ID::B));
new_term.in_a = sigmap(cell->getPort(TW::B));
new_term.is_signed = cell->getParam(ID::B_SIGNED).as_bool();
new_term.do_subtract = cell->type == ID($sub);
n->macc.terms.push_back(new_term);
@ -191,8 +191,8 @@ struct AlumaccWorker
if (cell->type.in(ID($mul)))
{
new_term.in_a = sigmap(cell->getPort(ID::A));
new_term.in_b = sigmap(cell->getPort(ID::B));
new_term.in_a = sigmap(cell->getPort(TW::A));
new_term.in_b = sigmap(cell->getPort(TW::B));
new_term.is_signed = cell->getParam(ID::A_SIGNED).as_bool();
new_term.do_subtract = false;
n->macc.terms.push_back(new_term);
@ -379,7 +379,7 @@ struct AlumaccWorker
for (auto &it : sig_macc)
{
auto n = it.second;
auto cell = module->addCell(NEW_ID, ID($macc));
auto cell = module->addCell(NEW_TWINE, ID($macc));
macc_counter++;
@ -389,7 +389,7 @@ struct AlumaccWorker
n->macc.optimize(GetSize(n->y));
n->macc.to_cell(cell);
cell->setPort(ID::Y, n->y);
cell->setPort(TW::Y, n->y);
cell->fixup_parameters();
module->remove(n->cell);
delete n;
@ -418,9 +418,9 @@ struct AlumaccWorker
bool cmp_equal = cell->type.in(ID($le), ID($ge));
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec A = sigmap(cell->getPort(TW::A));
RTLIL::SigSpec B = sigmap(cell->getPort(TW::B));
RTLIL::SigSpec Y = sigmap(cell->getPort(TW::Y));
alunode_t *n = nullptr;
@ -445,7 +445,7 @@ struct AlumaccWorker
n->a = A;
n->b = B;
n->c = State::S1;
n->y = module->addWire(NEW_ID, max(GetSize(A), GetSize(B)));
n->y = module->addWire(NEW_TWINE, max(GetSize(A), GetSize(B)));
n->is_signed = is_signed;
n->invert_b = true;
sig_alu[RTLIL::SigSig(A, B)].insert(n);
@ -463,9 +463,9 @@ struct AlumaccWorker
bool cmp_equal = cell->type.in(ID($eq), ID($eqx));
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
RTLIL::SigSpec A = sigmap(cell->getPort(ID::A));
RTLIL::SigSpec B = sigmap(cell->getPort(ID::B));
RTLIL::SigSpec Y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec A = sigmap(cell->getPort(TW::A));
RTLIL::SigSpec B = sigmap(cell->getPort(TW::B));
RTLIL::SigSpec Y = sigmap(cell->getPort(TW::Y));
alunode_t *n = nullptr;
@ -509,7 +509,7 @@ struct AlumaccWorker
goto delete_node;
}
n->alu_cell = module->addCell(NEW_ID, ID($alu));
n->alu_cell = module->addCell(NEW_TWINE, ID($alu));
alu_counter++;
log(" creating $alu cell for ");
@ -520,13 +520,13 @@ struct AlumaccWorker
if (n->cells.size() > 0)
n->alu_cell->adopt_src_from(n->cells[0]);
n->alu_cell->setPort(ID::A, n->a);
n->alu_cell->setPort(ID::B, n->b);
n->alu_cell->setPort(ID::CI, GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort(ID::BI, n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort(ID::Y, n->y);
n->alu_cell->setPort(ID::X, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(ID::CO, module->addWire(NEW_ID, GetSize(n->y)));
n->alu_cell->setPort(TW::A, n->a);
n->alu_cell->setPort(TW::B, n->b);
n->alu_cell->setPort(TW::CI, GetSize(n->c) ? n->c : State::S0);
n->alu_cell->setPort(TW::BI, n->invert_b ? State::S1 : State::S0);
n->alu_cell->setPort(TW::Y, n->y);
n->alu_cell->setPort(TW::X, module->addWire(NEW_TWINE, GetSize(n->y)));
n->alu_cell->setPort(TW::CO, module->addWire(NEW_TWINE, GetSize(n->y)));
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
for (auto &it : n->cmp)

28
passes/techmap/arith_tree.cc
View file

@ -79,15 +79,15 @@ struct AluInfo {
Traversal &traversal;
bool is_subtract(Cell *cell)
{
SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
SigSpec bi = traversal.sigmap(cell->getPort(TW::BI));
SigSpec ci = traversal.sigmap(cell->getPort(TW::CI));
return GetSize(bi) == 1 && bi[0] == State::S1 && GetSize(ci) == 1 && ci[0] == State::S1;
}
bool is_add(Cell *cell)
{
SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
SigSpec bi = traversal.sigmap(cell->getPort(TW::BI));
SigSpec ci = traversal.sigmap(cell->getPort(TW::CI));
return GetSize(bi) == 1 && bi[0] == State::S0 && GetSize(ci) == 1 && ci[0] == State::S0;
}
@ -96,10 +96,10 @@ struct AluInfo {
if (!(is_add(cell) || is_subtract(cell)))
return false;
for (auto bit : traversal.sigmap(cell->getPort(ID::X)))
for (auto bit : traversal.sigmap(cell->getPort(TW::X)))
if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
return false;
for (auto bit : traversal.sigmap(cell->getPort(ID::CO)))
for (auto bit : traversal.sigmap(cell->getPort(TW::CO)))
if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
return false;
@ -140,7 +140,7 @@ struct Rewriter {
{
dict<Cell *, Cell *> parent_of;
for (auto cell : candidates) {
Cell *consumer = sole_chainable_consumer(traversal.sigmap(cell->getPort(ID::Y)), candidates);
Cell *consumer = sole_chainable_consumer(traversal.sigmap(cell->getPort(TW::Y)), candidates);
if (consumer && consumer != cell)
parent_of[cell] = consumer;
}
@ -180,7 +180,7 @@ struct Rewriter {
{
pool<SigBit> bits;
for (auto cell : chain)
for (auto bit : traversal.sigmap(cell->getPort(ID::Y)))
for (auto bit : traversal.sigmap(cell->getPort(TW::Y)))
bits.insert(bit);
return bits;
}
@ -207,8 +207,8 @@ struct Rewriter {
return false;
// Check if any bit of child's Y connects to parent's B
SigSpec child_y = traversal.sigmap(child->getPort(ID::Y));
SigSpec parent_b = traversal.sigmap(parent->getPort(ID::B));
SigSpec child_y = traversal.sigmap(child->getPort(TW::Y));
SigSpec parent_b = traversal.sigmap(parent->getPort(TW::B));
for (auto bit : child_y)
for (auto pbit : parent_b)
if (bit == pbit)
@ -247,8 +247,8 @@ struct Rewriter {
for (auto cell : chain) {
bool cell_neg = negated.count(cell) ? negated[cell] : false;
SigSpec a = traversal.sigmap(cell->getPort(ID::A));
SigSpec b = traversal.sigmap(cell->getPort(ID::B));
SigSpec a = traversal.sigmap(cell->getPort(TW::A));
SigSpec b = traversal.sigmap(cell->getPort(TW::B));
bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
bool b_sub = (cell->type == ID($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
@ -357,7 +357,7 @@ struct Rewriter {
for (auto c : chain)
to_remove.insert(c);
replace_with_carry_save_tree(operands, root->getPort(ID::Y), neg_compensation, "Replaced add/sub chain");
replace_with_carry_save_tree(operands, root->getPort(TW::Y), neg_compensation, "Replaced add/sub chain");
}
for (auto cell : to_remove)
@ -374,7 +374,7 @@ struct Rewriter {
if (operands.size() < 3)
continue;
replace_with_carry_save_tree(operands, cell->getPort(ID::Y), neg_compensation, "Replaced $macc");
replace_with_carry_save_tree(operands, cell->getPort(TW::Y), neg_compensation, "Replaced $macc");
module->remove(cell);
}
}

16
passes/techmap/bmuxmap.cc
View file

@ -59,17 +59,17 @@ struct BmuxmapPass : public Pass {
if (cell->type != ID($bmux))
continue;
SigSpec sel = cell->getPort(ID::S);
SigSpec data = cell->getPort(ID::A);
int width = GetSize(cell->getPort(ID::Y));
int s_width = GetSize(cell->getPort(ID::S));
SigSpec sel = cell->getPort(TW::S);
SigSpec data = cell->getPort(TW::A);
int width = GetSize(cell->getPort(TW::Y));
int s_width = GetSize(cell->getPort(TW::S));
if(pmux_mode)
{
int num_cases = 1 << s_width;
SigSpec new_a = SigSpec(State::Sx, width);
SigSpec new_s = module->addWire(NEW_ID, num_cases);
SigSpec new_data = module->addWire(NEW_ID, width);
SigSpec new_s = module->addWire(NEW_TWINE, num_cases);
SigSpec new_data = module->addWire(NEW_TWINE, width);
for (int val = 0; val < num_cases; val++)
{
module->addEq(NEW_ID, sel, SigSpec(val, GetSize(sel)), new_s[val]);
@ -81,7 +81,7 @@ struct BmuxmapPass : public Pass {
else
{
for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
SigSpec new_data = module->addWire(NEW_TWINE, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
RTLIL::Cell *mux = module->addMux(NEW_ID,
data.extract(i*2, width),
@ -94,7 +94,7 @@ struct BmuxmapPass : public Pass {
}
}
module->connect(cell->getPort(ID::Y), data);
module->connect(cell->getPort(TW::Y), data);
module->remove(cell);
}
}

78
passes/techmap/booth.cc
View file

@ -213,9 +213,9 @@ struct BoothPassWorker {
bool is_signed;
if (cell->type == ID($mul)) {
A = cell->getPort(ID::A);
B = cell->getPort(ID::B);
Y = cell->getPort(ID::Y);
A = cell->getPort(TW::A);
B = cell->getPort(TW::B);
Y = cell->getPort(TW::Y);
log_assert(cell->getParam(ID::A_SIGNED).as_bool() == cell->getParam(ID::B_SIGNED).as_bool());
is_signed = cell->getParam(ID::A_SIGNED).as_bool();
@ -231,7 +231,7 @@ struct BoothPassWorker {
A = macc.terms[0].in_a;
B = macc.terms[0].in_b;
is_signed = macc.terms[0].is_signed;
Y = cell->getPort(ID::Y);
Y = cell->getPort(TW::Y);
} else {
continue;
}
@ -290,7 +290,7 @@ struct BoothPassWorker {
int required_op_size = x_sz_revised + y_sz_revised;
if (required_op_size != z_sz) {
SigSpec expanded_Y = module->addWire(NEW_ID, required_op_size);
SigSpec expanded_Y = module->addWire(NEW_TWINE, required_op_size);
SigSpec Y_driver = expanded_Y;
Y_driver.extend_u0(Y.size(), is_signed);
module->connect(Y, Y_driver);
@ -518,29 +518,29 @@ struct BoothPassWorker {
int ix = 0;
for (auto csa_elem : csa_tree) {
printf("\tCell %d %s type %s\n", ix, csa_elem->name.c_str(), csa_elem->type.c_str());
if (csa_elem->getPort(ID::A) == State::S0)
if (csa_elem->getPort(TW::A) == State::S0)
printf("\tA set to constant 0\n");
else if (csa_elem->getPort(ID::A) == State::S1)
else if (csa_elem->getPort(TW::A) == State::S1)
printf("\tA set to constant 1\n");
else
printf("\tA driven by %s\n", csa_elem->getPort(ID::A).as_wire()->name.c_str());
printf("\tA driven by %s\n", csa_elem->getPort(TW::A).as_wire()->name.c_str());
if (csa_elem->getPort(ID::B) == State::S0)
if (csa_elem->getPort(TW::B) == State::S0)
printf("\tB set to constant 0\n");
else if (csa_elem->getPort(ID::B) == State::S1)
else if (csa_elem->getPort(TW::B) == State::S1)
printf("\tB set to constant 1\n");
else
printf("\tB driven by %s\n", csa_elem->getPort(ID::B).as_wire()->name.c_str());
printf("\tB driven by %s\n", csa_elem->getPort(TW::B).as_wire()->name.c_str());
if (csa_elem->getPort(ID::C) == State::S0)
if (csa_elem->getPort(TW::C) == State::S0)
printf("\tC set to constant 0\n");
else if (csa_elem->getPort(ID::C) == State::S1)
else if (csa_elem->getPort(TW::C) == State::S1)
printf("\tC set to constant 1\n");
else
printf("\tC driven by %s\n", csa_elem->getPort(ID::C).as_wire()->name.c_str());
printf("\tC driven by %s\n", csa_elem->getPort(TW::C).as_wire()->name.c_str());
printf("Carry out: %s\n", csa_elem->getPort(ID::X).as_wire()->name.c_str());
printf("Sum out: %s\n", csa_elem->getPort(ID::Y).as_wire()->name.c_str());
printf("Carry out: %s\n", csa_elem->getPort(TW::X).as_wire()->name.c_str());
printf("Sum out: %s\n", csa_elem->getPort(TW::Y).as_wire()->name.c_str());
ix++;
}
@ -718,7 +718,7 @@ struct BoothPassWorker {
// End Case
else if (n == s_vec.size() - 1) {
// Make the carry results.. Two extra bits after fa.
SigBit carry_out = module->addWire(NEW_ID, 1);
SigBit carry_out = module->addWire(NEW_TWINE, 1);
module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
/* A */ s_vec[n],
/* B */ c_vec[n - 1],
@ -746,7 +746,7 @@ struct BoothPassWorker {
}
// Step case
else {
SigBit carry_out = module->addWire(NEW_ID_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
SigBit carry_out = module->addWire(NEW_TWINE_SUFFIX(stringf("cpa_%d_carry_%d", cpa_id, n)), 1);
module->addFa(NEW_ID_SUFFIX(stringf("cpa_%d_fa_%d", cpa_id, n)),
/* A */ s_vec[n],
/* B */ c_vec[n - 1],
@ -785,8 +785,8 @@ struct BoothPassWorker {
if (first_csa_ips.size() > 0) {
// build the first csa
auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
/* A */ first_csa_ips[0],
@ -817,8 +817,8 @@ struct BoothPassWorker {
}
if (csa_ips.size() > 0) {
auto c_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEW_ID_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto c_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_c", column_ix, csa_ix + 1)), 1);
auto s_wire = module->addWire(NEW_TWINE_SUFFIX(stringf("csa_%d_%d_s", column_ix, csa_ix + 1)), 1);
auto csa = module->addFa(NEW_ID_SUFFIX(stringf("csa_%d_%d", column_ix, csa_ix)),
/* A */ s_result,
@ -850,10 +850,10 @@ struct BoothPassWorker {
for (int y_ix = 0; y_ix < (!is_signed ? y_sz : y_sz - 1);) {
std::string enc_name = stringf("bur_enc_%d", encoder_ix);
two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
two_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
if (y_ix == 0) {
BuildBur4e(enc_name, State::S0, Y[y_ix],
@ -910,10 +910,10 @@ struct BoothPassWorker {
std::string enc_name = stringf("br_enc_pad_%d", encoder_ix);
two_int.append(module->addWire(NEW_ID_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEW_ID_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEW_ID_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEW_ID_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
two_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("two_int_%d", encoder_ix)), 1));
one_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("one_int_%d", encoder_ix)), 1));
s_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("s_int_%d", encoder_ix)), 1));
sb_int.append(module->addWire(NEW_TWINE_SUFFIX(stringf("sb_int_%d", encoder_ix)), 1));
SigBit one_o_int, two_o_int, s_o_int, sb_o_int;
BuildBur4e(enc_name, Y[y_ix], State::S0,
@ -957,10 +957,10 @@ struct BoothPassWorker {
for (unsigned encoder_ix = 1; encoder_ix <= enc_count; encoder_ix++) {
std::string enc_name = stringf("enc_%d", encoder_ix);
negi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
twoi_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
onei_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
cori_n_int[encoder_ix - 1] = module->addWire(NEW_ID_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
negi_n_int[encoder_ix - 1] = module->addWire(NEW_TWINE_SUFFIX(stringf("negi_n_int_%d", encoder_ix)), 1);
twoi_n_int[encoder_ix - 1] = module->addWire(NEW_TWINE_SUFFIX(stringf("twoi_n_int_%d", encoder_ix)), 1);
onei_n_int[encoder_ix - 1] = module->addWire(NEW_TWINE_SUFFIX(stringf("onei_n_int_%d", encoder_ix)), 1);
cori_n_int[encoder_ix - 1] = module->addWire(NEW_TWINE_SUFFIX(stringf("cori_n_int_%d", encoder_ix)), 1);
if (encoder_ix == 1) {
BuildBr4e(enc_name, State::S0, Y[0], Y[1],
@ -995,10 +995,10 @@ struct BoothPassWorker {
for (int encoder_ix = 1; encoder_ix <= (int)enc_count; encoder_ix++) {
for (int decoder_ix = 1; decoder_ix <= dec_count; decoder_ix++) {
PPij[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
module->addWire(NEW_ID_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
module->addWire(NEW_TWINE_SUFFIX(stringf("ppij_%d_%d", encoder_ix, decoder_ix)), 1);
nxj[((encoder_ix - 1) * dec_count) + decoder_ix - 1] =
module->addWire(NEW_ID_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
module->addWire(NEW_TWINE_SUFFIX(stringf("nxj_%s%d_%d", decoder_ix == 1 ? "pre_dec_" : "",
encoder_ix, decoder_ix)), 1);
}
}
@ -1065,8 +1065,8 @@ struct BoothPassWorker {
std::vector<SigSpec> fa_carry;
for (fa_row_ix = 0; fa_row_ix < fa_row_count; fa_row_ix++) {
fa_sum.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
fa_carry.push_back(module->addWire(NEW_ID_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
fa_sum.push_back(module->addWire(NEW_TWINE_SUFFIX(stringf("fa_sum_%d", fa_row_ix)), fa_count));
fa_carry.push_back(module->addWire(NEW_TWINE_SUFFIX(stringf("fa_carry_%d", fa_row_ix)), fa_count));
}
// full adder creation
@ -1103,7 +1103,7 @@ struct BoothPassWorker {
// instantiate the cpa
SigSpec cpa_carry;
if (z_sz > fa_row_count * 2)
cpa_carry = module->addWire(NEW_ID_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
cpa_carry = module->addWire(NEW_TWINE_SUFFIX("cpa_carry"), z_sz - fa_row_count * 2);
// The end case where we pass the last two summands
// from prior row directly to product output

16
passes/techmap/bufnorm.cc
View file

@ -280,8 +280,8 @@ struct BufnormPass : public Pass {
if (!cell->type.in(ID($buf), ID($_BUF_)))
continue;
SigSpec insig = cell->getPort(ID::A);
SigSpec outsig = cell->getPort(ID::Y);
SigSpec insig = cell->getPort(TW::A);
SigSpec outsig = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(insig) && i < GetSize(outsig); i++)
sigmap.add(insig[i], outsig[i]);
@ -401,7 +401,7 @@ struct BufnormPass : public Pass {
it->second.sort(compare_wires_f);
w = *(it->second.begin());
} else {
w = module->addWire(NEW_ID, GetSize(conn.second));
w = module->addWire(NEW_TWINE, GetSize(conn.second));
for (int i = 0; i < GetSize(w); i++)
sigmap.add(SigBit(w, i), keysig[i]);
}
@ -442,20 +442,20 @@ struct BufnormPass : public Pass {
old_buffers.erase(it);
added_buffers.insert(cell);
if (cell->getPort(ID::A) == src) {
if (cell->getPort(TW::A) == src) {
count_kept_buffers++;
} else {
cell->setPort(ID::A, src);
cell->setPort(TW::A, src);
count_updated_buffers++;
}
return;
}
Cell *cell = module->addCell(NEW_ID, type);
Cell *cell = module->addCell(NEW_TWINE, type);
added_buffers.insert(cell);
cell->setPort(ID::A, src);
cell->setPort(ID::Y, dst);
cell->setPort(TW::A, src);
cell->setPort(TW::Y, dst);
cell->fixup_parameters();
count_created_buffers++;
};

8
passes/techmap/bwmuxmap.cc
View file

@ -52,10 +52,10 @@ struct BwmuxmapPass : public Pass {
{
if (cell->type != ID($bwmux))
continue;
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
auto not_s = module->Not(NEW_ID, sig_s);
auto masked_b = module->And(NEW_ID, sig_s, sig_b);

10
passes/techmap/clkbufmap.cc
View file

@ -261,21 +261,21 @@ struct ClkbufmapPass : public Pass {
bool is_input = wire->port_input && !inpad_celltype.empty() && module->get_bool_attribute(ID::top);
if (!buf_celltype.empty() && (!is_input || buffer_inputs)) {
log("Inserting %s on %s.%s[%d].\n", buf_celltype, module, wire, i);
cell = module->addCell(NEW_ID, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_ID);
cell = module->addCell(NEW_TWINE, RTLIL::escape_id(buf_celltype));
iwire = module->addWire(NEW_TWINE);
cell->setPort(RTLIL::escape_id(buf_portname), mapped_wire_bit);
cell->setPort(RTLIL::escape_id(buf_portname2), iwire);
}
if (is_input) {
log("Inserting %s on %s.%s[%d].\n", inpad_celltype, module, wire, i);
RTLIL::Cell *cell2 = module->addCell(NEW_ID, RTLIL::escape_id(inpad_celltype));
RTLIL::Cell *cell2 = module->addCell(NEW_TWINE, RTLIL::escape_id(inpad_celltype));
if (iwire) {
cell2->setPort(RTLIL::escape_id(inpad_portname), iwire);
} else {
cell2->setPort(RTLIL::escape_id(inpad_portname), mapped_wire_bit);
cell = cell2;
}
iwire = module->addWire(NEW_ID);
iwire = module->addWire(NEW_TWINE);
cell2->setPort(RTLIL::escape_id(inpad_portname2), iwire);
}
if (iwire)
@ -294,7 +294,7 @@ struct ClkbufmapPass : public Pass {
if (!input_bits.empty()) {
// This is an input port and some buffers were inserted -- we need
// to create a new input wire and transfer attributes.
Wire *new_wire = module->addWire(NEW_ID, wire);
Wire *new_wire = module->addWire(NEW_TWINE, wire);
for (int i = 0; i < wire->width; i++) {
SigBit wire_bit(wire, i);

4
passes/techmap/clockgate.cc
View file

@ -371,10 +371,10 @@ struct ClockgatePass : public Pass {
if (!matching_icg_desc)
continue;
Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name);
Cell* icg = module->addCell(NEW_TWINE, matching_icg_desc->name);
icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit);
icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit);
gclk.new_net = module->addWire(NEW_ID);
gclk.new_net = module->addWire(NEW_TWINE);
icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net);
// Tie low DFT ports like scan chain enable
for (auto port : matching_icg_desc->tie_lo_pins)

4
passes/techmap/constmap.cc
View file

@ -32,8 +32,8 @@ static RTLIL::SigChunk value;
void constmap_worker(RTLIL::SigSpec &sig)
{
if (sig.is_fully_const()){
value = module->addWire(NEW_ID, sig.size());
RTLIL::Cell *cell = module->addCell(NEW_ID, celltype);
value = module->addWire(NEW_TWINE, sig.size());
RTLIL::Cell *cell = module->addCell(NEW_TWINE, celltype);
cell->setParam(cell_paramname, sig.as_const());
cell->setPort(cell_portname, value);
sig = value;

10
passes/techmap/demuxmap.cc
View file

@ -50,17 +50,17 @@ struct DemuxmapPass : public Pass {
if (cell->type != ID($demux))
continue;
SigSpec sel = cell->getPort(ID::S);
SigSpec data = cell->getPort(ID::A);
SigSpec out = cell->getPort(ID::Y);
int width = GetSize(cell->getPort(ID::A));
SigSpec sel = cell->getPort(TW::S);
SigSpec data = cell->getPort(TW::A);
SigSpec out = cell->getPort(TW::Y);
int width = GetSize(cell->getPort(TW::A));
for (int i = 0; i < 1 << GetSize(sel); i++) {
if (width == 1 && data == State::S1) {
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), out[i]);
module->design->merge_src(eq_cell, cell);
} else {
Wire *eq = module->addWire(NEW_ID);
Wire *eq = module->addWire(NEW_TWINE);
RTLIL::Cell *eq_cell = module->addEq(NEW_ID, sel, Const(i, GetSize(sel)), eq);
module->design->merge_src(eq_cell, cell);
RTLIL::Cell *mux = module->addMux(NEW_ID,

14
passes/techmap/dfflegalize.cc
View file

@ -293,7 +293,7 @@ struct DffLegalizePass : public Pass {
ff_dff.has_ce = ff.has_ce;
ff_dff.sig_ce = ff.sig_ce;
ff_dff.pol_ce = ff.pol_ce;
ff_dff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_dff.sig_q = ff.module->addWire(NEW_TWINE, ff.width);
ff_dff.val_init = ff.val_init;
ff_dff.is_fine = ff.is_fine;
@ -310,7 +310,7 @@ struct DffLegalizePass : public Pass {
ff_adff.has_ce = ff.has_ce;
ff_adff.sig_ce = ff.sig_ce;
ff_adff.pol_ce = ff.pol_ce;
ff_adff.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_adff.sig_q = ff.module->addWire(NEW_TWINE, ff.width);
ff_adff.val_init = Const(State::Sx, ff.width);
ff_adff.has_arst = true;
ff_adff.sig_arst = ff.sig_arst;
@ -320,7 +320,7 @@ struct DffLegalizePass : public Pass {
FfData ff_sel(ff.module, &initvals, NEW_ID);
ff_sel.width = 1;
ff_sel.sig_q = ff.module->addWire(NEW_ID);
ff_sel.sig_q = ff.module->addWire(NEW_TWINE);
ff_sel.has_arst = true;
ff_sel.sig_arst = ff.sig_arst;
ff_sel.pol_arst = ff.pol_arst;
@ -403,7 +403,7 @@ struct DffLegalizePass : public Pass {
ff_clr.sig_arst = ff.sig_clr;
ff_clr.pol_arst = ff.pol_clr;
ff_clr.val_arst = Const(State::S0, ff.width);
ff_clr.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_clr.sig_q = ff.module->addWire(NEW_TWINE, ff.width);
ff_clr.val_init = init_clr ? ff.val_init : Const(State::Sx, ff.width);
ff_clr.is_fine = ff.is_fine;
@ -424,7 +424,7 @@ struct DffLegalizePass : public Pass {
ff_set.sig_arst = ff.sig_set;
ff_set.pol_arst = ff.pol_set;
ff_set.val_arst = Const(State::S1, ff.width);
ff_set.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_set.sig_q = ff.module->addWire(NEW_TWINE, ff.width);
ff_set.val_init = init_set ? ff.val_init : Const(State::Sx, ff.width);
ff_set.is_fine = ff.is_fine;
@ -435,7 +435,7 @@ struct DffLegalizePass : public Pass {
ff_sel.pol_set = ff.pol_set;
ff_sel.sig_clr = ff.sig_clr;
ff_sel.sig_set = ff.sig_set;
ff_sel.sig_q = ff.module->addWire(NEW_ID, ff.width);
ff_sel.sig_q = ff.module->addWire(NEW_TWINE, ff.width);
ff_sel.val_init = Const(initsel, ff.width);
ff_sel.is_fine = ff.is_fine;
@ -841,7 +841,7 @@ struct DffLegalizePass : public Pass {
ff.sig_ad = State::S0;
ff.val_arst = State::S1;
ff.remove_init();
Wire *new_q = ff.module->addWire(NEW_ID);
Wire *new_q = ff.module->addWire(NEW_TWINE);
if (ff.is_fine)
ff.module->addNotGate(NEW_ID, new_q, ff.sig_q);
else

10
passes/techmap/dfflibmap.cc
View file

@ -505,7 +505,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0)
cell_list.push_back(cell);
if (cell->type == ID($_NOT_))
notmap[sigmap(cell->getPort(ID::A))].insert(cell);
notmap[sigmap(cell->getPort(TW::A))].insert(cell);
}
std::map<std::string, int> stats;
@ -536,11 +536,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
} else
if (port.second == 'q') {
RTLIL::SigSpec old_sig = cell_connections[std::string("\\") + char(port.second - ('a' - 'A'))];
sig = module->addWire(NEW_ID, GetSize(old_sig));
sig = module->addWire(NEW_TWINE, GetSize(old_sig));
if (has_q && has_qn) {
for (auto &it : notmap[sigmap(old_sig)]) {
module->connect(it->getPort(ID::Y), sig);
it->setPort(ID::Y, module->addWire(NEW_ID, GetSize(old_sig)));
module->connect(it->getPort(TW::Y), sig);
it->setPort(TW::Y, module->addWire(NEW_TWINE, GetSize(old_sig)));
}
} else {
module->addNotGate(NEW_ID, sig, old_sig);
@ -554,7 +554,7 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
sig = RTLIL::SigSpec(port.second == '0' ? 0 : 1, 1);
} else
if (port.second == 0) {
sig = module->addWire(NEW_ID);
sig = module->addWire(NEW_TWINE);
} else
log_abort();
new_cell->setPort("\\" + port.first, sig);

72
passes/techmap/extract_counter.cc
View file

@ -135,17 +135,17 @@ int counter_tryextract(
return 3;
//CO and X must be unconnected (exactly one connection to each port)
if(!is_unconnected(sigmap(cell->getPort(ID::CO)), index))
if(!is_unconnected(sigmap(cell->getPort(TW::CO)), index))
return 7;
if(!is_unconnected(sigmap(cell->getPort(ID::X)), index))
if(!is_unconnected(sigmap(cell->getPort(TW::X)), index))
return 8;
//true if $alu is performing A - B, else A + B
bool alu_is_subtract;
//BI and CI must be both constant 0 or both constant 1 as well
const RTLIL::SigSpec bi_port = sigmap(cell->getPort(ID::BI));
const RTLIL::SigSpec ci_port = sigmap(cell->getPort(ID::CI));
const RTLIL::SigSpec bi_port = sigmap(cell->getPort(TW::BI));
const RTLIL::SigSpec ci_port = sigmap(cell->getPort(TW::CI));
if(bi_port.is_fully_const() && bi_port.as_int() == 1 &&
ci_port.is_fully_const() && ci_port.as_int() == 1)
{
@ -169,7 +169,7 @@ int counter_tryextract(
{
const int a_width = cell->getParam(ID::A_WIDTH).as_int();
const int b_width = cell->getParam(ID::B_WIDTH).as_int();
const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
const RTLIL::SigSpec b_port = sigmap(cell->getPort(TW::B));
// down, cnt <= cnt - 1
if (b_width == 1 && b_port.is_fully_const() && b_port.as_int() == 1)
@ -197,8 +197,8 @@ int counter_tryextract(
{
const int a_width = cell->getParam(ID::A_WIDTH).as_int();
const int b_width = cell->getParam(ID::B_WIDTH).as_int();
const RTLIL::SigSpec a_port = sigmap(cell->getPort(ID::A));
const RTLIL::SigSpec b_port = sigmap(cell->getPort(ID::B));
const RTLIL::SigSpec a_port = sigmap(cell->getPort(TW::A));
const RTLIL::SigSpec b_port = sigmap(cell->getPort(TW::B));
// down, cnt <= cnt + -1
if (b_width == a_width && b_port.is_fully_const() && b_port.is_fully_ones())
@ -252,7 +252,7 @@ int counter_tryextract(
//Y must have exactly one connection, and it has to be a $mux cell.
//We must have a direct bus connection from our Y to their A.
const RTLIL::SigSpec aluy = sigmap(cell->getPort(ID::Y));
const RTLIL::SigSpec aluy = sigmap(cell->getPort(TW::Y));
pool<Cell*> y_loads = get_other_cells(aluy, index, cell);
if(y_loads.size() != 1)
return 9;
@ -266,14 +266,14 @@ int counter_tryextract(
if (extract.count_is_up)
{
//B connection of the mux must be 0
const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(TW::B));
if(!(underflow.is_fully_const() && underflow.is_fully_zero()))
return 12;
}
else
{
//B connection of the mux is our underflow value
const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(ID::B));
const RTLIL::SigSpec underflow = sigmap(count_mux->getPort(TW::B));
if(!underflow.is_fully_const())
return 12;
extract.count_value = underflow.as_int();
@ -281,7 +281,7 @@ int counter_tryextract(
//S connection of the mux must come from an inverter if down, eq if up
//(need not be the only load)
const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(ID::S));
const RTLIL::SigSpec muxsel = sigmap(count_mux->getPort(TW::S));
extract.outsig = muxsel;
pool<Cell*> muxsel_conns = get_other_cells(muxsel, index, count_mux);
Cell* overflow_cell = NULL;
@ -303,7 +303,7 @@ int counter_tryextract(
//Y connection of the mux must have exactly one load, the counter's internal register, if there's no clock enable
//If we have a clock enable, Y drives the B input of a mux. A of that mux must come from our register
const RTLIL::SigSpec muxy = sigmap(count_mux->getPort(ID::Y));
const RTLIL::SigSpec muxy = sigmap(count_mux->getPort(TW::Y));
pool<Cell*> muxy_loads = get_other_cells(muxy, index, count_mux);
if(muxy_loads.size() != 1)
return 14;
@ -316,23 +316,23 @@ int counter_tryextract(
//This mux is probably a clock enable mux.
//Find our count register (should be our only load)
cemux = muxload;
cey = sigmap(cemux->getPort(ID::Y));
cey = sigmap(cemux->getPort(TW::Y));
pool<Cell*> cey_loads = get_other_cells(cey, index, cemux);
if(cey_loads.size() != 1)
return 24;
count_reg = *cey_loads.begin();
if(sigmap(cemux->getPort(ID::Y)) != sigmap(count_reg->getPort(ID::D)))
if(sigmap(cemux->getPort(TW::Y)) != sigmap(count_reg->getPort(TW::D)))
return 24;
//Mux should have A driven by count Q, and B by muxy
//if A and B are swapped, CE polarity is inverted
if(sigmap(cemux->getPort(ID::B)) == muxy &&
sigmap(cemux->getPort(ID::A)) == sigmap(count_reg->getPort(ID::Q)))
if(sigmap(cemux->getPort(TW::B)) == muxy &&
sigmap(cemux->getPort(TW::A)) == sigmap(count_reg->getPort(TW::Q)))
{
extract.ce_inverted = false;
}
else if(sigmap(cemux->getPort(ID::A)) == muxy &&
sigmap(cemux->getPort(ID::B)) == sigmap(count_reg->getPort(ID::Q)))
else if(sigmap(cemux->getPort(TW::A)) == muxy &&
sigmap(cemux->getPort(TW::B)) == sigmap(count_reg->getPort(TW::Q)))
{
extract.ce_inverted = true;
}
@ -343,7 +343,7 @@ int counter_tryextract(
//Select of the mux is our clock enable
extract.has_ce = true;
extract.ce = sigmap(cemux->getPort(ID::S));
extract.ce = sigmap(cemux->getPort(TW::S));
}
else
extract.has_ce = false;
@ -371,7 +371,7 @@ int counter_tryextract(
return 23;
//Save the reset
extract.rst = sigmap(count_reg->getPort(ID::ARST));
extract.rst = sigmap(count_reg->getPort(TW::ARST));
}
//TODO: support synchronous reset
else
@ -395,7 +395,7 @@ int counter_tryextract(
//Register output must have exactly two loads, the inverter and ALU
//(unless we have a parallel output!)
//If we have a clock enable, 3 is OK
const RTLIL::SigSpec qport = count_reg->getPort(ID::Q);
const RTLIL::SigSpec qport = count_reg->getPort(TW::Q);
extract.poutsig = qport;
extract.has_pout = false;
const RTLIL::SigSpec cnout = sigmap(qport);
@ -456,7 +456,7 @@ int counter_tryextract(
if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::A, true))
{
// B must be the overflow value
const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::B));
const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(TW::B));
if(!overflow.is_fully_const())
return 12;
extract.count_value = overflow.as_int();
@ -464,7 +464,7 @@ int counter_tryextract(
else if(is_full_bus(cnout, index, count_reg, ID::Q, overflow_cell, ID::B, true))
{
// A must be the overflow value
const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(ID::A));
const RTLIL::SigSpec overflow = sigmap(overflow_cell->getPort(TW::A));
if(!overflow.is_fully_const())
return 12;
extract.count_value = overflow.as_int();
@ -480,7 +480,7 @@ int counter_tryextract(
return 19;
//Look up the clock from the register
extract.clk = sigmap(count_reg->getPort(ID::CLK));
extract.clk = sigmap(count_reg->getPort(TW::CLK));
if(!extract.count_is_up)
{
@ -522,10 +522,10 @@ void counter_worker(
//A input is the count value. Check if it has COUNT_EXTRACT set.
//If it's not a wire, don't even try
auto port = sigmap(cell->getPort(ID::A));
auto port = sigmap(cell->getPort(TW::A));
if(!port.is_wire())
{
port = sigmap(cell->getPort(ID::B));
port = sigmap(cell->getPort(TW::B));
if(!port.is_wire())
return;
}
@ -614,13 +614,13 @@ void counter_worker(
string countname = string("$COUNTx$") + extract.rwire->name.unescape();
//Wipe all of the old connections to the ALU
cell->unsetPort(ID::A);
cell->unsetPort(ID::B);
cell->unsetPort(ID::BI);
cell->unsetPort(ID::CI);
cell->unsetPort(ID::CO);
cell->unsetPort(ID::X);
cell->unsetPort(ID::Y);
cell->unsetPort(TW::A);
cell->unsetPort(TW::B);
cell->unsetPort(TW::BI);
cell->unsetPort(TW::CI);
cell->unsetPort(TW::CO);
cell->unsetPort(TW::X);
cell->unsetPort(TW::Y);
cell->unsetParam(ID::A_SIGNED);
cell->unsetParam(ID::A_WIDTH);
cell->unsetParam(ID::B_SIGNED);
@ -639,7 +639,7 @@ void counter_worker(
//If the reset is active low, infer an inverter ($__COUNT_ cells always have active high reset)
if(extract.rst_inverted)
{
auto realreset = cell->module->addWire(NEW_ID);
auto realreset = cell->module->addWire(NEW_TWINE);
cell->module->addNot(NEW_ID, extract.rst, RTLIL::SigSpec(realreset));
cell->setPort(ID(RST), realreset);
}
@ -656,7 +656,7 @@ void counter_worker(
//cell->setParam(ID(CLKIN_DIVIDE), RTLIL::Const(1));
cell->setParam(ID(COUNT_TO), RTLIL::Const(extract.count_value));
cell->setParam(ID::WIDTH, RTLIL::Const(extract.width));
cell->setPort(ID::CLK, extract.clk);
cell->setPort(TW::CLK, extract.clk);
cell->setPort(ID(OUT), extract.outsig);
//Hook up clock enable
@ -665,7 +665,7 @@ void counter_worker(
cell->setParam(ID(HAS_CE), RTLIL::Const(1));
if(extract.ce_inverted)
{
auto realce = cell->module->addWire(NEW_ID);
auto realce = cell->module->addWire(NEW_TWINE);
cell->module->addNot(NEW_ID, extract.ce, RTLIL::SigSpec(realce));
cell->setPort(ID(CE), realce);
}

38
passes/techmap/extract_fa.cc
View file

@ -89,7 +89,7 @@ struct ExtractFaWorker
ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($_MUX_), ID($_NMUX_),
ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_)))
{
SigBit y = sigmap(SigBit(cell->getPort(ID::Y)));
SigBit y = sigmap(SigBit(cell->getPort(TW::Y)));
log_assert(driver.count(y) == 0);
driver[y] = cell;
}
@ -281,8 +281,8 @@ struct ExtractFaWorker
void assign_new_driver(SigBit bit, SigBit new_driver)
{
Cell *cell = driver.at(bit);
if (sigmap(cell->getPort(ID::Y)) == SigSpec(bit)) {
cell->setPort(ID::Y, module->addWire(NEW_ID));
if (sigmap(cell->getPort(TW::Y)) == SigSpec(bit)) {
cell->setPort(TW::Y, module->addWire(NEW_TWINE));
module->connect(bit, new_driver);
}
}
@ -394,20 +394,20 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
Cell *cell = module->addCell(NEW_TWINE, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", cell);
cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
cell->setPort(TW::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(TW::B, f3i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(TW::C, f3i.inv_c ? module->NotGate(NEW_ID, C) : C);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEW_TWINE);
Y = module->addWire(NEW_TWINE);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
cell->setPort(TW::X, X);
cell->setPort(TW::Y, Y);
facache[fakey] = make_tuple(X, Y, cell);
}
@ -501,20 +501,20 @@ struct ExtractFaWorker
}
else
{
Cell *cell = module->addCell(NEW_ID, ID($fa));
Cell *cell = module->addCell(NEW_TWINE, ID($fa));
cell->setParam(ID::WIDTH, 1);
log(" Created $fa cell %s.\n", cell);
cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(ID::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(ID::C, State::S0);
cell->setPort(TW::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A);
cell->setPort(TW::B, f2i.inv_b ? module->NotGate(NEW_ID, B) : B);
cell->setPort(TW::C, State::S0);
X = module->addWire(NEW_ID);
Y = module->addWire(NEW_ID);
X = module->addWire(NEW_TWINE);
Y = module->addWire(NEW_TWINE);
cell->setPort(ID::X, X);
cell->setPort(ID::Y, Y);
cell->setPort(TW::X, X);
cell->setPort(TW::Y, Y);
}
if (func2.at(key).count(xor2_func)) {

8
passes/techmap/extract_reduce.cc
View file

@ -148,7 +148,7 @@ struct ExtractReducePass : public Pass
head_cell = x;
auto y = sigmap(x->getPort(ID::Y));
auto y = sigmap(x->getPort(TW::Y));
log_assert(y.size() == 1);
// Should only continue if there is one fanout back into a cell (not to a port)
@ -166,7 +166,7 @@ struct ExtractReducePass : public Pass
{
//BFS, following all chains until they hit a cell of a different type
//Pick the longest one
auto y = sigmap(cell->getPort(ID::Y));
auto y = sigmap(cell->getPort(TW::Y));
pool<Cell*> current_loads = sig_to_sink[y];
pool<Cell*> next_loads;
@ -183,7 +183,7 @@ struct ExtractReducePass : public Pass
continue;
}
auto xy = sigmap(x->getPort(ID::Y));
auto xy = sigmap(x->getPort(TW::Y));
//If this signal drives a port, add it to the sinks
//(even though it may not be the end of a chain)
@ -256,7 +256,7 @@ struct ExtractReducePass : public Pass
// Worth it to create reduce cell
log(" Creating $reduce_* cell!\n");
SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);
SigBit output = sigmap(head_cell->getPort(TW::Y)[0]);
SigSpec input;
for (auto it : sources) {

4
passes/techmap/extractinv.cc
View file

@ -105,10 +105,10 @@ struct ExtractinvPass : public Pass {
cell->parameters.erase(param_name);
if (invmask.is_fully_zero())
continue;
Wire *iwire = module->addWire(NEW_ID, sig.size());
Wire *iwire = module->addWire(NEW_TWINE, sig.size());
for (int i = 0; i < sig.size(); i++)
if (invmask[i] == State::S1) {
RTLIL::Cell *icell = module->addCell(NEW_ID, RTLIL::escape_id(inv_celltype));
RTLIL::Cell *icell = module->addCell(NEW_TWINE, RTLIL::escape_id(inv_celltype));
icell->setPort(RTLIL::escape_id(inv_portname), SigSpec(iwire, i));
icell->setPort(RTLIL::escape_id(inv_portname2), sig[i]);
log("Inserting %s on %s.%s.%s[%d].\n", inv_celltype, module, cell->type.unescape(), port.first.unescape(), i);

2
passes/techmap/flowmap.cc
View file

@ -1432,7 +1432,7 @@ struct FlowmapWorker
{
auto origin = node_origins[node];
RTLIL::SigSpec driver = origin.cell->getPort(origin.port);
driver[origin.offset] = module->addWire(NEW_ID);
driver[origin.offset] = module->addWire(NEW_TWINE);
origin.cell->setPort(origin.port, driver);
}
}

8
passes/techmap/hilomap.cc
View file

@ -36,16 +36,16 @@ void hilomap_worker(RTLIL::SigSpec &sig)
for (auto &bit : sig) {
if (bit == RTLIL::State::S1 && !hicell_celltype.empty()) {
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
last_hi = module->addWire(NEW_TWINE);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, RTLIL::escape_id(hicell_celltype));
cell->setPort(RTLIL::escape_id(hicell_portname), last_hi);
}
bit = last_hi;
}
if (bit == RTLIL::State::S0 && !locell_celltype.empty()) {
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
last_lo = module->addWire(NEW_TWINE);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, RTLIL::escape_id(locell_celltype));
cell->setPort(RTLIL::escape_id(locell_portname), last_lo);
}
bit = last_lo;

2
passes/techmap/insbuf.cc
View file

@ -94,7 +94,7 @@ struct InsbufPass : public Pass {
sigmap.add(outbit);
}
Cell *cell = module->addCell(NEW_ID, celltype);
Cell *cell = module->addCell(NEW_TWINE, celltype);
cell->setPort(in_portname, rhs);
cell->setPort(out_portname, lhs);

6
passes/techmap/iopadmap.cc
View file

@ -254,7 +254,7 @@ struct IopadmapPass : public Pass {
// Gather tristate buffers and always-on drivers.
for (auto cell : module->cells())
if (cell->type == ID($_TBUF_)) {
SigBit bit = cell->getPort(ID::Y).as_bit();
SigBit bit = cell->getPort(TW::Y).as_bit();
tbuf_bits[bit] = cell;
} else {
for (auto port : cell->connections())
@ -305,8 +305,8 @@ struct IopadmapPass : public Pass {
if (tbuf_cell != nullptr) {
// Found a tristate buffer — use it.
en_sig = tbuf_cell->getPort(ID::E).as_bit();
data_sig = tbuf_cell->getPort(ID::A).as_bit();
en_sig = tbuf_cell->getPort(TW::E).as_bit();
data_sig = tbuf_cell->getPort(TW::A).as_bit();
} else if (is_driven) {
// No tristate buffer, but an always-on driver is present.
// If this is an inout port, we're creating a tinoutpad

4
passes/techmap/lut2bmux.cc
View file

@ -45,8 +45,8 @@ struct Lut2BmuxPass : public Pass {
for (auto cell : module->selected_cells()) {
if (cell->type == ID($lut)) {
cell->type = ID($bmux);
cell->setPort(ID::S, cell->getPort(ID::A));
cell->setPort(ID::A, cell->getParam(ID::LUT));
cell->setPort(TW::S, cell->getPort(TW::A));
cell->setPort(TW::A, cell->getParam(ID::LUT));
cell->unsetParam(ID::LUT);
cell->fixup_parameters();
log("Converted %s.%s to BMUX cell.\n", module, cell);

8
passes/techmap/lut2mux.cc
View file

@ -25,8 +25,8 @@ PRIVATE_NAMESPACE_BEGIN
int lut2mux(Cell *cell, bool word_mode)
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_y = cell->getPort(ID::Y);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_y = cell->getPort(TW::Y);
Const lut = cell->getParam(ID::LUT);
int count = 1;
@ -41,8 +41,8 @@ int lut2mux(Cell *cell, bool word_mode)
{
SigSpec sig_a_hi = sig_a[GetSize(sig_a)-1];
SigSpec sig_a_lo = sig_a.extract(0, GetSize(sig_a)-1);
SigSpec sig_y1 = cell->module->addWire(NEW_ID);
SigSpec sig_y2 = cell->module->addWire(NEW_ID);
SigSpec sig_y1 = cell->module->addWire(NEW_TWINE);
SigSpec sig_y2 = cell->module->addWire(NEW_TWINE);
Const lut1 = lut.extract(0, GetSize(lut)/2);
Const lut2 = lut.extract(GetSize(lut)/2, GetSize(lut)/2);

56
passes/techmap/maccmap.cc
View file

@ -108,16 +108,16 @@ struct MaccmapWorker
in3 = in3.extract(start_index, stop_index-start_index);
int width = GetSize(in1);
RTLIL::Wire *w1 = module->addWire(NEW_ID, width);
RTLIL::Wire *w2 = module->addWire(NEW_ID, width);
RTLIL::Wire *w1 = module->addWire(NEW_TWINE, width);
RTLIL::Wire *w2 = module->addWire(NEW_TWINE, width);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($fa));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($fa));
cell->setParam(ID::WIDTH, width);
cell->setPort(ID::A, in1);
cell->setPort(ID::B, in2);
cell->setPort(ID::C, in3);
cell->setPort(ID::Y, w1);
cell->setPort(ID::X, w2);
cell->setPort(TW::A, in1);
cell->setPort(TW::B, in2);
cell->setPort(TW::C, in3);
cell->setPort(TW::Y, w1);
cell->setPort(TW::X, w2);
out1 = {out_zeros_msb, w1, out_zeros_lsb};
out2 = {out_zeros_msb, w2, out_zeros_lsb};
@ -237,23 +237,23 @@ struct MaccmapWorker
}
RTLIL::Cell *c = module->addCell(NEW_ID, ID($alu));
c->setPort(ID::A, summands.front());
c->setPort(ID::B, summands.back());
c->setPort(ID::CI, State::S0);
c->setPort(ID::BI, State::S0);
c->setPort(ID::Y, module->addWire(NEW_ID, width));
c->setPort(ID::X, module->addWire(NEW_ID, width));
c->setPort(ID::CO, module->addWire(NEW_ID, width));
RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($alu));
c->setPort(TW::A, summands.front());
c->setPort(TW::B, summands.back());
c->setPort(TW::CI, State::S0);
c->setPort(TW::BI, State::S0);
c->setPort(TW::Y, module->addWire(NEW_TWINE, width));
c->setPort(TW::X, module->addWire(NEW_TWINE, width));
c->setPort(TW::CO, module->addWire(NEW_TWINE, width));
c->fixup_parameters();
if (!tree_sum_bits.empty()) {
c->setPort(ID::CI, tree_sum_bits.back());
c->setPort(TW::CI, tree_sum_bits.back());
tree_sum_bits.pop_back();
}
log_assert(tree_sum_bits.empty());
return c->getPort(ID::Y);
return c->getPort(TW::Y);
}
};
@ -264,17 +264,17 @@ extern void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap = false
void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
Macc macc;
macc.from_cell(cell);
RTLIL::SigSpec all_input_bits;
all_input_bits.append(cell->getPort(ID::A));
all_input_bits.append(cell->getPort(ID::B));
all_input_bits.append(cell->getPort(TW::A));
all_input_bits.append(cell->getPort(TW::B));
if (all_input_bits.to_sigbit_set().count(RTLIL::Sx)) {
module->connect(cell->getPort(ID::Y), RTLIL::SigSpec(RTLIL::Sx, width));
module->connect(cell->getPort(TW::Y), RTLIL::SigSpec(RTLIL::Sx, width));
return;
}
@ -296,7 +296,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto &term : macc.terms) {
summand_t this_summand;
if (GetSize(term.in_b)) {
this_summand.first = module->addWire(NEW_ID, width);
this_summand.first = module->addWire(NEW_TWINE, width);
module->addMul(NEW_ID, term.in_a, term.in_b, this_summand.first, term.is_signed);
} else if (GetSize(term.in_a) == 1 && GetSize(term.in_b) == 0 && !term.is_signed && !term.do_subtract) {
// Mimic old 'bit_terms' treatment in case it's relevant for performance,
@ -304,7 +304,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
bit_terms.append(term.in_a);
continue;
} else if (GetSize(term.in_a) != width) {
this_summand.first = module->addWire(NEW_ID, width);
this_summand.first = module->addWire(NEW_TWINE, width);
module->addPos(NEW_ID, term.in_a, this_summand.first, term.is_signed);
} else {
this_summand.first = term.in_a;
@ -325,7 +325,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (int i = 0; i < GetSize(summands); i += 2) {
if (i+1 < GetSize(summands)) {
summand_t this_summand;
this_summand.first = module->addWire(NEW_ID, width);
this_summand.first = module->addWire(NEW_TWINE, width);
this_summand.second = summands[i].second && summands[i+1].second;
if (summands[i].second == summands[i+1].second)
module->addAdd(NEW_ID, summands[i].first, summands[i+1].first, this_summand.first);
@ -343,9 +343,9 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
}
if (summands.front().second)
module->addNeg(NEW_ID, summands.front().first, cell->getPort(ID::Y));
module->addNeg(NEW_ID, summands.front().first, cell->getPort(TW::Y));
else
module->connect(cell->getPort(ID::Y), summands.front().first);
module->connect(cell->getPort(TW::Y), summands.front().first);
}
else
{
@ -366,7 +366,7 @@ void maccmap(RTLIL::Module *module, RTLIL::Cell *cell, bool unmap)
for (auto bit : bit_terms)
worker.add(bit, 0);
module->connect(cell->getPort(ID::Y), worker.synth());
module->connect(cell->getPort(TW::Y), worker.synth());
}
}

104
passes/techmap/muxcover.cc
View file

@ -122,7 +122,7 @@ struct MuxcoverWorker
}
}
if (cell->type == ID($_MUX_))
sig_to_mux[sigmap(cell->getPort(ID::Y))] = cell;
sig_to_mux[sigmap(cell->getPort(TW::Y))] = cell;
}
log(" Treeifying %d MUXes:\n", GetSize(sig_to_mux));
@ -141,8 +141,8 @@ struct MuxcoverWorker
if (sig_to_mux.count(bit) && (bit == rootsig || !roots.count(bit))) {
Cell *c = sig_to_mux.at(bit);
tree.muxes[bit] = c;
wavefront.insert(sigmap(c->getPort(ID::A)));
wavefront.insert(sigmap(c->getPort(ID::B)));
wavefront.insert(sigmap(c->getPort(TW::A)));
wavefront.insert(sigmap(c->getPort(TW::B)));
}
}
@ -185,7 +185,7 @@ struct MuxcoverWorker
tuple<SigBit, SigBit, SigBit> key(A, B, sel);
if (decode_mux_cache.count(key) == 0) {
auto &entry = decode_mux_cache[key];
std::get<0>(entry) = module->addWire(NEW_ID);
std::get<0>(entry) = module->addWire(NEW_TWINE);
std::get<2>(entry) = false;
decode_mux_reverse_cache[std::get<0>(entry)] = key;
}
@ -513,69 +513,69 @@ struct MuxcoverWorker
if (GetSize(mux.inputs) == 2) {
count_muxes_by_type[0]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::Y, bit);
Cell *cell = module->addCell(NEW_TWINE, ID($_MUX_));
cell->setPort(TW::A, mux.inputs[0]);
cell->setPort(TW::B, mux.inputs[1]);
cell->setPort(TW::S, mux.selects[0]);
cell->setPort(TW::Y, bit);
return;
}
if (GetSize(mux.inputs) == 4) {
count_muxes_by_type[1]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX4_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);
cell->setPort(ID::D, mux.inputs[3]);
cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::T, mux.selects[1]);
cell->setPort(ID::Y, bit);
Cell *cell = module->addCell(NEW_TWINE, ID($_MUX4_));
cell->setPort(TW::A, mux.inputs[0]);
cell->setPort(TW::B, mux.inputs[1]);
cell->setPort(TW::C, mux.inputs[2]);
cell->setPort(TW::D, mux.inputs[3]);
cell->setPort(TW::S, mux.selects[0]);
cell->setPort(TW::T, mux.selects[1]);
cell->setPort(TW::Y, bit);
return;
}
if (GetSize(mux.inputs) == 8) {
count_muxes_by_type[2]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX8_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);
cell->setPort(ID::D, mux.inputs[3]);
cell->setPort(ID::E, mux.inputs[4]);
cell->setPort(ID::F, mux.inputs[5]);
cell->setPort(ID::G, mux.inputs[6]);
cell->setPort(ID::H, mux.inputs[7]);
cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::T, mux.selects[1]);
cell->setPort(ID::U, mux.selects[2]);
cell->setPort(ID::Y, bit);
Cell *cell = module->addCell(NEW_TWINE, ID($_MUX8_));
cell->setPort(TW::A, mux.inputs[0]);
cell->setPort(TW::B, mux.inputs[1]);
cell->setPort(TW::C, mux.inputs[2]);
cell->setPort(TW::D, mux.inputs[3]);
cell->setPort(TW::E, mux.inputs[4]);
cell->setPort(TW::F, mux.inputs[5]);
cell->setPort(TW::G, mux.inputs[6]);
cell->setPort(TW::H, mux.inputs[7]);
cell->setPort(TW::S, mux.selects[0]);
cell->setPort(TW::T, mux.selects[1]);
cell->setPort(TW::U, mux.selects[2]);
cell->setPort(TW::Y, bit);
return;
}
if (GetSize(mux.inputs) == 16) {
count_muxes_by_type[3]++;
Cell *cell = module->addCell(NEW_ID, ID($_MUX16_));
cell->setPort(ID::A, mux.inputs[0]);
cell->setPort(ID::B, mux.inputs[1]);
cell->setPort(ID::C, mux.inputs[2]);
cell->setPort(ID::D, mux.inputs[3]);
cell->setPort(ID::E, mux.inputs[4]);
cell->setPort(ID::F, mux.inputs[5]);
cell->setPort(ID::G, mux.inputs[6]);
cell->setPort(ID::H, mux.inputs[7]);
cell->setPort(ID::I, mux.inputs[8]);
cell->setPort(ID::J, mux.inputs[9]);
cell->setPort(ID::K, mux.inputs[10]);
cell->setPort(ID::L, mux.inputs[11]);
cell->setPort(ID::M, mux.inputs[12]);
cell->setPort(ID::N, mux.inputs[13]);
cell->setPort(ID::O, mux.inputs[14]);
cell->setPort(ID::P, mux.inputs[15]);
cell->setPort(ID::S, mux.selects[0]);
cell->setPort(ID::T, mux.selects[1]);
cell->setPort(ID::U, mux.selects[2]);
cell->setPort(ID::V, mux.selects[3]);
cell->setPort(ID::Y, bit);
Cell *cell = module->addCell(NEW_TWINE, ID($_MUX16_));
cell->setPort(TW::A, mux.inputs[0]);
cell->setPort(TW::B, mux.inputs[1]);
cell->setPort(TW::C, mux.inputs[2]);
cell->setPort(TW::D, mux.inputs[3]);
cell->setPort(TW::E, mux.inputs[4]);
cell->setPort(TW::F, mux.inputs[5]);
cell->setPort(TW::G, mux.inputs[6]);
cell->setPort(TW::H, mux.inputs[7]);
cell->setPort(TW::I, mux.inputs[8]);
cell->setPort(TW::J, mux.inputs[9]);
cell->setPort(TW::K, mux.inputs[10]);
cell->setPort(TW::L, mux.inputs[11]);
cell->setPort(TW::M, mux.inputs[12]);
cell->setPort(TW::N, mux.inputs[13]);
cell->setPort(TW::O, mux.inputs[14]);
cell->setPort(TW::P, mux.inputs[15]);
cell->setPort(TW::S, mux.selects[0]);
cell->setPort(TW::T, mux.selects[1]);
cell->setPort(TW::U, mux.selects[2]);
cell->setPort(TW::V, mux.selects[3]);
cell->setPort(TW::Y, bit);
return;
}

2
passes/techmap/nlutmap.cc
View file

@ -85,7 +85,7 @@ struct NlutmapWorker
if (cell->type != ID($lut) || mapped_cells.count(cell))
continue;
if (GetSize(cell->getPort(ID::A)) == lut_size || lut_size == 2)
if (GetSize(cell->getPort(TW::A)) == lut_size || lut_size == 2)
candidate_ratings[cell] = 0;
for (auto &conn : cell->connections())

10
passes/techmap/pmuxtree.cc
View file

@ -92,18 +92,18 @@ struct PmuxtreePass : public Pass {
if (cell->type != ID($pmux))
continue;
SigSpec sig_data = cell->getPort(ID::B);
SigSpec sig_sel = cell->getPort(ID::S);
SigSpec sig_data = cell->getPort(TW::B);
SigSpec sig_sel = cell->getPort(TW::S);
if (!cell->getPort(ID::A).is_fully_undef()) {
sig_data.append(cell->getPort(ID::A));
if (!cell->getPort(TW::A).is_fully_undef()) {
sig_data.append(cell->getPort(TW::A));
SigSpec sig_sel_or = module->ReduceOr(NEW_ID, sig_sel);
sig_sel.append(module->Not(NEW_ID, sig_sel_or));
}
SigSpec result, result_or;
result = recursive_mux_generator(module, sig_data, sig_sel, result_or);
module->connect(cell->getPort(ID::Y), result);
module->connect(cell->getPort(TW::Y), result);
module->remove(cell);
}
}

10
passes/techmap/shregmap.cc
View file

@ -72,12 +72,12 @@ struct ShregmapTechGreenpak4 : ShregmapTech
bool fixup(Cell *cell, dict<int, SigBit> &taps)
{
auto D = cell->getPort(ID::D);
auto C = cell->getPort(ID::C);
auto D = cell->getPort(TW::D);
auto C = cell->getPort(TW::C);
auto newcell = cell->module->addCell(NEW_ID, ID(GP_SHREG));
auto newcell = cell->module->addCell(NEW_TWINE, ID(GP_SHREG));
newcell->setPort(ID(nRST), State::S1);
newcell->setPort(ID::CLK, C);
newcell->setPort(TW::CLK, C);
newcell->setPort(ID(IN), D);
int i = 0;
@ -142,7 +142,7 @@ struct ShregmapWorker
// so that it can be identified as another chain
// (omitting this common flop)
// Link: https://github.com/YosysHQ/yosys/pull/1085
Wire *wire = module->addWire(NEW_ID);
Wire *wire = module->addWire(NEW_TWINE);
module->connect(wire, d_bit);
sigmap.add(wire, d_bit);
sigbit_chain_next.insert(std::make_pair(wire, cell));

226
passes/techmap/simplemap.cc
View file

@ -34,23 +34,23 @@ static void transfer_src (Cell* to, const Cell* from) {
void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (sig_a.has_const(State::Sz)) {
SigSpec new_a;
@ -72,8 +72,8 @@ void simplemap_buf(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
@ -82,9 +82,9 @@ void simplemap_pos(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (cell->type != ID($bweqx)) {
sig_a.extend_u0(GetSize(sig_y), cell->parameters.at(ID::A_SIGNED).as_bool());
@ -100,18 +100,18 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell)
log_assert(!gate_type.empty());
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type);
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_b[i]);
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (sig_y.size() == 0)
return;
@ -142,7 +142,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
while (sig_a.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig_a.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE, sig_a.size() / 2);
for (int i = 0; i < sig_a.size(); i += 2)
{
@ -151,11 +151,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type);
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_a[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_a[i+1]);
gate->setPort(TW::Y, sig_t[i/2]);
last_output_cell = gate;
}
@ -163,11 +163,11 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
}
if (cell->type == ID($reduce_xnor)) {
RTLIL::SigSpec sig_t = module->addWire(NEW_ID);
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_t);
gate->setPort(TW::A, sig_a);
gate->setPort(TW::Y, sig_t);
last_output_cell = gate;
sig_a = sig_t;
}
@ -175,7 +175,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell)
if (last_output_cell == NULL) {
module->connect(RTLIL::SigSig(sig_y, sig_a));
} else {
last_output_cell->setPort(ID::Y, sig_y);
last_output_cell->setPort(TW::Y, sig_y);
}
}
@ -183,7 +183,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
{
while (sig.size() > 1)
{
RTLIL::SigSpec sig_t = module->addWire(NEW_ID, sig.size() / 2);
RTLIL::SigSpec sig_t = module->addWire(NEW_TWINE, sig.size() / 2);
for (int i = 0; i < sig.size(); i += 2)
{
@ -192,11 +192,11 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
continue;
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_OR_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig[i]);
gate->setPort(ID::B, sig[i+1]);
gate->setPort(ID::Y, sig_t[i/2]);
gate->setPort(TW::A, sig[i]);
gate->setPort(TW::B, sig[i+1]);
gate->setPort(TW::Y, sig_t[i/2]);
}
sig = sig_t;
@ -208,10 +208,10 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell
void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
logic_reduce(module, sig_a, cell);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (sig_y.size() == 0)
return;
@ -221,21 +221,21 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell)
sig_y = sig_y.extract(0, 1);
}
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_NOT_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a);
gate->setPort(ID::Y, sig_y);
gate->setPort(TW::A, sig_a);
gate->setPort(TW::Y, sig_y);
}
void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
logic_reduce(module, sig_a, cell);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
logic_reduce(module, sig_b, cell);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
if (sig_y.size() == 0)
return;
@ -250,28 +250,28 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell)
if (cell->type == ID($logic_or)) gate_type = ID($_OR_);
log_assert(!gate_type.empty());
RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type);
RTLIL::Cell *gate = module->addCell(NEW_TWINE, gate_type);
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a);
gate->setPort(ID::B, sig_b);
gate->setPort(ID::Y, sig_y);
gate->setPort(TW::A, sig_a);
gate->setPort(TW::B, sig_b);
gate->setPort(TW::Y, sig_y);
}
void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
bool is_signed = cell->parameters.at(ID::A_SIGNED).as_bool();
bool is_ne = cell->type.in(ID($ne), ID($nex));
RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::SigSpec xor_out = module->addWire(NEW_TWINE, max(GetSize(sig_a), GetSize(sig_b)));
RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed);
transfer_src(xor_cell, cell);
simplemap_bitop(module, xor_cell);
module->remove(xor_cell);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID);
RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_TWINE);
RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out);
transfer_src(reduce_cell, cell);
simplemap_reduce(module, reduce_cell);
@ -287,101 +287,101 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell)
void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::S, cell->getPort(ID::S));
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_b[i]);
gate->setPort(TW::S, cell->getPort(TW::S));
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::B, sig_b[i]);
gate->setPort(ID::S, sig_s[i]);
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::B, sig_b[i]);
gate->setPort(TW::S, sig_s[i]);
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_e = cell->getPort(ID::EN);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_e = cell->getPort(TW::EN);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
for (int i = 0; i < GetSize(sig_y); i++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_TBUF_));
transfer_src(gate, cell);
gate->setPort(ID::A, sig_a[i]);
gate->setPort(ID::E, sig_e);
gate->setPort(ID::Y, sig_y[i]);
gate->setPort(TW::A, sig_a[i]);
gate->setPort(TW::E, sig_e);
gate->setPort(TW::Y, sig_y[i]);
}
}
void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec sel = cell->getPort(ID::S);
SigSpec data = cell->getPort(ID::A);
int width = GetSize(cell->getPort(ID::Y));
SigSpec sel = cell->getPort(TW::S);
SigSpec data = cell->getPort(TW::A);
int width = GetSize(cell->getPort(TW::Y));
for (int idx = 0; idx < GetSize(sel); idx++) {
SigSpec new_data = module->addWire(NEW_ID, GetSize(data)/2);
SigSpec new_data = module->addWire(NEW_TWINE, GetSize(data)/2);
for (int i = 0; i < GetSize(new_data); i += width) {
for (int k = 0; k < width; k++) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(gate, cell);
gate->setPort(ID::A, data[i*2+k]);
gate->setPort(ID::B, data[i*2+width+k]);
gate->setPort(ID::S, sel[idx]);
gate->setPort(ID::Y, new_data[i+k]);
gate->setPort(TW::A, data[i*2+k]);
gate->setPort(TW::B, data[i*2+width+k]);
gate->setPort(TW::S, sel[idx]);
gate->setPort(TW::Y, new_data[i+k]);
}
}
data = new_data;
}
module->connect(cell->getPort(ID::Y), data);
module->connect(cell->getPort(TW::Y), data);
}
void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec lut_ctrl = cell->getPort(ID::A);
SigSpec lut_ctrl = cell->getPort(TW::A);
SigSpec lut_data = cell->getParam(ID::LUT);
lut_data.extend_u0(1 << cell->getParam(ID::WIDTH).as_int());
for (int idx = 0; GetSize(lut_data) > 1; idx++) {
SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2);
SigSpec new_lut_data = module->addWire(NEW_TWINE, GetSize(lut_data)/2);
for (int i = 0; i < GetSize(lut_data); i += 2) {
RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(gate, cell);
gate->setPort(ID::A, lut_data[i]);
gate->setPort(ID::B, lut_data[i+1]);
gate->setPort(ID::S, lut_ctrl[idx]);
gate->setPort(ID::Y, new_lut_data[i/2]);
gate->setPort(TW::A, lut_data[i]);
gate->setPort(TW::B, lut_data[i+1]);
gate->setPort(TW::S, lut_ctrl[idx]);
gate->setPort(TW::Y, new_lut_data[i/2]);
}
lut_data = new_lut_data;
}
module->connect(cell->getPort(ID::Y), lut_data);
module->connect(cell->getPort(TW::Y), lut_data);
}
void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec ctrl = cell->getPort(ID::A);
SigSpec ctrl = cell->getPort(TW::A);
SigSpec table = cell->getParam(ID::TABLE);
int width = cell->getParam(ID::WIDTH).as_int();
@ -406,22 +406,22 @@ void simplemap_sop(RTLIL::Module *module, RTLIL::Cell *cell)
products.append(GetSize(in) > 0 ? module->Eq(NEW_ID, in, pat) : State::S1);
}
module->connect(cell->getPort(ID::Y), module->ReduceOr(NEW_ID, products));
module->connect(cell->getPort(TW::Y), module->ReduceOr(NEW_ID, products));
}
void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
{
int offset = cell->parameters.at(ID::OFFSET).as_int();
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
module->connect(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.size())));
}
void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_ab = cell->getPort(ID::A);
sig_ab.append(cell->getPort(ID::B));
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_ab = cell->getPort(TW::A);
sig_ab.append(cell->getPort(TW::B));
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
module->connect(RTLIL::SigSig(sig_y, sig_ab));
}
@ -437,10 +437,10 @@ void simplemap_ff(RTLIL::Module *, RTLIL::Cell *cell)
void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
int width = GetSize(sig_a);
int s_width = GetSize(sig_s);
@ -454,13 +454,13 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
// Implement: B_AND_BITS = B_AND_S[WIDTH*j+i]
for (int j = 0; j < s_width; j++) {
RTLIL::Cell *and_gate = module->addCell(NEW_ID, ID($_AND_));
RTLIL::Cell *and_gate = module->addCell(NEW_TWINE, ID($_AND_));
transfer_src(and_gate, cell);
and_gate->setPort(ID::A, sig_b[j * width + i]);
and_gate->setPort(ID::B, sig_s[j]);
and_gate->setPort(TW::A, sig_b[j * width + i]);
and_gate->setPort(TW::B, sig_s[j]);
RTLIL::SigSpec and_y = module->addWire(NEW_ID, 1);
and_gate->setPort(ID::Y, and_y);
RTLIL::SigSpec and_y = module->addWire(NEW_TWINE, 1);
and_gate->setPort(TW::Y, and_y);
b_and_bits.append(and_y);
}
@ -468,12 +468,12 @@ void simplemap_pmux(RTLIL::Module *module, RTLIL::Cell *cell)
logic_reduce(module, b_and_bits, cell);
// Implement: Y[i] = |S ? Y_B[i] : A[i]
RTLIL::Cell *mux_gate = module->addCell(NEW_ID, ID($_MUX_));
RTLIL::Cell *mux_gate = module->addCell(NEW_TWINE, ID($_MUX_));
transfer_src(mux_gate, cell);
mux_gate->setPort(ID::A, sig_a[i]);
mux_gate->setPort(ID::B, b_and_bits);
mux_gate->setPort(ID::S, any_s);
mux_gate->setPort(ID::Y, sig_y[i]);
mux_gate->setPort(TW::A, sig_a[i]);
mux_gate->setPort(TW::B, b_and_bits);
mux_gate->setPort(TW::S, any_s);
mux_gate->setPort(TW::Y, sig_y[i]);
}
}

2
passes/techmap/techmap.cc
View file

@ -247,7 +247,7 @@ struct TechmapWorker
for (auto &it : cell->connections())
{
IdString portname = it.first;
TwineRef portname = it.first;
if (positional_ports.count(portname) > 0)
portname = positional_ports.at(portname);
if (tpl->wire(portname) == nullptr || tpl->wire(portname)->port_id == 0) {

40
passes/techmap/tribuf.cc
View file

@ -66,38 +66,38 @@ struct TribufWorker {
for (auto cell : module->selected_cells())
{
if (cell->type == ID($tribuf))
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
if (cell->type == ID($_TBUF_))
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
if (cell->type.in(ID($mux), ID($_MUX_)))
{
IdString en_port = cell->type == ID($mux) ? ID::EN : ID::E;
IdString tri_type = cell->type == ID($mux) ? ID($tribuf) : ID($_TBUF_);
if (is_all_z(cell->getPort(ID::A)) && is_all_z(cell->getPort(ID::B))) {
if (is_all_z(cell->getPort(TW::A)) && is_all_z(cell->getPort(TW::B))) {
module->remove(cell);
continue;
}
if (is_all_z(cell->getPort(ID::A))) {
cell->setPort(ID::A, cell->getPort(ID::B));
cell->setPort(en_port, cell->getPort(ID::S));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
if (is_all_z(cell->getPort(TW::A))) {
cell->setPort(TW::A, cell->getPort(TW::B));
cell->setPort(en_port, cell->getPort(TW::S));
cell->unsetPort(TW::B);
cell->unsetPort(TW::S);
cell->type = tri_type;
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
continue;
}
if (is_all_z(cell->getPort(ID::B))) {
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(ID::S)));
cell->unsetPort(ID::B);
cell->unsetPort(ID::S);
if (is_all_z(cell->getPort(TW::B))) {
cell->setPort(en_port, module->Not(NEW_ID, cell->getPort(TW::S)));
cell->unsetPort(TW::B);
cell->unsetPort(TW::S);
cell->type = tri_type;
tribuf_cells[sigmap(cell->getPort(ID::Y))].push_back(cell);
tribuf_cells[sigmap(cell->getPort(TW::Y))].push_back(cell);
module->design->scratchpad_set_bool("tribuf.added_something", true);
continue;
}
@ -131,12 +131,12 @@ struct TribufWorker {
if (other_cell == cell)
continue;
else if (other_cell->type == ID($tribuf))
others_s.append(other_cell->getPort(ID::EN));
others_s.append(other_cell->getPort(TW::EN));
else
others_s.append(other_cell->getPort(ID::E));
others_s.append(other_cell->getPort(TW::E));
}
auto cell_s = cell->type == ID($tribuf) ? cell->getPort(ID::EN) : cell->getPort(ID::E);
auto cell_s = cell->type == ID($tribuf) ? cell->getPort(TW::EN) : cell->getPort(TW::E);
auto other_s = module->ReduceOr(NEW_ID, others_s);
@ -155,10 +155,10 @@ struct TribufWorker {
SigSpec pmux_b, pmux_s;
for (auto cell : it.second) {
if (cell->type == ID($tribuf))
pmux_s.append(cell->getPort(ID::EN));
pmux_s.append(cell->getPort(TW::EN));
else
pmux_s.append(cell->getPort(ID::E));
pmux_b.append(cell->getPort(ID::A));
pmux_s.append(cell->getPort(TW::E));
pmux_b.append(cell->getPort(TW::A));
module->remove(cell);
}