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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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44
passes/proc/proc_arst.cc
View file

@ -39,45 +39,45 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
for (auto cell : mod->cells())
{
if (cell->type == ID($reduce_or) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == ID($reduce_or) && cell->getPort(TW::Y) == signal)
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
if (cell->type == ID($reduce_bool) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == ID($reduce_bool) && cell->getPort(TW::Y) == signal)
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
if (cell->type == ID($logic_not) && cell->getPort(ID::Y) == signal) {
if (cell->type == ID($logic_not) && cell->getPort(TW::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
if (cell->type == ID($not) && cell->getPort(ID::Y) == signal) {
if (cell->type == ID($not) && cell->getPort(TW::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (!cell->getPort(ID::A).as_bool())
if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(TW::Y) == signal) {
if (cell->getPort(TW::A).is_fully_const()) {
if (!cell->getPort(TW::A).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::B), ref, polarity);
return check_signal(mod, cell->getPort(TW::B), ref, polarity);
}
if (cell->getPort(ID::B).is_fully_const()) {
if (!cell->getPort(ID::B).as_bool())
if (cell->getPort(TW::B).is_fully_const()) {
if (!cell->getPort(TW::B).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
}
if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (cell->getPort(ID::A).as_bool())
if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(TW::Y) == signal) {
if (cell->getPort(TW::A).is_fully_const()) {
if (cell->getPort(TW::A).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::B), ref, polarity);
return check_signal(mod, cell->getPort(TW::B), ref, polarity);
}
if (cell->getPort(ID::B).is_fully_const()) {
if (cell->getPort(ID::B).as_bool())
if (cell->getPort(TW::B).is_fully_const()) {
if (cell->getPort(TW::B).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
}
}

18
passes/proc/proc_dff.cc
View file

@ -100,11 +100,11 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
cell->parameters[ID::ALOAD_POLARITY] = RTLIL::Const(set_polarity, 1);
cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
cell->setPort(ID::D, sig_in);
cell->setPort(ID::Q, sig_out);
cell->setPort(ID::AD, sig_set);
cell->setPort(ID::CLK, clk);
cell->setPort(ID::ALOAD, set);
cell->setPort(TW::D, sig_in);
cell->setPort(TW::Q, sig_out);
cell->setPort(TW::AD, sig_set);
cell->setPort(TW::CLK, clk);
cell->setPort(TW::ALOAD, set);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type, cell->name,
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
@ -128,12 +128,12 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
}
cell->setPort(ID::D, sig_in);
cell->setPort(ID::Q, sig_out);
cell->setPort(TW::D, sig_in);
cell->setPort(TW::Q, sig_out);
if (arst)
cell->setPort(ID::ARST, *arst);
cell->setPort(TW::ARST, *arst);
if (!clk.empty())
cell->setPort(ID::CLK, clk);
cell->setPort(TW::CLK, clk);
if (!clk.empty())
log(" created %s cell `%s' with %s edge clock", cell->type, cell->name, clk_polarity ? "positive" : "negative");

32
passes/proc/proc_dlatch.cc
View file

@ -48,14 +48,14 @@ struct proc_dlatch_db_t
{
if (cell->type.in(ID($mux), ID($pmux), ID($bwmux)))
{
auto sig_y = sigmap(cell->getPort(ID::Y));
auto sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(sig_y); i++)
mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i);
pool<SigBit> mux_srcbits_pool;
for (auto bit : sigmap(cell->getPort(ID::A)))
for (auto bit : sigmap(cell->getPort(TW::A)))
mux_srcbits_pool.insert(bit);
for (auto bit : sigmap(cell->getPort(ID::B)))
for (auto bit : sigmap(cell->getPort(TW::B)))
mux_srcbits_pool.insert(bit);
vector<SigBit> mux_srcbits_vec;
@ -187,9 +187,9 @@ struct proc_dlatch_db_t
log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux)));
bool is_bwmux = (cell->type == ID($bwmux));
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_s = sigmap(cell->getPort(ID::S));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_s = sigmap(cell->getPort(TW::S));
int width = GetSize(sig_a);
pool<int> children;
@ -197,9 +197,9 @@ struct proc_dlatch_db_t
int n = find_mux_feedback(sig_a[index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_a[index] == needle) {
SigSpec sig = cell->getPort(ID::A);
SigSpec sig = cell->getPort(TW::A);
sig[index] = State::Sx;
cell->setPort(ID::A, sig);
cell->setPort(TW::A, sig);
}
if (!is_bwmux) {
for (int i = 0; i < GetSize(sig_s); i++)
@ -214,9 +214,9 @@ struct proc_dlatch_db_t
n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_b[i*width + index] == needle) {
SigSpec sig = cell->getPort(ID::B);
SigSpec sig = cell->getPort(TW::B);
sig[i*width + index] = State::Sx;
cell->setPort(ID::B, sig);
cell->setPort(TW::B, sig);
}
children.insert(make_inner(sig_s[is_bwmux ? index : i], State::S1, n));
}
@ -268,9 +268,9 @@ struct proc_dlatch_db_t
void fixup_mux(Cell *cell)
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_s = cell->getPort(ID::S);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
SigSpec sig_s = cell->getPort(TW::S);
SigSpec sig_any_valid_b;
SigSpec sig_new_b, sig_new_s;
@ -289,7 +289,7 @@ struct proc_dlatch_db_t
}
if (sig_a.is_fully_undef() && !sig_any_valid_b.empty())
cell->setPort(ID::A, sig_any_valid_b);
cell->setPort(TW::A, sig_any_valid_b);
if (GetSize(sig_new_s) == 1) {
cell->type = ID($mux);
@ -299,8 +299,8 @@ struct proc_dlatch_db_t
cell->setParam(ID::S_WIDTH, GetSize(sig_new_s));
}
cell->setPort(ID::B, sig_new_b);
cell->setPort(ID::S, sig_new_s);
cell->setPort(TW::B, sig_new_b);
cell->setPort(TW::S, sig_new_s);
}
void fixup_muxes()

14
passes/proc/proc_memwr.cc
View file

@ -42,15 +42,15 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
priority_mask.set(prev_port_ids[i], State::S1);
prev_port_ids.push_back(port_id);
RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));
RTLIL::Cell *cell = mod->addCell(NEW_TWINE, ID($memwr_v2));
cell->attributes = memwr.attributes;
cell->setParam(ID::MEMID, Const(memwr.memid.str()));
cell->setParam(ID::ABITS, GetSize(memwr.address));
cell->setParam(ID::WIDTH, GetSize(memwr.data));
cell->setParam(ID::PORTID, port_id);
cell->setParam(ID::PRIORITY_MASK, priority_mask);
cell->setPort(ID::ADDR, memwr.address);
cell->setPort(ID::DATA, memwr.data);
cell->setPort(TW::ADDR, memwr.address);
cell->setPort(TW::DATA, memwr.data);
SigSpec enable = memwr.enable;
for (auto sr2 : proc->syncs) {
if (sr2->type == RTLIL::SyncType::ST0) {
@ -61,17 +61,17 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
enable = mod->Mux(NEW_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal);
}
}
cell->setPort(ID::EN, enable);
cell->setPort(TW::EN, enable);
if (sr->type == RTLIL::SyncType::STa) {
cell->setPort(ID::CLK, State::Sx);
cell->setPort(TW::CLK, State::Sx);
cell->setParam(ID::CLK_ENABLE, State::S0);
cell->setParam(ID::CLK_POLARITY, State::Sx);
} else if (sr->type == RTLIL::SyncType::STp) {
cell->setPort(ID::CLK, sr->signal);
cell->setPort(TW::CLK, sr->signal);
cell->setParam(ID::CLK_ENABLE, State::S1);
cell->setParam(ID::CLK_POLARITY, State::S1);
} else if (sr->type == RTLIL::SyncType::STn) {
cell->setPort(ID::CLK, sr->signal);
cell->setPort(TW::CLK, sr->signal);
cell->setParam(ID::CLK_ENABLE, State::S1);
cell->setParam(ID::CLK_POLARITY, State::S0);
} else {

32
passes/proc/proc_mux.cc
View file

@ -188,9 +188,9 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size());
eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
eq_cell->setPort(ID::A, sig);
eq_cell->setPort(ID::B, comp);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
eq_cell->setPort(TW::A, sig);
eq_cell->setPort(TW::B, comp);
eq_cell->setPort(TW::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
}
}
@ -211,8 +211,8 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
any_cell->setPort(ID::A, cmp_wire);
any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
any_cell->setPort(TW::A, cmp_wire);
any_cell->setPort(TW::Y, RTLIL::SigSpec(ctrl_wire));
}
return RTLIL::SigSpec(ctrl_wire);
@ -243,10 +243,10 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
apply_attrs(mux_cell, sw, cs);
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
mux_cell->setPort(ID::A, else_signal);
mux_cell->setPort(ID::B, when_signal);
mux_cell->setPort(ID::S, ctrl_sig);
mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire));
mux_cell->setPort(TW::A, else_signal);
mux_cell->setPort(TW::B, when_signal);
mux_cell->setPort(TW::S, ctrl_sig);
mux_cell->setPort(TW::Y, RTLIL::SigSpec(result_wire));
last_mux_cell = mux_cell;
return RTLIL::SigSpec(result_wire);
@ -255,24 +255,24 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
log_assert(last_mux_cell != NULL);
log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());
log_assert(when_signal.size() == last_mux_cell->getPort(TW::A).size());
if (when_signal == last_mux_cell->getPort(ID::A))
if (when_signal == last_mux_cell->getPort(TW::A))
return;
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
log_assert(ctrl_sig.size() == 1);
last_mux_cell->type = ID($pmux);
RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
RTLIL::SigSpec new_s = last_mux_cell->getPort(TW::S);
new_s.append(ctrl_sig);
last_mux_cell->setPort(ID::S, new_s);
last_mux_cell->setPort(TW::S, new_s);
RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B);
RTLIL::SigSpec new_b = last_mux_cell->getPort(TW::B);
new_b.append(when_signal);
last_mux_cell->setPort(ID::B, new_b);
last_mux_cell->setPort(TW::B, new_b);
last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size();
last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(TW::S).size();
}
const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)

2
passes/proc/proc_rom.cc
View file

@ -151,7 +151,7 @@ struct RomWorker
}
// Ok, let's do it.
SigSpec rdata = module->addWire(NEW_ID, GetSize(lhs));
SigSpec rdata = module->addWire(NEW_TWINE, GetSize(lhs));
Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits);
mem.attributes = sw->attributes;