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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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50
passes/opt/muxpack.cc
View file

@ -38,11 +38,11 @@ struct ExclusiveDatabase
pool<Cell*> reduce_or;
for (auto cell : module->cells()) {
if (cell->type == ID($eq)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
const_sig = sigmap(cell->getPort(ID::B));
nonconst_sig = sigmap(cell->getPort(TW::A));
const_sig = sigmap(cell->getPort(TW::B));
if (!const_sig.is_fully_const()) {
if (!nonconst_sig.is_fully_const())
continue;
@ -51,10 +51,10 @@ struct ExclusiveDatabase
y_port = y_sig[0];
}
else if (cell->type == ID($logic_not)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
nonconst_sig = sigmap(cell->getPort(TW::A));
const_sig = Const(State::S0, GetSize(nonconst_sig));
y_port = y_sig[0];
}
@ -72,7 +72,7 @@ struct ExclusiveDatabase
for (auto cell : reduce_or) {
nonconst_sig = SigSpec();
std::vector<Const> values;
SigSpec a_port = sigmap(cell->getPort(ID::A));
SigSpec a_port = sigmap(cell->getPort(TW::A));
for (auto bit : a_port) {
auto it = sig_cmp_prev.find(bit);
if (it == sig_cmp_prev.end()) {
@ -90,7 +90,7 @@ struct ExclusiveDatabase
}
if (nonconst_sig.empty())
continue;
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
y_port = y_sig[0];
@ -154,11 +154,11 @@ struct MuxpackWorker
{
if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
{
SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec a_sig = sigmap(cell->getPort(TW::A));
SigSpec b_sig;
if (cell->type == ID($mux))
b_sig = sigmap(cell->getPort(ID::B));
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
b_sig = sigmap(cell->getPort(TW::B));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (sig_chain_next.count(a_sig))
for (auto a_bit : a_sig)
@ -195,9 +195,9 @@ struct MuxpackWorker
{
log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec a_sig = sigmap(cell->getPort(TW::A));
if (cell->type == ID($mux)) {
SigSpec b_sig = sigmap(cell->getPort(ID::B));
SigSpec b_sig = sigmap(cell->getPort(TW::B));
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
goto start_cell;
@ -217,8 +217,8 @@ struct MuxpackWorker
{
Cell *prev_cell = sig_chain_prev.at(a_sig);
log_assert(prev_cell);
SigSpec s_sig = sigmap(cell->getPort(ID::S));
s_sig.append(sigmap(prev_cell->getPort(ID::S)));
SigSpec s_sig = sigmap(cell->getPort(TW::S));
s_sig.append(sigmap(prev_cell->getPort(TW::S)));
if (!excl_db.query(s_sig))
goto start_cell;
}
@ -239,7 +239,7 @@ struct MuxpackWorker
{
chain.push_back(c);
SigSpec y_sig = sigmap(c->getPort(ID::Y));
SigSpec y_sig = sigmap(c->getPort(TW::Y));
if (sig_chain_next.count(y_sig) == 0)
break;
@ -278,28 +278,28 @@ struct MuxpackWorker
pmux_count += 1;
first_cell->type = ID($pmux);
SigSpec b_sig = first_cell->getPort(ID::B);
SigSpec s_sig = first_cell->getPort(ID::S);
SigSpec b_sig = first_cell->getPort(TW::B);
SigSpec s_sig = first_cell->getPort(TW::S);
for (int i = 1; i < cases; i++) {
Cell* prev_cell = chain[cursor+i-1];
Cell* cursor_cell = chain[cursor+i];
if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
b_sig.append(cursor_cell->getPort(ID::B));
s_sig.append(cursor_cell->getPort(ID::S));
if (sigmap(prev_cell->getPort(TW::Y)) == sigmap(cursor_cell->getPort(TW::A))) {
b_sig.append(cursor_cell->getPort(TW::B));
s_sig.append(cursor_cell->getPort(TW::S));
}
else {
log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
b_sig.append(cursor_cell->getPort(TW::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(TW::S)));
}
remove_cells.insert(cursor_cell);
}
first_cell->setPort(ID::B, b_sig);
first_cell->setPort(ID::S, s_sig);
first_cell->setPort(TW::B, b_sig);
first_cell->setPort(TW::S, s_sig);
first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
first_cell->setPort(TW::Y, last_cell->getPort(TW::Y));
cursor += cases;
}

26
passes/opt/opt_balance_tree.cc
View file

@ -77,7 +77,7 @@ struct OptBalanceTreeWorker {
// Base case: if we have two sources, create a single cell
if (sources.size() == 2) {
// Create a new cell of the same type
Cell* new_cell = module->addCell(NEW_ID, cell_type);
Cell* new_cell = module->addCell(NEW_TWINE, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
@ -88,12 +88,12 @@ struct OptBalanceTreeWorker {
out_width = max(sources[0].size(), sources[1].size()) + 1;
else if (cell_type == ID($mul))
out_width = sources[0].size() + sources[1].size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
Wire* out_wire = module->addWire(NEW_TWINE, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, sources[0]);
new_cell->setPort(ID::B, sources[1]);
new_cell->setPort(ID::Y, out_wire);
new_cell->setPort(TW::A, sources[0]);
new_cell->setPort(TW::B, sources[1]);
new_cell->setPort(TW::Y, out_wire);
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
@ -112,7 +112,7 @@ struct OptBalanceTreeWorker {
SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell);
// Create a cell to combine the two subtrees
Cell* new_cell = module->addCell(NEW_ID, cell_type);
Cell* new_cell = module->addCell(NEW_TWINE, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
@ -123,12 +123,12 @@ struct OptBalanceTreeWorker {
out_width = max(left_tree.size(), right_tree.size()) + 1;
else if (cell_type == ID($mul))
out_width = left_tree.size() + right_tree.size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
Wire* out_wire = module->addWire(NEW_TWINE, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, left_tree);
new_cell->setPort(ID::B, right_tree);
new_cell->setPort(ID::Y, out_wire);
new_cell->setPort(TW::A, left_tree);
new_cell->setPort(TW::B, right_tree);
new_cell->setPort(TW::Y, out_wire);
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
@ -185,7 +185,7 @@ struct OptBalanceTreeWorker {
// BFS, following all chains until they hit a cell of a different type
// Pick the longest one
auto y = sigmap(cell->getPort(ID::Y));
auto y = sigmap(cell->getPort(TW::Y));
pool<Cell*> sinks;
pool<Cell*> current_loads = sig_to_sink[y];
pool<Cell*> next_loads;
@ -202,7 +202,7 @@ struct OptBalanceTreeWorker {
continue;
}
auto xy = sigmap(x->getPort(ID::Y));
auto xy = sigmap(x->getPort(TW::Y));
// If this signal drives a port, add it to the sinks
// (even though it may not be the end of a chain)
@ -300,7 +300,7 @@ struct OptBalanceTreeWorker {
SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell);
// Connect the tree output to the head cell's output
SigSpec head_output = sigmap(head_cell->getPort(ID::Y));
SigSpec head_output = sigmap(head_cell->getPort(TW::Y));
int connect_width = std::min(head_output.size(), tree_output.size());
module->connect(head_output.extract(0, connect_width), tree_output.extract(0, connect_width));
if (head_output.size() > tree_output.size()) {

6
passes/opt/opt_clean/cells_all.cc
View file

@ -202,7 +202,7 @@ ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const Sig
if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
std::string msg = stringf("Driver-driver conflict "
"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), actx.mod->name.unescape());
log_signal(raw_bit), cell->name.unescape(), actx.mod->design->twines.str(it2.first), log_signal(bit), actx.mod->name);
logs.logs.insert(ctx, {wire_map(raw_bit), msg});
}
if (bit.wire != nullptr)
@ -304,7 +304,7 @@ pool<Cell*> all_unused_cells(const Module *mod, const CellAnalysis& analysis, Wi
});
for (int cell_index : sharded_unused_cells)
unused_cells.insert(mod->cell_at(cell_index));
unused_cells.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
unused_cells.sort(RTLIL::sort_by_name<RTLIL::Cell>());
return unused_cells;
}
@ -314,7 +314,7 @@ void remove_cells(RTLIL::Module* mod, FfInitVals& ffinit, const pool<Cell*>& cel
log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
mod->design->scratchpad_set_bool("opt.did_something", true);
if (cell->is_builtin_ff())
ffinit.remove_init(cell->getPort(ID::Q));
ffinit.remove_init(cell->getPort(TW::Q));
mod->remove(cell);
stats.count_rm_cells++;
}

18
passes/opt/opt_clean/cells_temp.cc
View file

@ -27,8 +27,8 @@ bool is_signed(RTLIL::Cell* cell) {
}
bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec y = cell->getPort(TW::Y);
a.extend_u0(GetSize(y), is_signed(cell));
if (a.has_const(State::Sz)) {
@ -58,20 +58,20 @@ bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose
if (verbose) {
if (cell->type == ID($connect)) {
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B)));
} else if (cell->type == ID($input_port)) {
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
log_signal(cell->getPort(TW::Y)));
} else if (cell->type == ID($output_port)) {
log_debug(" removing output port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::A)));
} else if (cell->type == ID($public)) {
log_debug(" removing public wire marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::A)));
} else {
did_something = true;
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::Y)), log_signal(cell->getPort(TW::A)));
}
}
mod->remove(cell);
@ -93,8 +93,8 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
if (trim_buf(cell, new_connections, ctx))
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec b = cell->getPort(TW::B);
if (a.has_const() && !b.has_const())
std::swap(a, b);
new_connections.insert(ctx, {a, b});

4
passes/opt/opt_clean/inits.cc
View file

@ -27,9 +27,9 @@ ShardedVector<std::pair<SigBit, State>> build_inits(AnalysisContext& actx) {
actx.subpool.run([&results, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int i : ctx.item_range(actx.mod->cells_size())) {
RTLIL::Cell *cell = actx.mod->cell_at(i);
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q))
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(TW::Q))
{
SigSpec sig = cell->getPort(ID::Q);
SigSpec sig = cell->getPort(TW::Q);
for (int i = 0; i < GetSize(sig); i++)
{

4
passes/opt/opt_clean/wires.cc
View file

@ -178,7 +178,7 @@ bool check_all(const ShardedSigPool &sigs, const RTLIL::SigSpec &spec) {
struct UpdateConnection {
RTLIL::Cell *cell;
RTLIL::IdString port;
TwineRef port;
RTLIL::SigSpec spec;
};
void fixup_cell_ports(ShardedVector<UpdateConnection> &update_connections)
@ -256,7 +256,7 @@ struct SigConnKinds {
// see commit message e36c71b5
bool clk2fflogic = cell->get_bool_attribute(ID::clk2fflogic);
for (auto &[port, sig] : cell->connections())
if (clk2fflogic ? port == ID::D : clean_ctx.ct_all.cell_output(cell->type, port))
if (clk2fflogic ? port == TW::D : clean_ctx.ct_all.cell_output(cell->type, port))
add_spec(raw_register_builder, ctx, sig);
}
for (auto &[_, sig] : cell->connections())

14
passes/opt/opt_demorgan.cc
View file

@ -38,7 +38,7 @@ void demorgan_worker(
if( (cell->type != ID($reduce_and)) && (cell->type != ID($reduce_or)) )
return;
auto insig = sigmap(cell->getPort(ID::A));
auto insig = sigmap(cell->getPort(TW::A));
if (GetSize(insig) < 1)
return;
@ -99,7 +99,7 @@ void demorgan_worker(
//We are NOT inverted! Add an inverter
if(!srcinv)
{
auto inverted_b = m->addWire(NEW_ID);
auto inverted_b = m->addWire(NEW_TWINE);
m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b));
insig[i] = inverted_b;
}
@ -107,7 +107,7 @@ void demorgan_worker(
//We ARE inverted - bypass it
//Don't automatically delete the inverter since other stuff might still use it
else
insig[i] = srcinv->getPort(ID::A);
insig[i] = srcinv->getPort(TW::A);
}
//Cosmetic fixup: If our input is just a scrambled version of one bus, rearrange it
@ -155,7 +155,7 @@ void demorgan_worker(
}
//Push the new input signal back to the reduction (after bypassing/adding inverters)
cell->setPort(ID::A, insig);
cell->setPort(TW::A, insig);
//Change the cell type
if(cell->type == ID($reduce_and))
@ -165,10 +165,10 @@ void demorgan_worker(
//don't change XOR
//Add an inverter to the output
auto inverted_output = cell->getPort(ID::Y);
auto uninverted_output = m->addWire(NEW_ID);
auto inverted_output = cell->getPort(TW::Y);
auto uninverted_output = m->addWire(NEW_TWINE);
m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
cell->setPort(ID::Y, uninverted_output);
cell->setPort(TW::Y, uninverted_output);
}
struct OptDemorganPass : public Pass {

86
passes/opt/opt_dff.cc
View file

@ -77,29 +77,29 @@ struct OptDffWorker
SigSpec create_not(SigSpec a, bool is_fine) {
if (is_fine)
return module->NotGate(NEW_ID, a);
return module->NotGate(NEW_TWINE, a);
else
return module->Not(NEW_ID, a);
return module->Not(NEW_TWINE, a);
}
SigSpec create_and(SigSpec a, SigSpec b, bool is_fine) {
if (is_fine)
return module->AndGate(NEW_ID, a, b);
return module->AndGate(NEW_TWINE, a, b);
else
return module->And(NEW_ID, a, b);
return module->And(NEW_TWINE, a, b);
}
void create_mux_to_output(SigSpec a, SigSpec b, SigSpec sel, SigSpec y, bool pol, bool is_fine) {
if (is_fine) {
if (pol)
module->addMuxGate(NEW_ID, a, b, sel, y);
module->addMuxGate(NEW_TWINE, a, b, sel, y);
else
module->addMuxGate(NEW_ID, b, a, sel, y);
module->addMuxGate(NEW_TWINE, b, a, sel, y);
} else {
if (pol)
module->addMux(NEW_ID, a, b, sel, y);
module->addMux(NEW_TWINE, a, b, sel, y);
else
module->addMux(NEW_ID, b, a, sel, y);
module->addMux(NEW_TWINE, b, a, sel, y);
}
}
@ -124,7 +124,7 @@ struct OptDffWorker
for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
}
@ -163,9 +163,9 @@ struct OptDffWorker
return ret; // D not driven by MUX / MUX drives multiple loads
cell_int_t mbit = bit2mux.at(d);
RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(ID::S));
RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(TW::B));
RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(TW::S));
int width = GetSize(sig_a), index = mbit.second;
// Traverse MUX tree
@ -173,9 +173,9 @@ struct OptDffWorker
if (path.count(sig_s[i]) && path.at(sig_s[i])) {
ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::B));
s[i*width + index] = RTLIL::Sx;
mbit.first->setPort(ID::B, s);
mbit.first->setPort(TW::B, s);
}
return ret;
@ -197,9 +197,9 @@ struct OptDffWorker
ret.insert(pat);
if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::B));
s[i*width + index] = RTLIL::Sx;
mbit.first->setPort(ID::B, s);
mbit.first->setPort(TW::B, s);
}
}
@ -208,9 +208,9 @@ struct OptDffWorker
ret.insert(pat);
if (sig_a[index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::A));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::A));
s[index] = RTLIL::Sx;
mbit.first->setPort(ID::A, s);
mbit.first->setPort(TW::A, s);
}
return ret;
@ -232,8 +232,8 @@ struct OptDffWorker
s2.append(it.second);
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = module->addNe(NEW_TWINE, s1, s2, y);
maybe_simplemap(c, make_gates);
or_input.append(y);
}
@ -249,8 +249,8 @@ struct OptDffWorker
if (GetSize(or_input) == 0) return ctrl_t(State::S1, true);
if (GetSize(or_input) == 1) return ctrl_t(or_input, true);
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = module->addReduceAnd(NEW_TWINE, or_input, y);
maybe_simplemap(c, make_gates);
return ctrl_t(y, true);
}
@ -273,10 +273,10 @@ struct OptDffWorker
or_input.append(create_not(item.first, make_gates));
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = final_pol
? module->addReduceOr(NEW_ID, or_input, y)
: module->addReduceAnd(NEW_ID, or_input, y);
? module->addReduceOr(NEW_TWINE, or_input, y)
: module->addReduceAnd(NEW_TWINE, or_input, y);
maybe_simplemap(c, make_gates);
return ctrl_t(y, final_pol);
}
@ -309,9 +309,9 @@ struct OptDffWorker
if (!ff.pol_clr)
module->connect(ff.sig_q[i], ff.sig_clr[i]);
else if (ff.is_fine)
module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNotGate(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
else
module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNot(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, cell, cell->type.unescape(), module);
sr_removed = true;
@ -406,22 +406,22 @@ struct OptDffWorker
SigSpec tmp;
if (ff.is_fine) {
tmp = ff.pol_set
? module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set)
: module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set);
? module->MuxGate(NEW_TWINE, ff.sig_ad, State::S1, ff.sig_set)
: module->MuxGate(NEW_TWINE, State::S1, ff.sig_ad, ff.sig_set);
if (ff.pol_clr)
module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEW_TWINE, tmp, State::S0, ff.sig_clr, ff.sig_q);
else
module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEW_TWINE, State::S0, tmp, ff.sig_clr, ff.sig_q);
} else {
tmp = ff.pol_set
? module->Or(NEW_ID, ff.sig_ad, ff.sig_set)
: module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set));
? module->Or(NEW_TWINE, ff.sig_ad, ff.sig_set)
: module->Or(NEW_TWINE, ff.sig_ad, module->Not(NEW_TWINE, ff.sig_set));
if (ff.pol_clr)
module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);
module->addAnd(NEW_TWINE, tmp, module->Not(NEW_TWINE, ff.sig_clr), ff.sig_q);
else
module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);
module->addAnd(NEW_TWINE, tmp, ff.sig_clr, ff.sig_q);
}
} else if (ff.has_arst) {
create_mux_to_output(ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q, ff.pol_arst, ff.is_fine);
@ -566,12 +566,12 @@ struct OptDffWorker
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
if (GetSize(mbit.first->getPort(ID::S)) != 1)
if (GetSize(mbit.first->getPort(TW::S)) != 1)
break;
SigBit s = sigmap(mbit.first->getPort(ID::S));
SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
SigBit s = sigmap(mbit.first->getPort(TW::S));
SigBit a = sigmap(mbit.first->getPort(TW::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(TW::B)[mbit.second]);
if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1))
break;
@ -649,12 +649,12 @@ struct OptDffWorker
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
if (GetSize(mbit.first->getPort(ID::S)) != 1)
if (GetSize(mbit.first->getPort(TW::S)) != 1)
break;
SigBit s = sigmap(mbit.first->getPort(ID::S));
SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
SigBit s = sigmap(mbit.first->getPort(TW::S));
SigBit a = sigmap(mbit.first->getPort(TW::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(TW::B)[mbit.second]);
if (a == ff.sig_q[i]) {
enables.insert(ctrl_t(s, true));

74
passes/opt/opt_expr.cc
View file

@ -243,7 +243,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
continue;
int group_size = GetSize(per_kind[kind]);
RTLIL::SigSpec new_y = patcher.addWire(NEW_ID, group_size);
RTLIL::SigSpec new_y = patcher.addWire(NEW_TWINE, group_size);
RTLIL::SigSpec new_a, new_b;
int slot = 0;
@ -295,9 +295,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
else if (new_a[j] == State::S0 || new_a[j] == State::S1) {
undef_a.append(new_a[j]);
if (cell->type == ID($xor))
undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_ID, new_b[j]).as_bit() : new_b[j]);
undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_TWINE, new_b[j]).as_bit() : new_b[j]);
else if (cell->type == ID($xnor))
undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_ID, new_b[j]).as_bit());
undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_TWINE, new_b[j]).as_bit());
else log_abort();
undef_y.append(new_y[j]);
}
@ -324,7 +324,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_y = std::move(def_y);
}
RTLIL::Cell *c = patcher.addCell(NEW_ID, cell->type);
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
c->setPort(TW::A, new_a);
c->parameters[ID::A_WIDTH] = new_a.size();
@ -687,7 +687,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
sig_y.append(RTLIL::Const(State::S0, width-1));
patcher.patch(cell, TW::Y, sig_y, "xor_buffer");
} else {
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_TWINE, sig_a) : patcher.Not(NEW_TWINE, sig_a);
sig_y.append(RTLIL::Const(State::S0, width-1));
patcher.patch(cell, TW::Y, sig_y, "xor_buffer");
}
@ -699,7 +699,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
sig_y.append(RTLIL::Const(State::S1, width-1));
patcher.patch(cell, TW::Y, sig_y, "xnor_buffer");
} else {
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_TWINE, sig_a) : patcher.Not(NEW_TWINE, sig_a);
sig_y.append(RTLIL::Const(State::S1, width-1));
patcher.patch(cell, TW::Y, sig_y, "xnor_buffer");
}
@ -771,7 +771,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!b_group_1.empty()) y_new_1 = b_group_1;
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.And(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.And(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else
y_new_x = Const(State::S0, GetSize(b_group_x));
}
@ -780,16 +780,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!b_group_1.empty()) y_new_1 = Const(State::S1, GetSize(b_group_1));
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.Or(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.Or(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else
y_new_x = Const(State::S1, GetSize(b_group_x));
}
} else if (cell->type.in(ID($xor), ID($xnor))) {
if (!b_group_0.empty()) y_new_0 = b_group_0;
if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_ID, b_group_1);
if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_TWINE, b_group_1);
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.Xor(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.Xor(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor
y_new_x = Const(State::Sx, GetSize(b_group_x));
}
@ -849,11 +849,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec y_new_0, y_new_1;
if (flip) {
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_ID, b_group_0, patcher.Not(NEW_ID, s_group_0));
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_ID, b_group_1, s_group_1);
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_TWINE, b_group_0, patcher.Not(NEW_TWINE, s_group_0));
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_TWINE, b_group_1, s_group_1);
} else {
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_ID, b_group_0, s_group_0);
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_ID, b_group_1, patcher.Not(NEW_ID, s_group_1));
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_TWINE, b_group_0, s_group_0);
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_TWINE, b_group_1, patcher.Not(NEW_TWINE, s_group_1));
}
RTLIL::SigSpec new_sig_y(width);
@ -1059,12 +1059,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigBit a = sig_a[i];
if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
module->connect(sig_y[i], a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_x[i], ci ? module->Not(NEW_TWINE, a).as_bit() : a);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else if (a == (ci ? State::S1 : State::S0)) {
module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_y[i], bi ? module->Not(NEW_TWINE, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_TWINE, b).as_bit() : b);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else
@ -1486,7 +1486,7 @@ skip_fine_alu:
/* sub, b is 0 */
RTLIL::SigSpec a = cell->getPort(TW::A);
a.extend_u0(y_width, is_signed);
new_x = patcher.Not(NEW_ID, a);
new_x = patcher.Not(NEW_TWINE, a);
new_co = RTLIL::Const(State::S1, y_width);
a_port = cell->getPort(TW::A);
a_port_signed = a_signed;
@ -1503,8 +1503,8 @@ skip_fine_alu:
}
IdString new_type = arith_inverse ? ID($neg) : ID($pos);
SigSpec new_y = patcher.addWire(NEW_ID, y_width);
Cell *new_cell = patcher.addCell(NEW_ID, new_type);
SigSpec new_y = patcher.addWire(NEW_TWINE, y_width);
Cell *new_cell = patcher.addCell(NEW_TWINE, new_type);
new_cell->setPort(TW::A, a_port);
new_cell->setPort(TW::Y, new_y);
new_cell->setParam(ID::A_WIDTH, a_port_width);
@ -1805,8 +1805,8 @@ skip_identity:
OptExprPatcher patcher(module, &assign_map);
int a_width = cell->parameters[ID::A_WIDTH].as_int();
SigSpec y_wire = patcher.addWire(NEW_ID, y_size);
Cell *mul = patcher.addCell(NEW_ID, ID($mul));
SigSpec y_wire = patcher.addWire(NEW_TWINE, y_size);
Cell *mul = patcher.addCell(NEW_TWINE, ID($mul));
mul->setPort(TW::A, Const(bit_idx, a_width));
mul->setPort(TW::B, cell->getPort(TW::B));
mul->setPort(TW::Y, y_wire);
@ -1816,8 +1816,8 @@ skip_identity:
mul->parameters[ID::B_SIGNED] = cell->parameters[ID::B_SIGNED];
mul->parameters[ID::Y_WIDTH] = y_size;
SigSpec new_y = patcher.addWire(NEW_ID, y_size);
patcher.addShl(NEW_ID, Const(State::S1, 1), y_wire, new_y);
SigSpec new_y = patcher.addWire(NEW_TWINE, y_size);
patcher.addShl(NEW_TWINE, Const(State::S1, 1), y_wire, new_y);
patcher.patch(cell, TW::Y, new_y, "pow_to_mul_shl");
goto next_cell;
@ -1954,13 +1954,13 @@ skip_identity:
// Truncating division is the same as flooring division, except when
// the result is negative and there is a remainder - then trunc = floor + 1
if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) {
Wire *flooring = module->addWire(NEW_ID, sig_y.size());
Wire *flooring = module->addWire(NEW_TWINE, sig_y.size());
cell->setPort(TW::Y, flooring);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero);
module->addAdd(NEW_ID, flooring, should_add, sig_y);
SigSpec rem_nonzero = module->ReduceOr(NEW_TWINE, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_TWINE, a_sign, rem_nonzero);
module->addAdd(NEW_TWINE, flooring, should_add, sig_y);
}
cell->check();
@ -1980,8 +1980,8 @@ skip_identity:
SigSpec truncating = sig_a.extract(0, exp);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = patcher.ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec extend_bit = patcher.And(NEW_ID, a_sign, rem_nonzero);
SigSpec rem_nonzero = patcher.ReduceOr(NEW_TWINE, sig_a.extract(0, exp));
SigSpec extend_bit = patcher.And(NEW_TWINE, a_sign, rem_nonzero);
truncating.append(extend_bit);
SigSpec new_y = truncating;
@ -2071,11 +2071,11 @@ skip_identity:
int sz = cur - prev;
bool last = cur == GetSize(sig_y);
SigSpec slice_y = patcher.addWire(NEW_ID, sz);
SigSpec slice_x = patcher.addWire(NEW_ID, sz);
SigSpec slice_co = patcher.addWire(NEW_ID, sz);
SigSpec slice_y = patcher.addWire(NEW_TWINE, sz);
SigSpec slice_x = patcher.addWire(NEW_TWINE, sz);
SigSpec slice_co = patcher.addWire(NEW_TWINE, sz);
RTLIL::Cell *c = patcher.addCell(NEW_ID, cell->type);
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
c->setPort(TW::A, sig_a.extract(prev, sz));
c->setPort(TW::B, sig_b.extract(prev, sz));
c->setPort(TW::BI, sig_bi);
@ -2248,14 +2248,14 @@ skip_alu_split:
{
condition = stringf("unsigned X<%s", log_signal(const_sig));
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
replace_sig[0] = patcher.LogicNot(NEW_ID, var_high_sig).as_bit();
replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_high_sig).as_bit();
replace = true;
}
if (cmp_type == ID($ge))
{
condition = stringf("unsigned X>=%s", log_signal(const_sig));
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
replace_sig[0] = patcher.ReduceOr(NEW_ID, var_high_sig).as_bit();
replace_sig[0] = patcher.ReduceOr(NEW_TWINE, var_high_sig).as_bit();
replace = true;
}
}
@ -2297,7 +2297,7 @@ skip_alu_split:
{
condition = "signed X>=0";
replacement = stringf("X[%d]", var_width - 1);
replace_sig[0] = patcher.LogicNot(NEW_ID, var_sig[var_width - 1]).as_bit();
replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_sig[var_width - 1]).as_bit();
replace = true;
}
}

14
passes/opt/opt_ffinv.cc
View file

@ -84,12 +84,12 @@ struct OptFfInvWorker
}
ff.flip_rst_bits({0});
ff.sig_d = d_inv->getPort(ID::A);
ff.sig_d = d_inv->getPort(TW::A);
for (Cell *lut: q_luts) {
if (lut->type == ID($lut)) {
int flip_mask = 0;
SigSpec sig_a = lut->getPort(ID::A);
SigSpec sig_a = lut->getPort(TW::A);
for (int i = 0; i < GetSize(sig_a); i++) {
if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q[0])) {
flip_mask |= 1 << i;
@ -101,14 +101,14 @@ struct OptFfInvWorker
new_mask_builder.push_back(mask[j ^ flip_mask]);
Const new_mask = new_mask_builder.build();
if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
module->connect(lut->getPort(ID::Y), ff.sig_q);
module->connect(lut->getPort(TW::Y), ff.sig_q);
module->remove(lut);
} else {
lut->setParam(ID::LUT, new_mask);
}
} else {
// it was an inverter
module->connect(lut->getPort(ID::Y), ff.sig_q);
module->connect(lut->getPort(TW::Y), ff.sig_q);
module->remove(lut);
}
}
@ -173,7 +173,7 @@ struct OptFfInvWorker
if (!q_inv) return false;
ff.flip_rst_bits({0});
ff.sig_q = q_inv->getPort(ID::Y);
ff.sig_q = q_inv->getPort(TW::Y);
module->remove(q_inv);
if (d_lut->type == ID($lut)) {
@ -188,12 +188,12 @@ struct OptFfInvWorker
Const new_mask = new_mask_builder.build();
d_lut->setParam(ID::LUT, new_mask);
if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {
module->connect(ff.sig_d, d_lut->getPort(ID::A));
module->connect(ff.sig_d, d_lut->getPort(TW::A));
module->remove(d_lut);
}
} else {
// it was an inverter
module->connect(ff.sig_d, d_lut->getPort(ID::A));
module->connect(ff.sig_d, d_lut->getPort(TW::A));
module->remove(d_lut);
}

4
passes/opt/opt_hier.cc
View file

@ -137,7 +137,7 @@ struct ModuleIndex {
rhs.replace(constant_outputs);
log_assert(rhs.is_fully_const());
parent.module->connect(value.extract(chunk.offset, chunk.width), rhs);
SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width);
SigSpec dummy = parent.module->addWire(NEW_TWINE_SUFFIX("const_output"), chunk.width);
for (int i = 0; i < chunk.width; i++)
value[chunk.offset + i] = dummy[i];
}
@ -182,7 +182,7 @@ struct ModuleIndex {
severed_port_bits.sort_and_unify();
for (auto chunk : severed_port_bits.chunks()) {
SigSpec &value = instantiation->connections_.at(chunk.wire->name);
SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width);
SigSpec dummy = parent.module->addWire(NEW_TWINE_SUFFIX("tie_together"), chunk.width);
for (int i = 0; i < chunk.width; i++)
value[chunk.offset + i] = dummy[i];
}

28
passes/opt/opt_lut.cc
View file

@ -50,7 +50,7 @@ struct OptLutWorker
bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
{
SigSpec lut_input = sigmap(lut->getPort(ID::A));
SigSpec lut_input = sigmap(lut->getPort(TW::A));
int lut_width = lut->getParam(ID::WIDTH).as_int();
Const lut_table = lut->getParam(ID::LUT);
int lut_index = 0;
@ -113,12 +113,12 @@ struct OptLutWorker
{
if (cell->has_keep_attr())
continue;
SigBit lut_output = cell->getPort(ID::Y);
SigBit lut_output = cell->getPort(TW::Y);
if (lut_output.wire->get_bool_attribute(ID::keep))
continue;
int lut_width = cell->getParam(ID::WIDTH).as_int();
SigSpec lut_input = cell->getPort(ID::A);
SigSpec lut_input = cell->getPort(TW::A);
int lut_arity = 0;
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, module, cell);
@ -218,7 +218,7 @@ struct OptLutWorker
}
auto lut = worklist.pop();
SigSpec lut_input = sigmap(lut->getPort(ID::A));
SigSpec lut_input = sigmap(lut->getPort(TW::A));
pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
vector<SigBit> lut_inputs;
@ -280,7 +280,7 @@ struct OptLutWorker
log_debug(" Not eliminating cell (connected to dedicated logic).\n");
else
{
SigSpec lut_output = lut->getPort(ID::Y);
SigSpec lut_output = lut->getPort(TW::Y);
for (auto &port : index.query_ports(lut_output))
{
if (port.cell != lut && luts.count(port.cell))
@ -317,13 +317,13 @@ struct OptLutWorker
}
auto lutA = worklist.pop();
SigSpec lutA_input = sigmap(lutA->getPort(ID::A));
SigBit lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
SigSpec lutA_input = sigmap(lutA->getPort(TW::A));
SigBit lutA_output = sigmap(lutA->getPort(TW::Y)[0]);
int lutA_width = lutA->getParam(ID::WIDTH).as_int();
int lutA_arity = luts_arity[lutA];
pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
auto lutA_output_ports = index.query_ports(lutA->getPort(ID::Y));
auto lutA_output_ports = index.query_ports(lutA->getPort(TW::Y));
if (lutA_output_ports.size() != 2)
continue;
@ -335,15 +335,15 @@ struct OptLutWorker
if (luts.count(port.cell))
{
auto lutB = port.cell;
SigSpec lutB_input = sigmap(lutB->getPort(ID::A));
SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]);
SigSpec lutB_input = sigmap(lutB->getPort(TW::A));
SigSpec lutB_output = sigmap(lutB->getPort(TW::Y)[0]);
int lutB_width = lutB->getParam(ID::WIDTH).as_int();
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", module, lutA, module, lutB);
if (index.query_is_output(lutA->getPort(ID::Y)))
if (index.query_is_output(lutA->getPort(TW::Y)))
{
log_debug(" Not combining LUTs (cascade connection feeds module output).\n");
continue;
@ -453,7 +453,7 @@ struct OptLutWorker
}
int lutM_width = lutM->getParam(ID::WIDTH).as_int();
SigSpec lutM_input = sigmap(lutM->getPort(ID::A));
SigSpec lutM_input = sigmap(lutM->getPort(TW::A));
std::vector<SigBit> lutM_new_inputs;
for (int i = 0; i < lutM_width; i++)
{
@ -499,8 +499,8 @@ struct OptLutWorker
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string());
lutM->setParam(ID::LUT, lutM_new_table);
lutM->setPort(ID::A, lutM_new_inputs);
lutM->setPort(ID::Y, lutB_output);
lutM->setPort(TW::A, lutM_new_inputs);
lutM->setPort(TW::Y, lutB_output);
luts_arity[lutM] = lutM_arity;
luts.erase(lutR);

26
passes/opt/opt_lut_ins.cc
View file

@ -79,8 +79,8 @@ struct OptLutInsPass : public Pass {
if (techname == "") {
if (cell->type != ID($lut))
continue;
inputs = cell->getPort(ID::A);
output = cell->getPort(ID::Y);
inputs = cell->getPort(TW::A);
output = cell->getPort(TW::Y);
lut = cell->getParam(ID::LUT);
} else if (techname == "xilinx" || techname == "gowin" || techname == "analogdevices") {
if (cell->type == ID(LUT1)) {
@ -128,16 +128,16 @@ struct OptLutInsPass : public Pass {
}
lut = cell->getParam(ID::INIT);
if (techname == "xilinx" || techname == "analogdevices")
output = cell->getPort(ID::O);
output = cell->getPort(TW::O);
else
output = cell->getPort(ID::F);
output = cell->getPort(TW::F);
} else if (techname == "lattice") {
if (cell->type == ID(LUT4)) {
inputs = {
cell->getPort(ID::A),
cell->getPort(ID::B),
cell->getPort(ID::C),
cell->getPort(ID::D),
cell->getPort(TW::A),
cell->getPort(TW::B),
cell->getPort(TW::C),
cell->getPort(TW::D),
};
lut = cell->getParam(ID::INIT);
output = cell->getPort(ID(Z));
@ -226,14 +226,14 @@ struct OptLutInsPass : public Pass {
if (techname == "") {
cell->setParam(ID::LUT, new_lut);
cell->setParam(ID::WIDTH, GetSize(new_inputs));
cell->setPort(ID::A, new_inputs);
cell->setPort(TW::A, new_inputs);
} else if (techname == "lattice" || techname == "ecp5") {
log_assert(GetSize(new_inputs) == 4);
cell->setParam(ID::INIT, new_lut);
cell->setPort(ID::A, new_inputs[0]);
cell->setPort(ID::B, new_inputs[1]);
cell->setPort(ID::C, new_inputs[2]);
cell->setPort(ID::D, new_inputs[3]);
cell->setPort(TW::A, new_inputs[0]);
cell->setPort(TW::B, new_inputs[1]);
cell->setPort(TW::C, new_inputs[2]);
cell->setPort(TW::D, new_inputs[3]);
} else {
// xilinx, gowin
cell->setParam(ID::INIT, new_lut);

18
passes/opt/opt_mem_feedback.cc
View file

@ -75,10 +75,10 @@ struct OptMemFeedbackWorker
RTLIL::Cell *cell = sig_to_mux.at(sig).first;
int bit_idx = sig_to_mux.at(sig).second;
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(TW::A));
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(TW::B));
std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(TW::S));
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(TW::Y));
log_assert(sig_y.at(bit_idx) == sig);
for (int i = 0; i < GetSize(sig_s); i++)
@ -295,18 +295,18 @@ struct OptMemFeedbackWorker
{
if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
if (sig_a.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
sigmap_xmux.add(cell->getPort(TW::Y), sig_b);
else if (sig_b.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
if (cell->type.in(ID($mux), ID($pmux)))
{
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < int(sig_y.size()); i++)
sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
}

2
passes/opt/opt_merge.cc
View file

@ -298,7 +298,7 @@ struct OptMergeWorker
for (auto [remove_cell, keep_cell] : cell_ptrs)
{
log_debug(" Cell `%s' is identical to cell `%s'.\n", remove_cell->name, keep_cell->name);
std::vector<std::pair<RTLIL::IdString, RTLIL::SigSpec>> port_replacements;
std::vector<std::pair<TwineRef, RTLIL::SigSpec>> port_replacements;
for (auto &it : remove_cell->connections()) {
if (remove_cell->output(it.first)) {
RTLIL::SigSpec keep_sig = keep_cell->getPort(it.first);

50
passes/opt/opt_merge_common.h
View file

@ -64,10 +64,10 @@ struct CellHasher
return comm.hash_into(h);
}
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
static void sort_pmux_conn(dict<TwineRef, RTLIL::SigSpec> &conn)
{
const SigSpec &sig_s = conn.at(ID::S);
const SigSpec &sig_b = conn.at(ID::B);
const SigSpec &sig_s = conn.at(TW::S);
const SigSpec &sig_b = conn.at(TW::B);
int s_width = GetSize(sig_s);
int width = GetSize(sig_b) / s_width;
@ -78,12 +78,12 @@ struct CellHasher
std::sort(sb_pairs.begin(), sb_pairs.end());
conn[ID::S] = SigSpec();
conn[ID::B] = SigSpec();
conn[TW::S] = SigSpec();
conn[TW::B] = SigSpec();
for (auto &it : sb_pairs) {
conn[ID::S].append(it.first);
conn[ID::B].append(it.second);
conn[TW::S].append(it.first);
conn[TW::B].append(it.second);
}
}
@ -94,22 +94,22 @@ struct CellHasher
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
hashlib::commutative_hash comm;
comm.eat(map_sig(cell->getPort(ID::A)));
comm.eat(map_sig(cell->getPort(ID::B)));
comm.eat(map_sig(cell->getPort(TW::A)));
comm.eat(map_sig(cell->getPort(TW::B)));
h = comm.hash_into(h);
} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
SigSpec a = map_sig(cell->getPort(ID::A));
SigSpec a = map_sig(cell->getPort(TW::A));
a.sort();
h = a.hash_into(h);
} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
SigSpec a = map_sig(cell->getPort(ID::A));
SigSpec a = map_sig(cell->getPort(TW::A));
a.sort_and_unify();
h = a.hash_into(h);
} else if (cell->type == ID($pmux)) {
SigSpec sig_s = map_sig(cell->getPort(ID::S));
SigSpec sig_b = map_sig(cell->getPort(ID::B));
SigSpec sig_s = map_sig(cell->getPort(TW::S));
SigSpec sig_b = map_sig(cell->getPort(TW::B));
h = hash_pmux_in(sig_s, sig_b, h);
h = map_sig(cell->getPort(ID::A)).hash_into(h);
h = map_sig(cell->getPort(TW::A)).hash_into(h);
} else {
hashlib::commutative_hash comm;
for (const auto& [port, sig] : cell->connections()) {
@ -119,7 +119,7 @@ struct CellHasher
}
h = comm.hash_into(h);
if (cell->is_builtin_ff())
h = initvals(cell->getPort(ID::Q)).hash_into(h);
h = initvals(cell->getPort(TW::Q)).hash_into(h);
}
return h;
}
@ -160,7 +160,7 @@ struct CellHasher
for (const auto &it : cell1->connections_) {
if (cell1->output(it.first)) {
if (it.first == ID::Q && cell1->is_builtin_ff()) {
if (it.first == TW::Q && cell1->is_builtin_ff()) {
// For the 'Q' output of state elements,
// use the (* init *) attribute value
conn1[it.first] = initvals(it.second);
@ -179,20 +179,20 @@ struct CellHasher
if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
if (conn1.at(ID::A) < conn1.at(ID::B)) {
std::swap(conn1[ID::A], conn1[ID::B]);
if (conn1.at(TW::A) < conn1.at(TW::B)) {
std::swap(conn1[TW::A], conn1[TW::B]);
}
if (conn2.at(ID::A) < conn2.at(ID::B)) {
std::swap(conn2[ID::A], conn2[ID::B]);
if (conn2.at(TW::A) < conn2.at(TW::B)) {
std::swap(conn2[TW::A], conn2[TW::B]);
}
} else
if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) {
conn1[ID::A].sort();
conn2[ID::A].sort();
conn1[TW::A].sort();
conn2[TW::A].sort();
} else
if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
conn1[ID::A].sort_and_unify();
conn2[ID::A].sort_and_unify();
conn1[TW::A].sort_and_unify();
conn2[TW::A].sort_and_unify();
} else
if (cell1->type == ID($pmux)) {
sort_pmux_conn(conn1);
@ -207,7 +207,7 @@ struct CellHasher
if (!cell->is_builtin_ff())
return false;
return !initvals(cell->getPort(ID::Q)).is_fully_def();
return !initvals(cell->getPort(TW::Q)).is_fully_def();
}
};

2
passes/opt/opt_merge_inc.cc
View file

@ -268,7 +268,7 @@ struct OptMergeIncWorker
did_something = true;
log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name);
std::vector<std::pair<RTLIL::IdString, RTLIL::SigSpec>> port_replacements;
std::vector<std::pair<TwineRef, RTLIL::SigSpec>> port_replacements;
for (auto &[port, sig] : cell->connections()) {
if (cell->output(port)) {
// TODO why was this removed before?

28
passes/opt/opt_muxtree.cc
View file

@ -113,10 +113,10 @@ struct OptMuxtreeWorker
// .input_sigs
// .const_activated
// .const_deactivated
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
muxinfo_t muxinfo;
muxinfo.cell = cell;
@ -300,10 +300,10 @@ struct OptMuxtreeWorker
continue;
}
RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A);
RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B);
RTLIL::SigSpec sig_s = mi.cell->getPort(ID::S);
RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = mi.cell->getPort(TW::A);
RTLIL::SigSpec sig_b = mi.cell->getPort(TW::B);
RTLIL::SigSpec sig_s = mi.cell->getPort(TW::S);
RTLIL::SigSpec sig_y = mi.cell->getPort(TW::Y);
RTLIL::SigSpec sig_ports = sig_b;
sig_ports.append(sig_a);
@ -328,9 +328,9 @@ struct OptMuxtreeWorker
}
}
mi.cell->setPort(ID::A, new_sig_a);
mi.cell->setPort(ID::B, new_sig_b);
mi.cell->setPort(ID::S, new_sig_s);
mi.cell->setPort(TW::A, new_sig_a);
mi.cell->setPort(TW::B, new_sig_b);
mi.cell->setPort(TW::S, new_sig_s);
if (GetSize(new_sig_s) == 1) {
mi.cell->type = ID($mux);
mi.cell->parameters.erase(ID::S_WIDTH);
@ -465,7 +465,7 @@ struct OptMuxtreeWorker
deactivate_port(knowledge, port_idx, muxinfo);
}
void replace_known(knowledge_t &knowledge, muxinfo_t &muxinfo, IdString portname)
void replace_known(knowledge_t &knowledge, muxinfo_t &muxinfo, TwineRef portname)
{
SigSpec sig = muxinfo.cell->getPort(portname);
bool did_something = false;
@ -473,8 +473,8 @@ struct OptMuxtreeWorker
int width_if_b = 0;
idict<int> ctrl_bits;
if (portname == ID::B)
width_if_b = GetSize(muxinfo.cell->getPort(ID::A));
for (int bit : sig2bits(muxinfo.cell->getPort(ID::S), false))
width_if_b = GetSize(muxinfo.cell->getPort(TW::A));
for (int bit : sig2bits(muxinfo.cell->getPort(TW::S), false))
ctrl_bits(bit);
int slice_idx = 0, slice_off = 0;

128
passes/opt/opt_reduce.cc
View file

@ -43,7 +43,7 @@ struct OptReduceWorker
return;
cells.erase(cell);
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
sig_a.sort_and_unify();
pool<RTLIL::SigBit> new_sig_a_bits;
@ -74,8 +74,8 @@ struct OptReduceWorker
for (auto child_cell : drivers.find(bit)) {
if (child_cell->type == cell->type) {
opt_reduce(cells, drivers, child_cell);
if (child_cell->getPort(ID::Y)[0] == bit) {
pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(ID::A)).to_sigbit_pool();
if (child_cell->getPort(TW::Y)[0] == bit) {
pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(TW::A)).to_sigbit_pool();
new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
} else
new_sig_a_bits.insert(RTLIL::State::S0);
@ -92,22 +92,22 @@ struct OptReduceWorker
if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(TW::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a));
did_something = true;
total_count++;
}
cell->setPort(ID::A, new_sig_a);
cell->setPort(TW::A, new_sig_a);
cell->parameters[ID::A_WIDTH] = RTLIL::Const(new_sig_a.size());
return;
}
void opt_pmux(RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S));
RTLIL::SigSpec new_sig_b, new_sig_s;
dict<RTLIL::SigSpec, std::vector<RTLIL::SigBit>> grouped_b_to_s;
@ -126,15 +126,15 @@ struct OptReduceWorker
RTLIL::SigSpec this_s{this_s_bit};
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
reduce_or_cell->setPort(ID::A, this_s);
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
reduce_or_cell->setPort(TW::A, this_s);
reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_TWINE);
this_s = RTLIL::SigSpec(reduce_or_wire);
reduce_or_cell->setPort(ID::Y, this_s);
reduce_or_cell->setPort(TW::Y, this_s);
}
new_sig_b.append(this_b);
@ -143,8 +143,8 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
assign_map.add(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
assign_map.add(cell->getPort(TW::Y), cell->getPort(TW::A));
module->remove(cell);
did_something = true;
total_count++;
@ -155,8 +155,8 @@ struct OptReduceWorker
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::B, new_sig_b);
cell->setPort(ID::S, new_sig_s);
cell->setPort(TW::B, new_sig_b);
cell->setPort(TW::S, new_sig_s);
if (new_sig_s.size() > 1) {
cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
} else {
@ -168,8 +168,8 @@ struct OptReduceWorker
void opt_bmux(RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S));
int width = cell->getParam(ID::WIDTH).as_int();
RTLIL::SigSpec new_sig_a, new_sig_s;
@ -218,8 +218,8 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
module->connect(cell->getPort(ID::Y), new_sig_a);
assign_map.add(cell->getPort(ID::Y), new_sig_a);
module->connect(cell->getPort(TW::Y), new_sig_a);
assign_map.add(cell->getPort(TW::Y), new_sig_a);
module->remove(cell);
did_something = true;
total_count++;
@ -229,9 +229,9 @@ struct OptReduceWorker
if (new_sig_s.size() == 1)
{
cell->type = ID($mux);
cell->setPort(ID::A, new_sig_a.extract(0, width));
cell->setPort(ID::B, new_sig_a.extract(width, width));
cell->setPort(ID::S, new_sig_s);
cell->setPort(TW::A, new_sig_a.extract(0, width));
cell->setPort(TW::B, new_sig_a.extract(width, width));
cell->setPort(TW::S, new_sig_s);
cell->parameters.erase(ID::S_WIDTH);
did_something = true;
total_count++;
@ -242,16 +242,16 @@ struct OptReduceWorker
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::A, new_sig_a);
cell->setPort(ID::S, new_sig_s);
cell->setPort(TW::A, new_sig_a);
cell->setPort(TW::S, new_sig_s);
cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
}
}
void opt_demux(RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S));
int width = cell->getParam(ID::WIDTH).as_int();
RTLIL::SigSpec new_sig_y, new_sig_s;
@ -319,27 +319,27 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
module->connect(new_sig_y, cell->getPort(ID::A));
assign_map.add(new_sig_y, cell->getPort(ID::A));
module->connect(new_sig_y, cell->getPort(TW::A));
assign_map.add(new_sig_y, cell->getPort(TW::A));
module->remove(cell);
}
else
{
cell->setPort(ID::S, new_sig_s);
cell->setPort(ID::Y, new_sig_y);
cell->setPort(TW::S, new_sig_s);
cell->setPort(TW::Y, new_sig_y);
cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
}
}
bool opt_mux_bits(RTLIL::Cell *cell)
{
SigSpec sig_a = assign_map(cell->getPort(ID::A));
SigSpec sig_a = assign_map(cell->getPort(TW::A));
SigSpec sig_b;
SigSpec sig_y = assign_map(cell->getPort(ID::Y));
SigSpec sig_y = assign_map(cell->getPort(TW::Y));
int width = GetSize(sig_y);
if (cell->type != ID($bmux))
sig_b = assign_map(cell->getPort(ID::B));
sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSig old_sig_conn;
@ -387,11 +387,11 @@ struct OptReduceWorker
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
if (cell->type != ID($bmux)) {
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
} else {
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::Y)));
}
if (swizzle.empty()) {
@ -401,29 +401,29 @@ struct OptReduceWorker
for (int i = 0; i < GetSize(sig_a); i += width)
for (int j: swizzle)
new_sig_a.append(sig_a[i+j]);
cell->setPort(ID::A, new_sig_a);
cell->setPort(TW::A, new_sig_a);
if (cell->type != ID($bmux)) {
SigSpec new_sig_b;
for (int i = 0; i < GetSize(sig_b); i += width)
for (int j: swizzle)
new_sig_b.append(sig_b[i+j]);
cell->setPort(ID::B, new_sig_b);
cell->setPort(TW::B, new_sig_b);
}
SigSpec new_sig_y;
for (int j: swizzle)
new_sig_y.append(sig_y[j]);
cell->setPort(ID::Y, new_sig_y);
cell->setPort(TW::Y, new_sig_y);
cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
if (cell->type != ID($bmux)) {
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
} else {
log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::Y)));
}
}
@ -437,8 +437,8 @@ struct OptReduceWorker
}
bool opt_demux_bits(RTLIL::Cell *cell) {
SigSpec sig_a = assign_map(cell->getPort(ID::A));
SigSpec sig_y = assign_map(cell->getPort(ID::Y));
SigSpec sig_a = assign_map(cell->getPort(TW::A));
SigSpec sig_y = assign_map(cell->getPort(TW::Y));
int width = GetSize(sig_a);
RTLIL::SigSig old_sig_conn;
@ -477,8 +477,8 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::Y)));
if (swizzle.empty()) {
module->remove(cell);
@ -486,18 +486,18 @@ struct OptReduceWorker
SigSpec new_sig_a;
for (int j: swizzle)
new_sig_a.append(sig_a[j]);
cell->setPort(ID::A, new_sig_a);
cell->setPort(TW::A, new_sig_a);
SigSpec new_sig_y;
for (int i = 0; i < GetSize(sig_y); i += width)
for (int j: swizzle)
new_sig_y.append(sig_y[i+j]);
cell->setPort(ID::Y, new_sig_y);
cell->setPort(TW::Y, new_sig_y);
cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::Y)));
}
log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
@ -521,14 +521,14 @@ struct OptReduceWorker
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type.in(ID($mem), ID($mem_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN)));
mem_wren_sigs.add(assign_map(cell->getPort(TW::WR_EN)));
if (cell->type.in(ID($memwr), ID($memwr_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(ID::EN)));
mem_wren_sigs.add(assign_map(cell->getPort(TW::EN)));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Q))))
mem_wren_sigs.add(assign_map(cell->getPort(ID::D)));
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q))))
mem_wren_sigs.add(assign_map(cell->getPort(TW::D)));
}
bool keep_expanding_mem_wren_sigs = true;
@ -536,12 +536,12 @@ struct OptReduceWorker
keep_expanding_mem_wren_sigs = false;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) {
if (!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::A))) ||
!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::B))))
if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
if (!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::A))) ||
!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::B))))
keep_expanding_mem_wren_sigs = true;
mem_wren_sigs.add(assign_map(cell->getPort(ID::A)));
mem_wren_sigs.add(assign_map(cell->getPort(ID::B)));
mem_wren_sigs.add(assign_map(cell->getPort(TW::A)));
mem_wren_sigs.add(assign_map(cell->getPort(TW::B)));
}
}
}
@ -563,7 +563,7 @@ struct OptReduceWorker
RTLIL::Cell *cell = cell_it.second;
if (cell->type != type || !design->selected(module, cell))
continue;
drivers.insert(assign_map(cell->getPort(ID::Y)), cell);
drivers.insert(assign_map(cell->getPort(TW::Y)), cell);
cells.insert(cell);
}
@ -582,7 +582,7 @@ struct OptReduceWorker
// this optimization is to aggressive for most coarse-grain applications.
// but we always want it for multiplexers driving write enable ports.
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) {
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
if (cell->type == ID($demux)) {
if (opt_demux_bits(cell))
continue;

58
passes/opt/opt_share.cc
View file

@ -96,8 +96,8 @@ struct ExtSigSpec {
bool cell_supported(RTLIL::Cell *cell)
{
if (cell->type.in(ID($alu))) {
RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
RTLIL::SigSpec sig_bi = cell->getPort(TW::BI);
RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
return true;
@ -126,7 +126,7 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
return a_type == b_type;
}
RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_name)
RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name)
{
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B)
return port_name;
@ -137,17 +137,17 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
return "";
}
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, TwineRef port_name) {
if (cell->type == ID($alu) && port_name == ID::B)
return cell->getPort(ID::BI);
return cell->getPort(TW::BI);
else if (cell->type == ID($sub) && port_name == ID::B)
return RTLIL::Const(1, 1);
return RTLIL::Const(0, 1);
}
bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name)
bool decode_port_signed(RTLIL::Cell *cell, TwineRef port_name)
{
if (cell->type.in(BITWISE_OPS, LOGICAL_OPS))
return false;
@ -158,7 +158,7 @@ bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name)
return false;
}
ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMap &sigmap)
ExtSigSpec decode_port(RTLIL::Cell *cell, TwineRef port_name, const SigMap &sigmap)
{
auto sig = sigmap(cell->getPort(port_name));
@ -206,9 +206,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
module->remove(op);
}
RTLIL::SigSpec mux_a = mux->getPort(ID::A);
RTLIL::SigSpec mux_b = mux->getPort(ID::B);
RTLIL::SigSpec mux_s = mux->getPort(ID::S);
RTLIL::SigSpec mux_a = mux->getPort(TW::A);
RTLIL::SigSpec mux_b = mux->getPort(TW::B);
RTLIL::SigSpec mux_s = mux->getPort(TW::S);
int conn_width = ports[0].sig.size();
int conn_mux_offset = ports[0].mux_port_offset;
@ -219,7 +219,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
RTLIL::SigSpec shared_pmux_s;
// Make a new wire to avoid false equivalence with whatever the former shared output was connected to.
Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width);
Wire *new_out = module->addWire(NEW_TWINE, conn_op_offset + conn_width);
SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);
for (int i = 0; i < GetSize(ports); i++) {
@ -235,9 +235,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
}
}
mux->setPort(ID::A, mux_a);
mux->setPort(ID::B, mux_b);
mux->setPort(ID::S, mux_s);
mux->setPort(TW::A, mux_a);
mux->setPort(TW::B, mux_b);
mux->setPort(TW::S, mux_s);
SigSpec mux_to_oper;
if (GetSize(shared_pmux_s) == 1) {
@ -247,22 +247,22 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
}
if (shared_op->type.in(ID($alu))) {
shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(TW::X, module->addWire(NEW_TWINE, GetSize(new_out)));
shared_op->setPort(TW::CO, module->addWire(NEW_TWINE, GetSize(new_out)));
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
shared_op->setPort(ID::Y, new_out);
shared_op->setPort(TW::Y, new_out);
if (!is_fine)
shared_op->setParam(ID::Y_WIDTH, GetSize(new_out));
if (decode_port(shared_op, ID::A, sigmap) == operand) {
shared_op->setPort(ID::B, mux_to_oper);
shared_op->setPort(TW::B, mux_to_oper);
if (!is_fine)
shared_op->setParam(ID::B_WIDTH, max_width);
} else {
shared_op->setPort(ID::A, mux_to_oper);
shared_op->setPort(TW::A, mux_to_oper);
if (!is_fine)
shared_op->setParam(ID::A_WIDTH, max_width);
}
@ -313,7 +313,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon
auto op_a = seed->op;
for (RTLIL::IdString port_name : {ID::A, ID::B}) {
for (TwineRef port_name : {ID::A, ID::B}) {
oper = decode_port(op_a, port_name, sigmap);
auto operand_users = operand_to_users.at(oper);
@ -386,7 +386,7 @@ struct OptSharePass : public Pass {
bool skip = false;
if (cell->type == ID($alu)) {
for (RTLIL::IdString port_name : {ID::X, ID::CO}) {
for (TwineRef port_name : {ID::X, ID::CO}) {
for (auto outbit : sigmap(cell->getPort(port_name)))
if (bit_users[outbit] > 1)
skip = true;
@ -396,11 +396,11 @@ struct OptSharePass : public Pass {
if (skip)
continue;
auto mux_insig = sigmap(cell->getPort(ID::Y));
auto mux_insig = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(mux_insig); i++)
op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i);
for (RTLIL::IdString port_name : {ID::A, ID::B}) {
for (TwineRef port_name : {ID::A, ID::B}) {
auto op_insig = decode_port(cell, port_name, sigmap);
operand_to_users[op_insig].insert(cell);
if (operand_to_users[op_insig].size() > 1)
@ -419,19 +419,19 @@ struct OptSharePass : public Pass {
if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux)))
continue;
int mux_port_size = GetSize(mux->getPort(ID::A));
int mux_port_num = GetSize(mux->getPort(ID::S)) + 1;
int mux_port_size = GetSize(mux->getPort(TW::A));
int mux_port_num = GetSize(mux->getPort(TW::S)) + 1;
RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)});
RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(TW::B), mux->getPort(TW::A)});
std::vector<std::set<OpMuxConn>> mux_port_conns(mux_port_num);
int found = 0;
for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) {
SigSpec mux_insig;
if (mux_port_id == mux_port_num - 1) {
mux_insig = sigmap(mux->getPort(ID::A));
mux_insig = sigmap(mux->getPort(TW::A));
} else {
mux_insig = sigmap(mux->getPort(ID::B).extract(mux_port_id * mux_port_size, mux_port_size));
mux_insig = sigmap(mux->getPort(TW::B).extract(mux_port_id * mux_port_size, mux_port_size));
}
for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) {
@ -441,7 +441,7 @@ struct OptSharePass : public Pass {
RTLIL::Cell *cell;
int op_outsig_offset;
std::tie(cell, op_outsig_offset) = op_outbit_to_outsig.at(mux_insig[mux_port_offset]);
SigSpec op_outsig = sigmap(cell->getPort(ID::Y));
SigSpec op_outsig = sigmap(cell->getPort(TW::Y));
int op_outsig_size = GetSize(op_outsig);
int op_conn_width = 0;

2
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -50,7 +50,7 @@ code
// instead of the latch. We don't delete the latch in case its output is
// used to drive other nodes. If it isn't, it will be trivially removed by
// clean
SigSpec flopped_en = module->addWire(NEW_ID);
SigSpec flopped_en = module->addWire(NEW_TWINE);
module->addDff(NEW_ID, clk, en, flopped_en, true, latch->src_ref());
and_gate->setPort(latched_en_port_name, flopped_en);
did_something = true;

4
passes/opt/peepopt_shiftmul_left.pmg
View file

@ -129,7 +129,7 @@ code
if (bit == SigBit(State::Sm))
padbits++;
SigSpec padwire = module->addWire(NEW_ID, padbits);
SigSpec padwire = module->addWire(NEW_TWINE, padbits);
for (int i = new_y.size() - 1; i >= 0; i--)
if (new_y[i] == SigBit(State::Sm)) {
@ -148,7 +148,7 @@ code
shift->setPort(\B, new_b);
shift->setParam(\B_WIDTH, GetSize(new_b));
} else {
SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1);
SigSpec b_neg = module->addWire(NEW_TWINE, GetSize(new_b) + 1);
module->addNeg(NEW_ID, new_b, b_neg);
shift->setPort(\B, b_neg);
shift->setParam(\B_WIDTH, GetSize(b_neg));

44
passes/opt/pmux2shiftx.cc
View file

@ -56,19 +56,19 @@ struct OnehotDatabase
if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff)))
{
output = cell->getPort(ID::Q);
output = cell->getPort(TW::Q);
if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
inputs.push_back(cell->getParam(ID::ARST_VALUE));
if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
inputs.push_back(cell->getParam(ID::SRST_VALUE));
inputs.push_back(cell->getPort(ID::D));
inputs.push_back(cell->getPort(TW::D));
}
if (cell->type.in(ID($mux), ID($pmux)))
{
output = cell->getPort(ID::Y);
inputs.push_back(cell->getPort(ID::A));
SigSpec B = cell->getPort(ID::B);
output = cell->getPort(TW::Y);
inputs.push_back(cell->getPort(TW::A));
SigSpec B = cell->getPort(TW::B);
for (int i = 0; i < GetSize(B); i += GetSize(output))
inputs.push_back(B.extract(i, GetSize(output)));
}
@ -289,8 +289,8 @@ struct Pmux2ShiftxPass : public Pass {
{
dict<SigBit, State> bits;
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B));
SigSpec A = sigmap(cell->getPort(TW::A));
SigSpec B = sigmap(cell->getPort(TW::B));
int a_width = cell->getParam(ID::A_WIDTH).as_int();
int b_width = cell->getParam(ID::B_WIDTH).as_int();
@ -329,7 +329,7 @@ struct Pmux2ShiftxPass : public Pass {
}
entry.second = entry_bits_builder.build();
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
eqdb[sigmap(cell->getPort(TW::Y)[0])] = entry;
goto next_cell;
}
@ -337,7 +337,7 @@ struct Pmux2ShiftxPass : public Pass {
{
dict<SigBit, State> bits;
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec A = sigmap(cell->getPort(TW::A));
for (int i = 0; i < GetSize(A); i++)
bits[A[i]] = State::S0;
@ -351,7 +351,7 @@ struct Pmux2ShiftxPass : public Pass {
}
entry.second = entry_bits_builder.build();
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
eqdb[sigmap(cell->getPort(TW::Y)[0])] = entry;
goto next_cell;
}
next_cell:;
@ -372,9 +372,9 @@ struct Pmux2ShiftxPass : public Pass {
dict<SigSpec, pool<int>> seldb;
SigSpec A = cell->getPort(ID::A);
SigSpec B = cell->getPort(ID::B);
SigSpec S = sigmap(cell->getPort(ID::S));
SigSpec A = cell->getPort(TW::A);
SigSpec B = cell->getPort(TW::B);
SigSpec S = sigmap(cell->getPort(TW::S));
for (int i = 0; i < GetSize(S); i++)
{
if (!eqdb.count(S[i]))
@ -395,8 +395,8 @@ struct Pmux2ShiftxPass : public Pass {
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
SigSpec updated_S = cell->getPort(ID::S);
SigSpec updated_B = cell->getPort(ID::B);
SigSpec updated_S = cell->getPort(TW::S);
SigSpec updated_B = cell->getPort(TW::B);
while (!seldb.empty())
{
@ -691,7 +691,7 @@ struct Pmux2ShiftxPass : public Pass {
Const enable_mask(State::S0, max_choice+1);
for (auto &it : perm_choices)
enable_mask.set(it.first.as_int(), State::S1);
en = module->addWire(NEW_ID);
en = module->addWire(NEW_TWINE);
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
}
@ -711,7 +711,7 @@ struct Pmux2ShiftxPass : public Pass {
// create shiftx cell
SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)};
SigSpec outsig = module->addWire(NEW_ID, width);
SigSpec outsig = module->addWire(NEW_TWINE, width);
Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
updated_S.append(en);
updated_B.append(outsig);
@ -722,8 +722,8 @@ struct Pmux2ShiftxPass : public Pass {
}
// update $pmux cell
cell->setPort(ID::S, updated_S);
cell->setPort(ID::B, updated_B);
cell->setPort(TW::S, updated_S);
cell->setPort(TW::B, updated_B);
cell->setParam(ID::S_WIDTH, GetSize(updated_S));
}
}
@ -780,8 +780,8 @@ struct OnehotPass : public Pass {
if (cell->type != ID($eq))
continue;
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B));
SigSpec A = sigmap(cell->getPort(TW::A));
SigSpec B = sigmap(cell->getPort(TW::B));
int a_width = cell->getParam(ID::A_WIDTH).as_int();
int b_width = cell->getParam(ID::B_WIDTH).as_int();
@ -828,7 +828,7 @@ struct OnehotPass : public Pass {
continue;
}
SigSpec Y = cell->getPort(ID::Y);
SigSpec Y = cell->getPort(TW::Y);
SigSpec replacement;
if (not_onehot)

146
passes/opt/share.cc
View file

@ -89,7 +89,7 @@ struct ShareWorker
for (auto &pbit : portbits) {
if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && visited_cells.count(pbit.cell) == 0) {
pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID::S)).to_sigbit_pool();
pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(TW::S)).to_sigbit_pool();
terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end());
visited_cells.insert(pbit.cell);
@ -127,7 +127,7 @@ struct ShareWorker
static int bits_macc(RTLIL::Cell *c)
{
Macc m(c);
int width = GetSize(c->getPort(ID::Y));
int width = GetSize(c->getPort(TW::Y));
return bits_macc(m, width);
}
@ -206,12 +206,12 @@ struct ShareWorker
sig_b2.extend_u0(GetSize(sig_b), p2.is_signed);
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
sig_a = module->addWire(NEW_TWINE, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
sig_b = module->addWire(NEW_TWINE, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b));
}
@ -241,7 +241,7 @@ struct ShareWorker
{
Macc m1(c1), m2(c2), supermacc;
int w1 = GetSize(c1->getPort(ID::Y)), w2 = GetSize(c2->getPort(ID::Y));
int w1 = GetSize(c1->getPort(TW::Y)), w2 = GetSize(c2->getPort(TW::Y));
int width = max(w1, w2);
m1.optimize(w1);
@ -283,12 +283,12 @@ struct ShareWorker
RTLIL::SigSpec sig_b = m1.terms[i].in_b;
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
sig_a = module->addWire(NEW_TWINE, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
sig_b = module->addWire(NEW_TWINE, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b));
}
@ -306,12 +306,12 @@ struct ShareWorker
RTLIL::SigSpec sig_b = m2.terms[i].in_b;
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
sig_a = module->addWire(NEW_TWINE, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
sig_b = module->addWire(NEW_TWINE, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b));
}
@ -325,13 +325,13 @@ struct ShareWorker
if (supercell)
{
RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width);
RTLIL::SigSpec sig_y = module->addWire(NEW_TWINE, width);
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(TW::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(TW::Y)));
supercell->setParam(ID::Y_WIDTH, width);
supercell->setPort(ID::Y, sig_y);
supercell->setPort(TW::Y, sig_y);
supermacc.optimize(width);
supermacc.to_cell(supercell);
@ -365,7 +365,7 @@ struct ShareWorker
if (cell->type.in(ID($memrd), ID($memrd_v2))) {
if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue;
if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID::ADDR)).is_fully_const())
if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(TW::ADDR)).is_fully_const())
shareable_cells.insert(cell);
continue;
}
@ -510,11 +510,11 @@ struct ShareWorker
if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort(TW::A).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
RTLIL::SigSpec new_a = unsigned_cell->getPort(TW::A);
new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
unsigned_cell->setPort(TW::A, new_a);
}
unsigned_cell->parameters.at(ID::A_SIGNED) = true;
unsigned_cell->check();
@ -523,11 +523,11 @@ struct ShareWorker
bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool();
log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
RTLIL::SigSpec a1 = c1->getPort(ID::A);
RTLIL::SigSpec y1 = c1->getPort(ID::Y);
RTLIL::SigSpec a1 = c1->getPort(TW::A);
RTLIL::SigSpec y1 = c1->getPort(TW::Y);
RTLIL::SigSpec a2 = c2->getPort(ID::A);
RTLIL::SigSpec y2 = c2->getPort(ID::Y);
RTLIL::SigSpec a2 = c2->getPort(TW::A);
RTLIL::SigSpec y2 = c2->getPort(TW::Y);
int a_width = max(a1.size(), a2.size());
int y_width = max(y1.size(), y2.size());
@ -535,17 +535,17 @@ struct ShareWorker
a1.extend_u0(a_width, a_signed);
a2.extend_u0(a_width, a_signed);
RTLIL::SigSpec a = module->addWire(NEW_ID, a_width);
RTLIL::SigSpec a = module->addWire(NEW_TWINE, a_width);
supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID::A_WIDTH] = a_width;
supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::Y, y);
supercell->setPort(TW::A, a);
supercell->setPort(TW::Y, y);
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
@ -568,9 +568,9 @@ struct ShareWorker
if (score_flipped < score_unflipped)
{
RTLIL::SigSpec tmp = c2->getPort(ID::A);
c2->setPort(ID::A, c2->getPort(ID::B));
c2->setPort(ID::B, tmp);
RTLIL::SigSpec tmp = c2->getPort(TW::A);
c2->setPort(TW::A, c2->getPort(TW::B));
c2->setPort(TW::B, tmp);
std::swap(c2->parameters.at(ID::A_WIDTH), c2->parameters.at(ID::B_WIDTH));
std::swap(c2->parameters.at(ID::A_SIGNED), c2->parameters.at(ID::B_SIGNED));
@ -582,11 +582,11 @@ struct ShareWorker
{
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort(TW::A).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
RTLIL::SigSpec new_a = unsigned_cell->getPort(TW::A);
new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
unsigned_cell->setPort(TW::A, new_a);
}
unsigned_cell->parameters.at(ID::A_SIGNED) = true;
modified_src_cells = true;
@ -595,11 +595,11 @@ struct ShareWorker
if (c1->parameters.at(ID::B_SIGNED).as_bool() != c2->parameters.at(ID::B_SIGNED).as_bool())
{
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::B_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort(TW::B).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID::B_WIDTH) = unsigned_cell->parameters.at(ID::B_WIDTH).as_int() + 1;
RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B);
RTLIL::SigSpec new_b = unsigned_cell->getPort(TW::B);
new_b.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::B, new_b);
unsigned_cell->setPort(TW::B, new_b);
}
unsigned_cell->parameters.at(ID::B_SIGNED) = true;
modified_src_cells = true;
@ -619,13 +619,13 @@ struct ShareWorker
if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
b_signed = false;
RTLIL::SigSpec a1 = c1->getPort(ID::A);
RTLIL::SigSpec b1 = c1->getPort(ID::B);
RTLIL::SigSpec y1 = c1->getPort(ID::Y);
RTLIL::SigSpec a1 = c1->getPort(TW::A);
RTLIL::SigSpec b1 = c1->getPort(TW::B);
RTLIL::SigSpec y1 = c1->getPort(TW::Y);
RTLIL::SigSpec a2 = c2->getPort(ID::A);
RTLIL::SigSpec b2 = c2->getPort(ID::B);
RTLIL::SigSpec y2 = c2->getPort(ID::Y);
RTLIL::SigSpec a2 = c2->getPort(TW::A);
RTLIL::SigSpec b2 = c2->getPort(TW::B);
RTLIL::SigSpec y2 = c2->getPort(TW::Y);
int a_width = max(a1.size(), a2.size());
int b_width = max(b1.size(), b2.size());
@ -650,43 +650,43 @@ struct ShareWorker
b1.extend_u0(b_width, b_signed);
b2.extend_u0(b_width, b_signed);
RTLIL::SigSpec a = module->addWire(NEW_ID, a_width);
RTLIL::SigSpec b = module->addWire(NEW_ID, b_width);
RTLIL::SigSpec a = module->addWire(NEW_TWINE, a_width);
RTLIL::SigSpec b = module->addWire(NEW_TWINE, b_width);
supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a));
supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID::B_SIGNED] = b_signed;
supercell->parameters[ID::A_WIDTH] = a_width;
supercell->parameters[ID::B_WIDTH] = b_width;
supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::B, b);
supercell->setPort(ID::Y, y);
supercell->setPort(TW::A, a);
supercell->setPort(TW::B, b);
supercell->setPort(TW::Y, y);
if (c1->type == ID($alu)) {
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
supercell->setPort(ID::CI, ci);
supercell->setPort(ID::BI, bi);
supercell->setPort(ID::CO, co);
supercell->setPort(ID::X, x);
RTLIL::Wire *ci = module->addWire(NEW_TWINE), *bi = module->addWire(NEW_TWINE);
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(TW::CI), c1->getPort(TW::CI), act, ci));
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(TW::BI), c1->getPort(TW::BI), act, bi));
supercell->setPort(TW::CI, ci);
supercell->setPort(TW::BI, bi);
supercell->setPort(TW::CO, co);
supercell->setPort(TW::X, x);
}
supercell->check();
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
if (c1->type == ID($alu)) {
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(TW::CO)));
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(TW::CO)));
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(TW::X)));
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(TW::X)));
}
supercell_aux.insert(supercell);
@ -695,7 +695,7 @@ struct ShareWorker
if (c1->type == ID($macc))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
supercell_aux.insert(supercell);
share_macc(c1, c2, act, supercell, &supercell_aux);
supercell->check();
@ -704,16 +704,16 @@ struct ShareWorker
if (c1->type.in(ID($memrd), ID($memrd_v2)))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR);
RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR);
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1);
RTLIL::SigSpec addr1 = c1->getPort(TW::ADDR);
RTLIL::SigSpec addr2 = c2->getPort(TW::ADDR);
if (GetSize(addr1) < GetSize(addr2))
addr1.extend_u0(GetSize(addr2));
else
addr2.extend_u0(GetSize(addr1));
supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
supercell->setPort(TW::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1));
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(TW::DATA), c2->getPort(TW::DATA)));
supercell_aux.insert(supercell);
return supercell;
}
@ -745,7 +745,7 @@ struct ShareWorker
for (auto &bit : pbits) {
if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID::S)
forbidden_controls_cache[cell].insert(bit.cell->getPort(ID::S).extract(bit.offset, 1));
forbidden_controls_cache[cell].insert(bit.cell->getPort(TW::S).extract(bit.offset, 1));
consumer_cells.insert(bit.cell);
}
@ -909,9 +909,9 @@ struct ShareWorker
std::set<int> used_in_b_parts;
int width = c->parameters.at(ID::WIDTH).as_int();
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID::B));
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID::S));
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(TW::A));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(TW::B));
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(TW::S));
for (auto &bit : sig_a)
if (cell_out_bits.count(bit))
@ -1059,7 +1059,7 @@ struct ShareWorker
RTLIL::SigSpec make_cell_activation_logic(const pool<ssc_pair_t> &activation_patterns, pool<RTLIL::Cell*> &supercell_aux)
{
RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
RTLIL::Wire *all_cases_wire = module->addWire(NEW_TWINE, 0);
for (auto &p : activation_patterns) {
all_cases_wire->width++;
@ -1069,7 +1069,7 @@ struct ShareWorker
if (all_cases_wire->width == 1)
return all_cases_wire;
RTLIL::Wire *result_wire = module->addWire(NEW_ID);
RTLIL::Wire *result_wire = module->addWire(NEW_TWINE);
supercell_aux.insert(module->addReduceOr(NEW_ID, all_cases_wire, result_wire));
return result_wire;
}

60
passes/opt/wreduce.cc
View file

@ -66,10 +66,10 @@ struct WreduceWorker
{
// Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
SigSpec sig_b = mi.sigmap(cell->getPort(ID::B));
SigSpec sig_s = mi.sigmap(cell->getPort(ID::S));
SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y));
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A));
SigSpec sig_b = mi.sigmap(cell->getPort(TW::B));
SigSpec sig_s = mi.sigmap(cell->getPort(TW::S));
SigSpec sig_y = mi.sigmap(cell->getPort(TW::Y));
std::vector<SigBit> bits_removed;
if (sig_y.has_const())
@ -132,9 +132,9 @@ struct WreduceWorker
for (auto bit : new_work_queue_bits)
work_queue_bits.insert(bit);
cell->setPort(ID::A, new_sig_a);
cell->setPort(ID::B, new_sig_b);
cell->setPort(ID::Y, new_sig_y);
cell->setPort(TW::A, new_sig_a);
cell->setPort(TW::B, new_sig_b);
cell->setPort(TW::Y, new_sig_y);
cell->fixup_parameters();
module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
@ -144,8 +144,8 @@ struct WreduceWorker
{
// Reduce size of FF if inputs are just sign/zero extended or output bit is not used
SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
SigSpec sig_d = mi.sigmap(cell->getPort(TW::D));
SigSpec sig_q = mi.sigmap(cell->getPort(TW::Q));
bool has_reset = false;
Const rst_value;
std::vector<State> initval = initvals(sig_q).to_bits();
@ -234,9 +234,9 @@ struct WreduceWorker
cell->setParam(ID::SRST_VALUE, rst_value);
}
cell->setPort(ID::D, sig_d);
cell->setPort(ID::Q, sig_q);
initvals.set_init(cell->getPort(ID::Q), initval);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
initvals.set_init(cell->getPort(TW::Q), initval);
cell->fixup_parameters();
}
@ -298,7 +298,7 @@ struct WreduceWorker
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch)))
return run_cell_dff(cell);
SigSpec sig = mi.sigmap(cell->getPort(ID::Y));
SigSpec sig = mi.sigmap(cell->getPort(TW::Y));
if (sig.has_const())
return;
@ -306,8 +306,8 @@ struct WreduceWorker
// Reduce size of ports A and B based on constant input bits and size of output port
int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : -1;
int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : -1;
int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : -1;
int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : -1;
if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) {
max_port_a_size = min(max_port_a_size, GetSize(sig));
@ -322,7 +322,7 @@ struct WreduceWorker
if (cell->type.in(ID($mul), ID($add), ID($sub)) &&
max_port_a_size == GetSize(sig) &&
max_port_b_size == GetSize(sig)) {
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B));
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B));
// Remove top bits from sig_a and sig_b which are not visible on the output
sig_a.extend_u0(max_port_a_size);
@ -363,7 +363,7 @@ struct WreduceWorker
run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something);
if (cell->hasPort(ID::A) && cell->hasPort(ID::B) && port_a_signed && port_b_signed) {
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B));
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
@ -377,7 +377,7 @@ struct WreduceWorker
}
if (cell->hasPort(ID::A) && !cell->hasPort(ID::B) && port_a_signed) {
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
module, cell, cell->type.unescape());
@ -414,8 +414,8 @@ struct WreduceWorker
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub);
int a_size = 0, b_size = 0;
if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A));
if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(ID::B));
if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(TW::A));
if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(TW::B));
int max_y_size = max(a_size, b_size);
@ -447,7 +447,7 @@ struct WreduceWorker
if (bits_removed) {
log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescape());
cell->setPort(ID::Y, sig);
cell->setPort(TW::Y, sig);
did_something = true;
}
@ -519,7 +519,7 @@ struct WreduceWorker
continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), module, w);
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
Wire *nw = module->addWire(NEW_TWINE, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
}
@ -591,10 +591,10 @@ struct WreducePass : public Pass {
{
if (c->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(ID::Y)) > 1) {
SigSpec sig = c->getPort(ID::Y);
ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(TW::Y)) > 1) {
SigSpec sig = c->getPort(TW::Y);
if (!sig.has_const()) {
c->setPort(ID::Y, sig[0]);
c->setPort(TW::Y, sig[0]);
c->setParam(ID::Y_WIDTH, 1);
sig.remove(0);
module->connect(sig, Const(0, GetSize(sig)));
@ -603,7 +603,7 @@ struct WreducePass : public Pass {
if (c->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
{
SigSpec A = c->getPort(ID::A);
SigSpec A = c->getPort(TW::A);
int original_a_width = GetSize(A);
if (c->getParam(ID::A_SIGNED).as_bool()) {
while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0)
@ -615,11 +615,11 @@ struct WreducePass : public Pass {
if (original_a_width != GetSize(A)) {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, module, c, c->type.unescape());
c->setPort(ID::A, A);
c->setPort(TW::A, A);
c->setParam(ID::A_WIDTH, GetSize(A));
}
SigSpec B = c->getPort(ID::B);
SigSpec B = c->getPort(TW::B);
int original_b_width = GetSize(B);
if (c->getParam(ID::B_SIGNED).as_bool()) {
while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0)
@ -631,7 +631,7 @@ struct WreducePass : public Pass {
if (original_b_width != GetSize(B)) {
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, module, c, c->type.unescape());
c->setPort(ID::B, B);
c->setPort(TW::B, B);
c->setParam(ID::B_WIDTH, GetSize(B));
}
}
@ -648,7 +648,7 @@ struct WreducePass : public Pass {
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
module, c, memid.unescape());
c->setParam(ID::ABITS, max_addrbits);
c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
c->setPort(TW::ADDR, c->getPort(TW::ADDR).extract(0, max_addrbits));
}
}
}