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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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6
passes/memory/memory_bmux2rom.cc
View file

@ -50,7 +50,7 @@ struct MemoryBmux2RomPass : public Pass {
if (cell->type != ID($bmux))
continue;
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_a = cell->getPort(TW::A);
if (!sig_a.is_fully_const())
continue;
@ -70,8 +70,8 @@ struct MemoryBmux2RomPass : public Pass {
mem.inits.push_back(std::move(init));
MemRd rd;
rd.addr = cell->getPort(ID::S);
rd.data = cell->getPort(ID::Y);
rd.addr = cell->getPort(TW::S);
rd.data = cell->getPort(TW::Y);
rd.init_value = Const(State::Sx, width);
rd.arst_value = Const(State::Sx, width);
rd.srst_value = Const(State::Sx, width);

6
passes/memory/memory_bram.cc
View file

@ -903,7 +903,7 @@ grow_read_ports:;
// Swizzle read ports.
for (auto &port : mem.rd_ports) {
SigSpec new_data = module->addWire(NEW_ID, mem.width);
SigSpec new_data = module->addWire(NEW_TWINE, mem.width);
Const new_init_value = Const(State::Sx, mem.width);
Const new_arst_value = Const(State::Sx, mem.width);
Const new_srst_value = Const(State::Sx, mem.width);
@ -1023,12 +1023,12 @@ grow_read_ports:;
auto &port = mem.rd_ports[pi.mapped_port];
SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits);
SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits);
SigSpec bram_dout = module->addWire(NEW_TWINE, bram.dbits);
c->setPort(stringf("\\%sDATA", pf), bram_dout);
SigSpec addr_ok_q = addr_ok;
if (port.clk_enable && !addr_ok.empty()) {
addr_ok_q = module->addWire(NEW_ID);
addr_ok_q = module->addWire(NEW_TWINE);
module->addDffe(NEW_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity);
}

10
passes/memory/memory_dff.cc
View file

@ -177,7 +177,7 @@ struct MemQueryCache
if (!driver.cell->type.in(ID($mux), ID($pmux)))
return false;
log_assert(driver.port == ID::Y);
SigSpec sig_s = driver.cell->getPort(ID::S);
SigSpec sig_s = driver.cell->getPort(TW::S);
int sel_sat = qcsat.importSigBit(sel);
if (neg_sel)
sel_sat = qcsat.ez->NOT(sel_sat);
@ -187,14 +187,14 @@ struct MemQueryCache
int sbit = qcsat.importSigBit(sig_s[i]);
qcsat.prepare();
if (!qcsat.ez->solve(port_ren, sel_sat, qcsat.ez->NOT(sbit))) {
bit = driver.cell->getPort(ID::B)[i * width + driver.offset];
bit = driver.cell->getPort(TW::B)[i * width + driver.offset];
return true;
}
if (qcsat.ez->solve(port_ren, sel_sat, sbit))
all_0 = false;
}
if (all_0) {
bit = driver.cell->getPort(ID::A)[driver.offset];
bit = driver.cell->getPort(TW::A)[driver.offset];
return true;
}
return false;
@ -264,7 +264,7 @@ struct MemoryDffWorker
} else {
continue;
}
SigSpec y = consumer.cell->getPort(ID::Y);
SigSpec y = consumer.cell->getPort(TW::Y);
int mux_width = GetSize(y);
SigBit ybit = y.extract(consumer.offset);
if (prev_cell != consumer.cell || prev_idx+1 != i || prev_is_b != is_b) {
@ -272,7 +272,7 @@ struct MemoryDffWorker
md.base_idx = i;
md.size = 0;
md.is_b = is_b;
md.sig_s = consumer.cell->getPort(ID::S);
md.sig_s = consumer.cell->getPort(TW::S);
md.sig_other.resize(GetSize(md.sig_s));
prev_cell = consumer.cell;
prev_is_b = is_b;

16
passes/memory/memory_libmap.cc
View file

@ -142,13 +142,13 @@ struct MapWorker {
{
if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
if (sig_a.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
sigmap_xmux.add(cell->getPort(TW::Y), sig_b);
else if (sig_b.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
}
}
@ -1665,14 +1665,14 @@ std::vector<SigSpec> generate_mux(Mem &mem, int rpidx, const Swizzle &swz) {
return {port.data};
}
if (port.clk_enable) {
SigSpec new_sig_s = mem.module->addWire(NEW_ID, GetSize(sig_s));
SigSpec new_sig_s = mem.module->addWire(NEW_TWINE, GetSize(sig_s));
mem.module->addDffe(NEW_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity);
sig_s = new_sig_s;
}
SigSpec sig_a = Const(State::Sx, GetSize(port.data) << hi_bits << GetSize(swz.addr_mux_bits));
for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) {
for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) {
SigSpec sig = mem.module->addWire(NEW_ID, GetSize(port.data));
SigSpec sig = mem.module->addWire(NEW_TWINE, GetSize(port.data));
int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1);
int pos = (hi << GetSize(swz.addr_mux_bits) | j) * GetSize(port.data);
for (int k = 0; k < GetSize(port.data); k++)
@ -1948,7 +1948,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), hw_val);
}
}
SigSpec hw_rdata = mem.module->addWire(NEW_ID, width);
SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width);
cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata);
SigSpec lhs;
SigSpec rhs;
@ -1983,7 +1983,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
else if (pdef.rdsrstval == ResetValKind::NoUndef)
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), Const(State::S0, width));
}
SigSpec hw_rdata = mem.module->addWire(NEW_ID, width);
SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width);
cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata);
}
}

34
passes/memory/memory_map.cc
View file

@ -241,7 +241,7 @@ struct MemoryMapWorker
} else {
c = module->addCell(ff_id, ID($dff));
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
c->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::S0));
}
} else if (async_wr) {
log_assert(formal); // General async write not implemented yet, checked against above
@ -249,14 +249,14 @@ struct MemoryMapWorker
} else {
c = module->addCell(ff_id, ID($dff));
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol);
c->setPort(ID::CLK, refclock);
c->setPort(TW::CLK, refclock);
}
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = mem.width;
RTLIL::Wire *w_in = module->addWire(genid(mem.memid, "", addr, "$d"), mem.width);
data_reg_in[idx] = w_in;
c->setPort(ID::D, w_in);
c->setPort(TW::D, w_in);
std::string w_out_name = stringf("%s[%d]", mem.memid, addr);
if (module->wire(RTLIL::IdString(w_out_name)) != nullptr)
@ -276,7 +276,7 @@ struct MemoryMapWorker
w_out->attributes[ID::init] = w_init.as_const();
data_reg_out[idx] = w_out;
c->setPort(ID::Q, w_out);
c->setPort(TW::Q, w_out);
if (static_only)
module->connect(RTLIL::SigSig(w_in, w_out));
@ -308,15 +308,15 @@ struct MemoryMapWorker
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$rdmux", i, "", j, "", k), ID($mux));
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = GetSize(port.data);
c->setPort(ID::Y, rd_signals[k]);
c->setPort(ID::S, rd_addr.extract(abits-j-1, 1));
c->setPort(TW::Y, rd_signals[k]);
c->setPort(TW::S, rd_addr.extract(abits-j-1, 1));
count_mux++;
c->setPort(ID::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data)));
c->setPort(ID::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data)));
c->setPort(TW::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data)));
c->setPort(TW::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data)));
next_rd_signals.push_back(c->getPort(ID::A));
next_rd_signals.push_back(c->getPort(ID::B));
next_rd_signals.push_back(c->getPort(TW::A));
next_rd_signals.push_back(c->getPort(TW::B));
}
next_rd_signals.swap(rd_signals);
@ -372,22 +372,22 @@ struct MemoryMapWorker
c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
c->parameters[ID::B_WIDTH] = RTLIL::Const(1);
c->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
c->setPort(ID::A, w);
c->setPort(ID::B, wr_bit);
c->setPort(TW::A, w);
c->setPort(TW::B, wr_bit);
w = module->addWire(genid(mem.memid, "$wren", addr, "", j, "", wr_offset, "$y"));
c->setPort(ID::Y, RTLIL::SigSpec(w));
c->setPort(TW::Y, RTLIL::SigSpec(w));
}
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset), ID($mux));
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = wr_width;
c->setPort(ID::A, sig.extract(wr_offset, wr_width));
c->setPort(ID::B, port.data.extract(wr_offset + sub * mem.width, wr_width));
c->setPort(ID::S, RTLIL::SigSpec(w));
c->setPort(TW::A, sig.extract(wr_offset, wr_width));
c->setPort(TW::B, port.data.extract(wr_offset + sub * mem.width, wr_width));
c->setPort(TW::S, RTLIL::SigSpec(w));
w = module->addWire(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset, "$y"), wr_width);
c->setPort(ID::Y, w);
c->setPort(TW::Y, w);
sig.replace(wr_offset, w);
wr_offset += wr_width;

2
passes/memory/memory_memx.cc
View file

@ -63,7 +63,7 @@ struct MemoryMemxPass : public Pass {
module, mem.memid.unescape());
SigSpec addr_ok = make_addr_check(mem, port.addr);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data));
Wire *raw_rdata = module->addWire(NEW_TWINE, GetSize(port.data));
module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data);
port.data = raw_rdata;
}

12
passes/memory/memory_share.cc
View file

@ -164,7 +164,7 @@ struct MemoryShareWorker
port2.addr = addr2;
mem.prepare_rd_merge(i, j, &initvals);
mem.widen_prep(wide_log2);
SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2);
SigSpec new_data = module->addWire(NEW_TWINE, mem.width << wide_log2);
module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2));
module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2));
for (int k = 0; k < wide_log2; k++)
@ -438,7 +438,7 @@ struct MemoryShareWorker
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
RTLIL::Wire *grouped_en = module->addWire(NEW_TWINE, 0);
for (int j = 0; j < int(this_en.size()); j++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
@ -484,13 +484,13 @@ struct MemoryShareWorker
{
if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
if (sig_a.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
sigmap_xmux.add(cell->getPort(TW::Y), sig_b);
else if (sig_b.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
}