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WIP
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parent
015ab4e45b
commit
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203 changed files with 4575 additions and 4481 deletions
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@ -19,18 +19,18 @@ struct TestPatchPass : public Pass {
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for (auto cell : module->selected_cells()) {
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if (cell->type == ID($add)) {
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Cell* add = cell;
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log_assert(add->getPort(ID::B).is_wire());
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log_assert(add->getPort(ID::B).known_driver());
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auto neg = add->getPort(ID::B)[0].wire->driverCell();
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log_assert(add->getPort(TW::B).is_wire());
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log_assert(add->getPort(TW::B).known_driver());
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auto neg = add->getPort(TW::B)[0].wire->driverCell();
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log_assert(neg->type == ID($not));
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RTLIL::Patch patcher(module, nullptr);
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int width = cell->getPort(ID::A).size();
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int width = cell->getPort(TW::A).size();
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auto sub = patcher.addSub(NEW_ID,
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neg->getPort(ID::A),
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add->getPort(ID::A),
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patcher.addWire(NEW_ID, width));
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auto new_out_wire = patcher.addWire(NEW_ID, width);
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auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(ID::Y), new_out_wire);
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neg->getPort(TW::A),
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add->getPort(TW::A),
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patcher.addWire(NEW_TWINE, width));
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auto new_out_wire = patcher.addWire(NEW_TWINE, width);
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auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(TW::Y), new_out_wire);
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log_cell(new_cell);
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patcher.patch(add, ID::Y, new_out_wire);
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}
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