mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-24 08:02:32 +00:00
Code Activity

WIP

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/cmds/abstract.cc
View file

@ -102,7 +102,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o
}
bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, EnableLogic enable) {
Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size());
Wire* abstracted = ff.module->addWire(NEW_TWINE, offsets.size());
SigSpec mux_input;
int abstracted_idx = 0;
for (int d_idx = 0; d_idx < ff.width; d_idx++) {
@ -213,7 +213,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
}
bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, IdString port_name, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, offsets.size());
Wire* to_abstract = mod->addWire(NEW_TWINE, offsets.size());
SigSpec mux_input;
SigSpec mux_output;
const SigSpec& old_port = cell->getPort(port_name);
@ -235,7 +235,7 @@ bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, Id
}
bool abstract_value_mod_port(Module* mod, Wire* wire, std::set<int> offsets, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, wire);
Wire* to_abstract = mod->addWire(NEW_TWINE, wire);
to_abstract->port_input = true;
to_abstract->port_id = wire->port_id;
wire->port_input = false;
@ -507,7 +507,7 @@ struct AbstractPass : public Pass {
case Enable::Initstates: {
SigBit in_init_states = mod->Initstate(NEW_ID);
for (int i = 1; i < initstates; i++) {
Wire *in_init_states_q = mod->addWire(NEW_ID);
Wire *in_init_states_q = mod->addWire(NEW_TWINE);
mod->addFf(NEW_ID, in_init_states, in_init_states_q);
in_init_states_q->attributes[ID::init] = State::S1;
in_init_states = in_init_states_q;

8
passes/cmds/add.cc
View file

@ -41,10 +41,10 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
formal_cell->setPort(ID::A, wire);
RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, "$" + celltype);
formal_cell->setPort(TW::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID::EN, State::S1);
formal_cell->setPort(TW::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name);
}
else {
@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name);
formal_cell->setPort(ID::EN, enable_wire);
formal_cell->setPort(TW::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name);
}
}

2
passes/cmds/bugpoint.cc
View file

@ -306,7 +306,7 @@ struct BugpointPass : public Pass {
if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
{
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
RTLIL::Wire *wire = mod->addWire(NEW_TWINE, port.size());
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
wire->port_output = cell->output(it.first);

10
passes/cmds/check.cc
View file

@ -304,8 +304,8 @@ struct CheckPass : public Pass {
if (cell->type.in(ID($pmux), ID($bmux))) {
// We're skipping inputs A and B, since each of their bits contributes only one edge
in_widths = GetSize(cell->getPort(ID::S));
out_widths = GetSize(cell->getPort(ID::Y));
in_widths = GetSize(cell->getPort(TW::S));
out_widths = GetSize(cell->getPort(TW::Y));
} else {
for (auto &conn : cell->connections()) {
if (cell->input(conn.first))
@ -370,8 +370,8 @@ struct CheckPass : public Pass {
if (cell->type == ID($connect)) {
// Inefficient, but rare case in sane design
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
for (int i = 0; i < sig_a.size(); i++) {
int count_a = wire_drivers_count[sig_a[i]];
int count_b = wire_drivers_count[sig_b[i]];
@ -561,7 +561,7 @@ struct CheckPass : public Pass {
if (cell->is_builtin_ff() == 0)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
init_bits.erase(bit);
}

60
passes/cmds/chformal.cc
View file

@ -275,15 +275,15 @@ struct ChformalPass : public Pass {
for (auto cell : module->selected_cells())
{
if (cell->type == ID($ff)) {
SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort(ID::Q));
SigSpec D = sigmap(cell->getPort(TW::D));
SigSpec Q = sigmap(cell->getPort(TW::Q));
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
}
if (cell->type == ID($dff)) {
SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort(ID::Q));
SigSpec C = sigmap(cell->getPort(ID::CLK));
SigSpec D = sigmap(cell->getPort(TW::D));
SigSpec Q = sigmap(cell->getPort(TW::Q));
SigSpec C = sigmap(cell->getPort(TW::CLK));
bool clockpol = cell->getParam(ID::CLK_POLARITY).as_bool();
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol));
@ -295,7 +295,7 @@ struct ChformalPass : public Pass {
if (is_triggered_check_cell(cell)) {
if (cell->getParam(ID::TRG_WIDTH).as_int() != 1)
continue;
cell->setPort(ID::TRG, SigSpec());
cell->setPort(TW::TRG, SigSpec());
cell->setParam(ID::TRG_ENABLE, false);
cell->setParam(ID::TRG_WIDTH, 0);
cell->setParam(ID::TRG_POLARITY, false);
@ -305,8 +305,8 @@ struct ChformalPass : public Pass {
while (true)
{
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec EN = sigmap(cell->getPort(ID::EN));
SigSpec A = sigmap(cell->getPort(TW::A));
SigSpec EN = sigmap(cell->getPort(TW::EN));
if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
break;
@ -322,8 +322,8 @@ struct ChformalPass : public Pass {
if (A_map.second != EN_map.second)
break;
cell->setPort(ID::A, A_map.first);
cell->setPort(ID::EN, EN_map.first);
cell->setPort(TW::A, A_map.first);
cell->setPort(TW::EN, EN_map.first);
}
}
}
@ -337,18 +337,18 @@ struct ChformalPass : public Pass {
for (int i = 0; i < mode_arg; i++)
{
SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort(ID::EN);
SigSpec orig_a = cell->getPort(TW::A);
SigSpec orig_en = cell->getPort(TW::EN);
Wire *new_a = module->addWire(NEW_ID);
Wire *new_en = module->addWire(NEW_ID);
Wire *new_a = module->addWire(NEW_TWINE);
Wire *new_en = module->addWire(NEW_TWINE);
new_en->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
cell->setPort(ID::A, new_a);
cell->setPort(ID::EN, new_en);
cell->setPort(TW::A, new_a);
cell->setPort(TW::EN, new_en);
}
}
}
@ -358,14 +358,14 @@ struct ChformalPass : public Pass {
SigSpec en = State::S1;
for (int i = 0; i < mode_arg; i++) {
Wire *w = module->addWire(NEW_ID);
Wire *w = module->addWire(NEW_TWINE);
w->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, en, w);
en = w;
}
for (auto cell : constr_cells)
cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
cell->setPort(TW::EN, module->LogicAnd(NEW_ID, en, cell->getPort(TW::EN)));
}
else
if (mode =='p')
@ -373,7 +373,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
{
if (cell->type == ID($check)) {
Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check));
Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), ID($check));
cover->attributes = cell->attributes;
if (cell->src_id() != Twine::Null && module->design)
cover->set_src_id(cell->src_id());
@ -383,11 +383,11 @@ struct ChformalPass : public Pass {
for (auto const &conn : cell->connections())
if (!conn.first.in(ID::A, ID::EN))
cover->setPort(conn.first, conn.second);
cover->setPort(ID::A, cell->getPort(ID::EN));
cover->setPort(ID::EN, State::S1);
cover->setPort(TW::A, cell->getPort(TW::EN));
cover->setPort(TW::EN, State::S1);
} else {
module->addCover(NEW_ID_SUFFIX("coverenable"),
cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
cell->getPort(TW::EN), State::S1, cell->get_src_attribute());
}
}
}
@ -419,17 +419,17 @@ struct ChformalPass : public Pass {
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", cell);
Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell));
Cell *plain_cell = module->addCell(NEW_TWINE, formal_flavor(cell));
plain_cell->attributes = cell->attributes;
if (cell->src_id() != Twine::Null && module->design)
plain_cell->set_src_id(cell->src_id());
SigBit sig_a = cell->getPort(ID::A);
SigBit sig_en = cell->getPort(ID::EN);
SigBit sig_a = cell->getPort(TW::A);
SigBit sig_en = cell->getPort(TW::EN);
plain_cell->setPort(ID::A, sig_a);
plain_cell->setPort(ID::EN, sig_en);
plain_cell->setPort(TW::A, sig_a);
plain_cell->setPort(TW::EN, sig_en);
if (plain_cell->type.in(ID($assert), ID($assume)))
sig_a = module->Not(NEW_ID, sig_a);
@ -438,12 +438,12 @@ struct ChformalPass : public Pass {
module->swap_names(cell, plain_cell);
if (cell->getPort(ID::ARGS).empty()) {
if (cell->getPort(TW::ARGS).empty()) {
module->remove(cell);
} else {
cell->type = ID($print);
cell->setPort(ID::EN, combined_en);
cell->unsetPort(ID::A);
cell->setPort(TW::EN, combined_en);
cell->unsetPort(TW::A);
cell->unsetParam(ID(FLAVOR));
}
}

16
passes/cmds/clean_zerowidth.cc
View file

@ -77,7 +77,7 @@ struct CleanZeroWidthPass : public Pass {
// Coarse FF cells: remove if WIDTH == 0 (no outputs).
// This will also trigger on fine cells, so use the Q port
// width instead of actual WIDTH parameter.
if (GetSize(cell->getPort(ID::Q)) == 0) {
if (GetSize(cell->getPort(TW::Q)) == 0) {
module->remove(cell);
}
} else if (cell->type.in(ID($pmux), ID($bmux), ID($demux))) {
@ -87,17 +87,17 @@ struct CleanZeroWidthPass : public Pass {
module->remove(cell);
}
if (cell->getParam(ID::S_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
module->remove(cell);
}
} else if (cell->type == ID($concat)) {
// If a concat has a zero-width input: replace with direct
// connection to the other input.
if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::B));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::B));
module->remove(cell);
} else if (cell->getParam(ID::B_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
module->remove(cell);
}
} else if (cell->type == ID($fsm)) {
@ -107,7 +107,7 @@ struct CleanZeroWidthPass : public Pass {
} else if (cell->type == ID($lut)) {
// Zero-width LUT is just a const driver.
if (cell->getParam(ID::WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getParam(ID::LUT)[0]);
module->connect(cell->getPort(TW::Y), cell->getParam(ID::LUT)[0]);
module->remove(cell);
}
} else if (cell->type == ID($sop)) {
@ -115,7 +115,7 @@ struct CleanZeroWidthPass : public Pass {
if (cell->getParam(ID::WIDTH).as_int() == 0) {
// The value is 1 iff DEPTH is non-0.
bool val = cell->getParam(ID::DEPTH).as_int() != 0;
module->connect(cell->getPort(ID::Y), val);
module->connect(cell->getPort(TW::Y), val);
module->remove(cell);
}
} else if (cell->hasParam(ID::WIDTH)) {
@ -132,11 +132,11 @@ struct CleanZeroWidthPass : public Pass {
// TODO: fixing zero-width A and B not supported.
} else {
if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
cell->setPort(ID::A, State::S0);
cell->setPort(TW::A, State::S0);
cell->setParam(ID::A_WIDTH, 1);
}
if (cell->hasParam(ID::B_WIDTH) && cell->getParam(ID::B_WIDTH).as_int() == 0) {
cell->setPort(ID::B, State::S0);
cell->setPort(TW::B, State::S0);
cell->setParam(ID::B_WIDTH, 1);
}
}

2
passes/cmds/connect.cc
View file

@ -30,7 +30,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{
CellTypes ct(design);
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
RTLIL::Wire *dummy_wire = module->addWire(NEW_TWINE, sig.size());
// (void)module->connections(); // trigger signorm flush

94
passes/cmds/dft_tag.cc
View file

@ -98,10 +98,10 @@ struct DftTagWorker {
}
for (auto cell : overwrite_cells) {
log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(ID::A)));
SigSpec orig_signal = cell->getPort(ID::A);
log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(TW::A)));
SigSpec orig_signal = cell->getPort(TW::A);
SigSpec interposed_signal = divert_users(orig_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(TW::SET), cell->getPort(TW::CLR), interposed_signal);
modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections
design_changed = true;
}
@ -123,7 +123,7 @@ struct DftTagWorker {
signal_mapped.sort_and_unify();
if (GetSize(signal_mapped) < GetSize(signal))
log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal));
SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal));
SigSpec new_wire = module->addWire(NEW_TWINE, GetSize(signal));
for (int i = 0; i < GetSize(new_wire); ++i)
divert_users(signal[i], new_wire[i]);
return new_wire;
@ -359,7 +359,7 @@ struct DftTagWorker {
// when the outer call for this tag/cell returns
for (auto &conn : cell->connections())
if (cell->output(conn.first))
emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second)));
emit_tag_signal(tag, conn.second, module->addWire(NEW_TWINE, GetSize(conn.second)));
return;
}
@ -380,8 +380,8 @@ struct DftTagWorker {
group_of_tag[tag] = tag_group;
}
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
// TODO handle constant set/clr masks
add_tags(sig_y, singleton(tag));
forward_tags(sig_y, sig_a);
@ -393,8 +393,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($not), ID($pos))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type.in(ID($not), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
}
@ -403,9 +403,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -416,10 +416,10 @@ struct DftTagWorker {
}
if (cell->type.in(ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -445,7 +445,7 @@ struct DftTagWorker {
ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
ID($eq), ID($ne)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_y = cell->getPort(TW::Y);
add_tags(sig_y[0], tags(cell));
return;
@ -480,12 +480,12 @@ struct DftTagWorker {
if (cell->type == ID($set_tag)) {
IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A));
auto &sig_y = cell->getPort(ID::Y);
auto tag_sig_a = tag_signal(tag, cell->getPort(TW::A));
auto &sig_y = cell->getPort(TW::Y);
if (cell_tag == tag) {
auto &sig_set = cell->getPort(ID::SET);
auto &sig_clr = cell->getPort(ID::CLR);
auto &sig_set = cell->getPort(TW::SET);
auto &sig_clr = cell->getPort(TW::CLR);
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr));
tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set);
}
@ -499,8 +499,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type.in(ID($not), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
}
@ -512,9 +512,9 @@ struct DftTagWorker {
ID($and), ID($or),
ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -555,9 +555,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -573,10 +573,10 @@ struct DftTagWorker {
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -607,9 +607,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -636,9 +636,9 @@ struct DftTagWorker {
if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -667,8 +667,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto group_sig_a = tag_group_signal(tag, sig_a);
auto tag_sig_a = tag_signal(tag, sig_a);
@ -701,7 +701,7 @@ struct DftTagWorker {
ff.name = NEW_ID;
ff.cell = nullptr;
ff.sig_d = tag_signal(tag, ff.sig_d);
ff.sig_q = module->addWire(NEW_ID, width);
ff.sig_q = module->addWire(NEW_TWINE, width);
ff.is_anyinit = false;
ff.val_init = Const(0, width);
ff.emit();
@ -751,7 +751,7 @@ struct DftTagWorker {
get_tag_cells.push_back(cell);
for (auto cell : get_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
tag_signal(tag, sig_a);
@ -808,15 +808,15 @@ struct DftTagWorker {
}
for (auto cell : set_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_y = cell->getPort(TW::Y);
module->connect(sig_y, sig_a);
module->remove(cell);
}
for (auto cell : get_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_y = cell->getPort(TW::Y);
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
auto tag_sig = tag_signal(tag, sig_a);

2
passes/cmds/future.cc
View file

@ -53,7 +53,7 @@ struct FutureWorker {
if (cell->type != ID($future_ff))
continue;
module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A)));
module->connect(cell->getPort(TW::Y), future_ff(cell->getPort(TW::A)));
replaced_cells.push_back(cell);
}

8
passes/cmds/glift.cc
View file

@ -189,7 +189,7 @@ private:
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
const unsigned int A = 0, B = 1, Y = 2;
const unsigned int NUM_PORTS = 3;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1)
@ -254,7 +254,7 @@ private:
else if (cell->type.in(ID($_XOR_), ID($_XNOR_))) {
const unsigned int A = 0, B = 1, Y = 2;
const unsigned int NUM_PORTS = 3;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1)
@ -310,7 +310,7 @@ private:
else if (cell->type.in(ID($_MUX_), ID($_NMUX_))) {
const unsigned int A = 0, B = 1, S = 2, Y = 3;
const unsigned int NUM_PORTS = 4;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::S), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::S), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[S].size() != 1 || ports[Y].size() != 1)
@ -323,7 +323,7 @@ private:
else if (cell->type.in(ID($_NOT_))) {
const unsigned int A = 0, Y = 1;
const unsigned int NUM_PORTS = 2;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[Y].size() != 1)

10
passes/cmds/portarcs.cc
View file

@ -32,7 +32,7 @@ static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit)
RTLIL::Wire *w;
while ((w = bit.wire) != NULL && !w->port_input &&
w->driverCell()->type.in(ID($buf), ID($_BUF_))) {
bit = w->driverCell()->getPort(ID::A)[bit.offset];
bit = w->driverCell()->getPort(TW::A)[bit.offset];
}
return bit;
}
@ -292,7 +292,7 @@ struct PortarcsPass : Pass {
int *p = annotations.at(canonical_bit(bit));
for (auto i = 0; i < inputs.size(); i++) {
if (p[i] >= 0) {
Cell *spec = m->addCell(NEW_ID, ID($specify2));
Cell *spec = m->addCell(NEW_TWINE, ID($specify2));
spec->setParam(ID::SRC_WIDTH, 1);
spec->setParam(ID::DST_WIDTH, 1);
spec->setParam(ID::T_FALL_MAX, p[i]);
@ -304,9 +304,9 @@ struct PortarcsPass : Pass {
spec->setParam(ID::SRC_DST_POL, false);
spec->setParam(ID::SRC_DST_PEN, false);
spec->setParam(ID::FULL, false);
spec->setPort(ID::EN, Const(1, 1));
spec->setPort(ID::SRC, inputs[i]);
spec->setPort(ID::DST, bit);
spec->setPort(TW::EN, Const(1, 1));
spec->setPort(TW::SRC, inputs[i]);
spec->setPort(TW::DST, bit);
}
}
}

2
passes/cmds/scatter.cc
View file

@ -51,7 +51,7 @@ struct ScatterPass : public Pass {
for (auto cell : module->cells()) {
dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
for (auto conn : cell->connections())
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_TWINE, GetSize(conn.second))));
for (auto &it : new_connections) {
if (ct.cell_output(cell->type, it.first))
module->connect(RTLIL::SigSig(it.second.first, it.second.second));

4
passes/cmds/scc.cc
View file

@ -152,14 +152,14 @@ struct SccWorker
if (subcell->type != ID($specify2))
continue;
for (auto bit : subcell->getPort(ID::SRC))
for (auto bit : subcell->getPort(TW::SRC))
{
if (!bit.wire || !cell->hasPort(bit.wire->name))
continue;
inputSignals.append(sigmap(cell->getPort(bit.wire->name)));
}
for (auto bit : subcell->getPort(ID::DST))
for (auto bit : subcell->getPort(TW::DST))
{
if (!bit.wire || !cell->hasPort(bit.wire->name))
continue;

4
passes/cmds/setundef.cc
View file

@ -371,13 +371,13 @@ struct SetundefPass : public Pass {
bool cell_selected = design->selected(module, cell);
bool wire_selected = false;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
if (bit.wire && design->selected(module, bit.wire))
wire_selected = true;
if (!cell_selected && !wire_selected)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
ffbits.insert(bit);
}

18
passes/cmds/splice.cc
View file

@ -75,13 +75,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($slice));
cell->parameters[ID::OFFSET] = offset;
cell->parameters[ID::A_WIDTH] = sig_a.size();
cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
cell->setPort(TW::A, sig_a);
cell->setPort(TW::Y, module->addWire(NEW_TWINE, sig.size()));
new_sig = cell->getPort(TW::Y);
}
sliced_signals_cache[sig] = new_sig;
@ -132,13 +132,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($concat));
cell->parameters[ID::A_WIDTH] = new_sig.size();
cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
new_sig = cell->getPort(ID::Y);
cell->setPort(TW::A, new_sig);
cell->setPort(TW::B, sig2);
cell->setPort(TW::Y, module->addWire(NEW_TWINE, new_sig.size() + sig2.size()));
new_sig = cell->getPort(TW::Y);
}
spliced_signals_cache[sig] = new_sig;

30
passes/cmds/splitcells.cc
View file

@ -70,16 +70,16 @@ struct SplitcellsWorker
{
if (cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor"))
{
SigSpec outsig = sigmap(cell->getPort(ID::Y));
SigSpec outsig = sigmap(cell->getPort(TW::Y));
if (GetSize(outsig) <= 1) return 0;
std::vector<int> slices;
slices.push_back(0);
int width = GetSize(outsig);
width = std::min(width, GetSize(cell->getPort(ID::A)));
width = std::min(width, GetSize(cell->getPort(TW::A)));
if (cell->hasPort(ID::B))
width = std::min(width, GetSize(cell->getPort(ID::B)));
width = std::min(width, GetSize(cell->getPort(TW::B)));
for (int i = 1; i < width; i++) {
auto &last_users = bit_users_db[outsig[slices.back()]];
@ -110,23 +110,23 @@ struct SplitcellsWorker
return new_sig;
};
slice->setPort(ID::A, slice_signal(slice->getPort(ID::A)));
slice->setPort(TW::A, slice_signal(slice->getPort(TW::A)));
if (slice->hasParam(ID::A_WIDTH))
slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(ID::A)));
slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(TW::A)));
if (slice->hasPort(ID::B)) {
slice->setPort(ID::B, slice_signal(slice->getPort(ID::B)));
slice->setPort(TW::B, slice_signal(slice->getPort(TW::B)));
if (slice->hasParam(ID::B_WIDTH))
slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(ID::B)));
slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(TW::B)));
}
slice->setPort(ID::Y, slice_signal(slice->getPort(ID::Y)));
slice->setPort(TW::Y, slice_signal(slice->getPort(TW::Y)));
if (slice->hasParam(ID::Y_WIDTH))
slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(ID::Y)));
slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(TW::Y)));
if (slice->hasParam(ID::WIDTH))
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Y)));
log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(ID::Y)));
log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(TW::Y)));
}
module->remove(cell);
@ -139,7 +139,7 @@ struct SplitcellsWorker
auto splitports = {ID::D, ID::Q, ID::AD, ID::SET, ID::CLR};
auto splitparams = {ID::ARST_VALUE, ID::SRST_VALUE};
SigSpec outsig = sigmap(cell->getPort(ID::Q));
SigSpec outsig = sigmap(cell->getPort(TW::Q));
if (GetSize(outsig) <= 1) return 0;
int width = GetSize(outsig);
@ -167,7 +167,7 @@ struct SplitcellsWorker
Cell *slice = module->addCell(slice_name, cell);
for (IdString portname : splitports) {
for (TwineRef portname : splitports) {
if (slice->hasPort(portname)) {
SigSpec sig = slice->getPort(portname);
sig = sig.extract(slice_lsb, slice_msb-slice_lsb+1);
@ -183,9 +183,9 @@ struct SplitcellsWorker
}
}
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Q)));
slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Q)));
log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(ID::Q)));
log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(TW::Q)));
}
module->remove(cell);

24
passes/cmds/stat.cc
View file

@ -190,22 +190,22 @@ struct statdata_t {
ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt),
ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul),
ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
} else if (cell_type.in(ID($mux)))
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Y)));
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)));
else if (cell_type.in(ID($bmux), ID($pmux)))
cell_type =
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S)));
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)));
else if (cell_type == ID($demux))
cell_type =
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S)));
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)));
else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
ID($dlatchsr)))
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Q)));
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)));
}
if (!cell_area.empty()) {
@ -215,10 +215,10 @@ struct statdata_t {
if (cell_data.single_parameter_area.size() > 0) {
// assume that we just take the max of the A,B,Y ports
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(ID::Q)) : 0;
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(TW::Q)) : 0;
int max_width = max<int>({width_a, width_b, width_y, width_q});
if (!cell_area.count(cell_type)) {
cell_area[cell_type] = cell_data;
@ -237,7 +237,7 @@ struct statdata_t {
vector<double> widths;
if (cell_data.parameter_names.size() > 0) {
for (auto &it : cell_data.parameter_names) {
RTLIL::IdString port_name;
TwineRef port_name;
if (it == "A") {
port_name = ID::A;
} else if (it == "B") {

18
passes/cmds/test_patch.cc
View file

@ -19,18 +19,18 @@ struct TestPatchPass : public Pass {
for (auto cell : module->selected_cells()) {
if (cell->type == ID($add)) {
Cell* add = cell;
log_assert(add->getPort(ID::B).is_wire());
log_assert(add->getPort(ID::B).known_driver());
auto neg = add->getPort(ID::B)[0].wire->driverCell();
log_assert(add->getPort(TW::B).is_wire());
log_assert(add->getPort(TW::B).known_driver());
auto neg = add->getPort(TW::B)[0].wire->driverCell();
log_assert(neg->type == ID($not));
RTLIL::Patch patcher(module, nullptr);
int width = cell->getPort(ID::A).size();
int width = cell->getPort(TW::A).size();
auto sub = patcher.addSub(NEW_ID,
neg->getPort(ID::A),
add->getPort(ID::A),
patcher.addWire(NEW_ID, width));
auto new_out_wire = patcher.addWire(NEW_ID, width);
auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(ID::Y), new_out_wire);
neg->getPort(TW::A),
add->getPort(TW::A),
patcher.addWire(NEW_TWINE, width));
auto new_out_wire = patcher.addWire(NEW_TWINE, width);
auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(TW::Y), new_out_wire);
log_cell(new_cell);
patcher.patch(add, ID::Y, new_out_wire);
}

2
passes/cmds/trace.cc
View file

@ -36,7 +36,7 @@ struct TraceMonitor : public RTLIL::Monitor
log("#TRACE# Module delete: %s\n", module);
}
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
}

180
passes/cmds/xprop.cc
View file

@ -202,9 +202,9 @@ struct XpropWorker
EncodedSig new_sigs;
if (new_bits > 0) {
new_sigs.is_0 = module->addWire(NEW_ID, new_bits);
new_sigs.is_1 = module->addWire(NEW_ID, new_bits);
new_sigs.is_x = module->addWire(NEW_ID, new_bits);
new_sigs.is_0 = module->addWire(NEW_TWINE, new_bits);
new_sigs.is_1 = module->addWire(NEW_TWINE, new_bits);
new_sigs.is_x = module->addWire(NEW_TWINE, new_bits);
}
int invert_pos = 0;
@ -319,8 +319,8 @@ struct XpropWorker
}
if (cell->type == ID($not)) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]))
mark_maybe_x(sig_y[i]);
@ -328,9 +328,9 @@ struct XpropWorker
}
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto sig_b = cell->getPort(ID::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto sig_b = cell->getPort(TW::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]))
mark_maybe_x(sig_y[i]);
@ -338,10 +338,10 @@ struct XpropWorker
}
if (cell->type.in(ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]) || maybe_x(sig_s[i]))
mark_maybe_x(sig_y[i]);
@ -349,10 +349,10 @@ struct XpropWorker
}
if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
if (maybe_x(sig_s)) {
mark_maybe_x(sig_y);
return;
@ -373,9 +373,9 @@ struct XpropWorker
}
if (cell->type.in(ID($demux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_s = cell->getPort(TW::S);
if (maybe_x(sig_s)) {
mark_maybe_x(sig_y);
return;
@ -388,15 +388,15 @@ struct XpropWorker
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) {
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_b = cell->getPort(TW::B);
auto &sig_y = cell->getPort(TW::Y);
if (maybe_x(sig_b)) {
mark_maybe_x(sig_y);
return;
}
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
if (maybe_x(sig_a)) {
// We could be more precise for shifts, but that's not required
@ -408,15 +408,15 @@ struct XpropWorker
}
if (cell->type.in(ID($shiftx))) {
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_b = cell->getPort(TW::B);
auto &sig_y = cell->getPort(TW::Y);
if (cell->getParam(ID::B_SIGNED).as_bool() || GetSize(sig_b) >= 30) {
mark_maybe_x(sig_y);
} else {
int max_shift = (1 << GetSize(sig_b)) - 1;
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
for (int i = 0; i < GetSize(sig_y); i++)
if (i + max_shift >= GetSize(sig_a))
@ -428,7 +428,7 @@ struct XpropWorker
return;
}
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
if (maybe_x(sig_a)) {
// We could be more precise for shifts, but that's not required
// for correctness, so let's keep it simple
@ -457,7 +457,7 @@ struct XpropWorker
ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_y = cell->getPort(TW::Y);
if (inputs_maybe_x(cell))
mark_maybe_x(sig_y[0]);
return;
@ -482,9 +482,9 @@ struct XpropWorker
if (!ports_maybe_x(cell)) {
if (cell->type == ID($bweq)) {
auto sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
RTLIL::IdString name(cell->name);
module->remove(cell);
@ -493,9 +493,9 @@ struct XpropWorker
}
if (cell->type.in(ID($nex), ID($eqx))) {
auto sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
RTLIL::IdString name(cell->name);
auto type = cell->type;
@ -511,8 +511,8 @@ struct XpropWorker
}
if (cell->type.in(ID($not), ID($_NOT_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type == ID($not))
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
@ -528,9 +528,9 @@ struct XpropWorker
}
if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -555,8 +555,8 @@ struct XpropWorker
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto enc_a = encoded(sig_a);
auto enc_y = encoded(sig_y, true);
@ -577,8 +577,8 @@ struct XpropWorker
}
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto enc_a = encoded(sig_a);
auto enc_y = encoded(sig_y, true);
@ -597,9 +597,9 @@ struct XpropWorker
}
if (cell->type.in(ID($logic_and), ID($logic_or))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -623,9 +623,9 @@ struct XpropWorker
}
if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -646,9 +646,9 @@ struct XpropWorker
}
if (cell->type.in(ID($eq), ID($ne))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -672,9 +672,9 @@ struct XpropWorker
}
if (cell->type.in(ID($eqx), ID($nex))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -697,9 +697,9 @@ struct XpropWorker
}
if (cell->type.in(ID($bweqx))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -712,10 +712,10 @@ struct XpropWorker
}
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -737,10 +737,10 @@ struct XpropWorker
}
if (cell->type.in(ID($pmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -772,9 +772,9 @@ struct XpropWorker
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -783,9 +783,9 @@ struct XpropWorker
auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0];
auto not_all_x = module->Not(NEW_ID, all_x)[0];
SigSpec y_not_0 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_not_0 = module->addWire(NEW_TWINE, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_TWINE, GetSize(sig_y));
auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
@ -793,23 +793,23 @@ struct XpropWorker
std::swap(enc_a.is_0, enc_a.is_x);
}
auto shift_0 = module->addCell(NEW_ID, encoded_type);
auto shift_0 = module->addCell(NEW_TWINE, encoded_type);
shift_0->parameters = cell->parameters;
shift_0->setPort(ID::A, module->Not(NEW_ID, enc_a.is_0));
shift_0->setPort(ID::B, enc_b.is_1);
shift_0->setPort(ID::Y, y_not_0);
shift_0->setPort(TW::A, module->Not(NEW_ID, enc_a.is_0));
shift_0->setPort(TW::B, enc_b.is_1);
shift_0->setPort(TW::Y, y_not_0);
auto shift_1 = module->addCell(NEW_ID, encoded_type);
auto shift_1 = module->addCell(NEW_TWINE, encoded_type);
shift_1->parameters = cell->parameters;
shift_1->setPort(ID::A, enc_a.is_1);
shift_1->setPort(ID::B, enc_b.is_1);
shift_1->setPort(ID::Y, y_1);
shift_1->setPort(TW::A, enc_a.is_1);
shift_1->setPort(TW::B, enc_b.is_1);
shift_1->setPort(TW::Y, y_1);
auto shift_x = module->addCell(NEW_ID, encoded_type);
auto shift_x = module->addCell(NEW_TWINE, encoded_type);
shift_x->parameters = cell->parameters;
shift_x->setPort(ID::A, enc_a.is_x);
shift_x->setPort(ID::B, enc_b.is_1);
shift_x->setPort(ID::Y, y_x);
shift_x->setPort(TW::A, enc_a.is_x);
shift_x->setPort(TW::B, enc_b.is_1);
shift_x->setPort(TW::Y, y_x);
SigSpec y_0 = module->Not(NEW_ID, y_not_0);
@ -825,8 +825,8 @@ struct XpropWorker
}
if (cell->type.in(ID($ff))) {
auto &sig_d = cell->getPort(ID::D);
auto &sig_q = cell->getPort(ID::Q);
auto &sig_d = cell->getPort(TW::D);
auto &sig_q = cell->getPort(TW::Q);
auto init_q = initvals(sig_q);
auto init_q_is_1 = init_q;
@ -842,7 +842,7 @@ struct XpropWorker
auto enc_d = encoded(sig_d);
auto enc_q = encoded(sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(sig_q));
auto data_q = module->addWire(NEW_TWINE, GetSize(sig_q));
module->addFf(NEW_ID, enc_d.is_1, data_q);
module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x);
@ -885,7 +885,7 @@ struct XpropWorker
auto enc_d = encoded(ff.sig_d);
auto enc_q = encoded(ff.sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(ff.sig_q));
auto data_q = module->addWire(NEW_TWINE, GetSize(ff.sig_q));
ff.sig_d = enc_d.is_1;
ff.sig_q = data_q;
@ -928,11 +928,11 @@ struct XpropWorker
}
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
auto sig_b = cell->getPort(ID::B);
auto sig_b = cell->getPort(TW::B);
auto invalid = module->LogicNot(NEW_ID, sig_b);
inbits_x.append(invalid);
sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid);
cell->setPort(ID::B, sig_b);
cell->setPort(TW::B, sig_b);
}
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x));
@ -945,7 +945,7 @@ struct XpropWorker
if (bool_out)
enc_port.connect_as_bool();
SigSpec new_output = module->addWire(NEW_ID, GetSize(conn.second));
SigSpec new_output = module->addWire(NEW_TWINE, GetSize(conn.second));
enc_port.connect_1_under_x(bool_out ? new_output.extract(0) : new_output);
enc_port.connect_x(SigSpec(outbits_x, GetSize(enc_port)));