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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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8
passes/cmds/abstract.cc
View file

@ -102,7 +102,7 @@ void emit_mux_anyseq(Module* mod, const SigSpec& mux_input, const SigSpec& mux_o
}
bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, EnableLogic enable) {
Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size());
Wire* abstracted = ff.module->addWire(NEW_TWINE, offsets.size());
SigSpec mux_input;
int abstracted_idx = 0;
for (int d_idx = 0; d_idx < ff.width; d_idx++) {
@ -213,7 +213,7 @@ unsigned int abstract_state(Module* mod, EnableLogic enable, const std::vector<S
}
bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, IdString port_name, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, offsets.size());
Wire* to_abstract = mod->addWire(NEW_TWINE, offsets.size());
SigSpec mux_input;
SigSpec mux_output;
const SigSpec& old_port = cell->getPort(port_name);
@ -235,7 +235,7 @@ bool abstract_value_cell_port(Module* mod, Cell* cell, std::set<int> offsets, Id
}
bool abstract_value_mod_port(Module* mod, Wire* wire, std::set<int> offsets, EnableLogic enable) {
Wire* to_abstract = mod->addWire(NEW_ID, wire);
Wire* to_abstract = mod->addWire(NEW_TWINE, wire);
to_abstract->port_input = true;
to_abstract->port_id = wire->port_id;
wire->port_input = false;
@ -507,7 +507,7 @@ struct AbstractPass : public Pass {
case Enable::Initstates: {
SigBit in_init_states = mod->Initstate(NEW_ID);
for (int i = 1; i < initstates; i++) {
Wire *in_init_states_q = mod->addWire(NEW_ID);
Wire *in_init_states_q = mod->addWire(NEW_TWINE);
mod->addFf(NEW_ID, in_init_states, in_init_states_q);
in_init_states_q->attributes[ID::init] = State::S1;
in_init_states = in_init_states_q;

8
passes/cmds/add.cc
View file

@ -41,10 +41,10 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
log_error("Could not find wire with name \"%s\".\n", name);
}
else {
RTLIL::Cell *formal_cell = module->addCell(NEW_ID, "$" + celltype);
formal_cell->setPort(ID::A, wire);
RTLIL::Cell *formal_cell = module->addCell(NEW_TWINE, "$" + celltype);
formal_cell->setPort(TW::A, wire);
if(enable_name == "") {
formal_cell->setPort(ID::EN, State::S1);
formal_cell->setPort(TW::EN, State::S1);
log("Added $%s cell for wire \"%s.%s\"\n", celltype, module->name.str(), name);
}
else {
@ -52,7 +52,7 @@ static void add_formal(RTLIL::Module *module, const std::string &celltype, const
if(enable_wire == nullptr)
log_error("Could not find enable wire with name \"%s\".\n", enable_name);
formal_cell->setPort(ID::EN, enable_wire);
formal_cell->setPort(TW::EN, enable_wire);
log("Added $%s cell for wire \"%s.%s\" enabled by wire \"%s.%s\".\n", celltype, module->name.str(), name, module->name.str(), enable_name);
}
}

2
passes/cmds/bugpoint.cc
View file

@ -306,7 +306,7 @@ struct BugpointPass : public Pass {
if (!stage2 && (cell->input(it.first) || cell->output(it.first)) && index++ == seed)
{
log_header(design, "Trying to expose cell port %s.%s.%s as module port.\n", mod, cell, it.first.unescape());
RTLIL::Wire *wire = mod->addWire(NEW_ID, port.size());
RTLIL::Wire *wire = mod->addWire(NEW_TWINE, port.size());
wire->set_bool_attribute(ID($bugpoint));
wire->port_input = cell->input(it.first);
wire->port_output = cell->output(it.first);

10
passes/cmds/check.cc
View file

@ -304,8 +304,8 @@ struct CheckPass : public Pass {
if (cell->type.in(ID($pmux), ID($bmux))) {
// We're skipping inputs A and B, since each of their bits contributes only one edge
in_widths = GetSize(cell->getPort(ID::S));
out_widths = GetSize(cell->getPort(ID::Y));
in_widths = GetSize(cell->getPort(TW::S));
out_widths = GetSize(cell->getPort(TW::Y));
} else {
for (auto &conn : cell->connections()) {
if (cell->input(conn.first))
@ -370,8 +370,8 @@ struct CheckPass : public Pass {
if (cell->type == ID($connect)) {
// Inefficient, but rare case in sane design
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
for (int i = 0; i < sig_a.size(); i++) {
int count_a = wire_drivers_count[sig_a[i]];
int count_b = wire_drivers_count[sig_b[i]];
@ -561,7 +561,7 @@ struct CheckPass : public Pass {
if (cell->is_builtin_ff() == 0)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
init_bits.erase(bit);
}

60
passes/cmds/chformal.cc
View file

@ -275,15 +275,15 @@ struct ChformalPass : public Pass {
for (auto cell : module->selected_cells())
{
if (cell->type == ID($ff)) {
SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort(ID::Q));
SigSpec D = sigmap(cell->getPort(TW::D));
SigSpec Q = sigmap(cell->getPort(TW::Q));
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(State::Sm, false));
}
if (cell->type == ID($dff)) {
SigSpec D = sigmap(cell->getPort(ID::D));
SigSpec Q = sigmap(cell->getPort(ID::Q));
SigSpec C = sigmap(cell->getPort(ID::CLK));
SigSpec D = sigmap(cell->getPort(TW::D));
SigSpec Q = sigmap(cell->getPort(TW::Q));
SigSpec C = sigmap(cell->getPort(TW::CLK));
bool clockpol = cell->getParam(ID::CLK_POLARITY).as_bool();
for (int i = 0; i < GetSize(D); i++)
ffmap[Q[i]] = make_pair(D[i], make_pair(C, clockpol));
@ -295,7 +295,7 @@ struct ChformalPass : public Pass {
if (is_triggered_check_cell(cell)) {
if (cell->getParam(ID::TRG_WIDTH).as_int() != 1)
continue;
cell->setPort(ID::TRG, SigSpec());
cell->setPort(TW::TRG, SigSpec());
cell->setParam(ID::TRG_ENABLE, false);
cell->setParam(ID::TRG_WIDTH, 0);
cell->setParam(ID::TRG_POLARITY, false);
@ -305,8 +305,8 @@ struct ChformalPass : public Pass {
while (true)
{
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec EN = sigmap(cell->getPort(ID::EN));
SigSpec A = sigmap(cell->getPort(TW::A));
SigSpec EN = sigmap(cell->getPort(TW::EN));
if (ffmap.count(A) == 0 || ffmap.count(EN) == 0)
break;
@ -322,8 +322,8 @@ struct ChformalPass : public Pass {
if (A_map.second != EN_map.second)
break;
cell->setPort(ID::A, A_map.first);
cell->setPort(ID::EN, EN_map.first);
cell->setPort(TW::A, A_map.first);
cell->setPort(TW::EN, EN_map.first);
}
}
}
@ -337,18 +337,18 @@ struct ChformalPass : public Pass {
for (int i = 0; i < mode_arg; i++)
{
SigSpec orig_a = cell->getPort(ID::A);
SigSpec orig_en = cell->getPort(ID::EN);
SigSpec orig_a = cell->getPort(TW::A);
SigSpec orig_en = cell->getPort(TW::EN);
Wire *new_a = module->addWire(NEW_ID);
Wire *new_en = module->addWire(NEW_ID);
Wire *new_a = module->addWire(NEW_TWINE);
Wire *new_en = module->addWire(NEW_TWINE);
new_en->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, orig_a, new_a);
module->addFf(NEW_ID, orig_en, new_en);
cell->setPort(ID::A, new_a);
cell->setPort(ID::EN, new_en);
cell->setPort(TW::A, new_a);
cell->setPort(TW::EN, new_en);
}
}
}
@ -358,14 +358,14 @@ struct ChformalPass : public Pass {
SigSpec en = State::S1;
for (int i = 0; i < mode_arg; i++) {
Wire *w = module->addWire(NEW_ID);
Wire *w = module->addWire(NEW_TWINE);
w->attributes[ID::init] = State::S0;
module->addFf(NEW_ID, en, w);
en = w;
}
for (auto cell : constr_cells)
cell->setPort(ID::EN, module->LogicAnd(NEW_ID, en, cell->getPort(ID::EN)));
cell->setPort(TW::EN, module->LogicAnd(NEW_ID, en, cell->getPort(TW::EN)));
}
else
if (mode =='p')
@ -373,7 +373,7 @@ struct ChformalPass : public Pass {
for (auto cell : constr_cells)
{
if (cell->type == ID($check)) {
Cell *cover = module->addCell(NEW_ID_SUFFIX("coverenable"), ID($check));
Cell *cover = module->addCell(NEW_TWINE_SUFFIX("coverenable"), ID($check));
cover->attributes = cell->attributes;
if (cell->src_id() != Twine::Null && module->design)
cover->set_src_id(cell->src_id());
@ -383,11 +383,11 @@ struct ChformalPass : public Pass {
for (auto const &conn : cell->connections())
if (!conn.first.in(ID::A, ID::EN))
cover->setPort(conn.first, conn.second);
cover->setPort(ID::A, cell->getPort(ID::EN));
cover->setPort(ID::EN, State::S1);
cover->setPort(TW::A, cell->getPort(TW::EN));
cover->setPort(TW::EN, State::S1);
} else {
module->addCover(NEW_ID_SUFFIX("coverenable"),
cell->getPort(ID::EN), State::S1, cell->get_src_attribute());
cell->getPort(TW::EN), State::S1, cell->get_src_attribute());
}
}
}
@ -419,17 +419,17 @@ struct ChformalPass : public Pass {
log_error("Cannot lower edge triggered $check cell %s, run async2sync or clk2fflogic first.\n", cell);
Cell *plain_cell = module->addCell(NEW_ID, formal_flavor(cell));
Cell *plain_cell = module->addCell(NEW_TWINE, formal_flavor(cell));
plain_cell->attributes = cell->attributes;
if (cell->src_id() != Twine::Null && module->design)
plain_cell->set_src_id(cell->src_id());
SigBit sig_a = cell->getPort(ID::A);
SigBit sig_en = cell->getPort(ID::EN);
SigBit sig_a = cell->getPort(TW::A);
SigBit sig_en = cell->getPort(TW::EN);
plain_cell->setPort(ID::A, sig_a);
plain_cell->setPort(ID::EN, sig_en);
plain_cell->setPort(TW::A, sig_a);
plain_cell->setPort(TW::EN, sig_en);
if (plain_cell->type.in(ID($assert), ID($assume)))
sig_a = module->Not(NEW_ID, sig_a);
@ -438,12 +438,12 @@ struct ChformalPass : public Pass {
module->swap_names(cell, plain_cell);
if (cell->getPort(ID::ARGS).empty()) {
if (cell->getPort(TW::ARGS).empty()) {
module->remove(cell);
} else {
cell->type = ID($print);
cell->setPort(ID::EN, combined_en);
cell->unsetPort(ID::A);
cell->setPort(TW::EN, combined_en);
cell->unsetPort(TW::A);
cell->unsetParam(ID(FLAVOR));
}
}

16
passes/cmds/clean_zerowidth.cc
View file

@ -77,7 +77,7 @@ struct CleanZeroWidthPass : public Pass {
// Coarse FF cells: remove if WIDTH == 0 (no outputs).
// This will also trigger on fine cells, so use the Q port
// width instead of actual WIDTH parameter.
if (GetSize(cell->getPort(ID::Q)) == 0) {
if (GetSize(cell->getPort(TW::Q)) == 0) {
module->remove(cell);
}
} else if (cell->type.in(ID($pmux), ID($bmux), ID($demux))) {
@ -87,17 +87,17 @@ struct CleanZeroWidthPass : public Pass {
module->remove(cell);
}
if (cell->getParam(ID::S_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
module->remove(cell);
}
} else if (cell->type == ID($concat)) {
// If a concat has a zero-width input: replace with direct
// connection to the other input.
if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::B));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::B));
module->remove(cell);
} else if (cell->getParam(ID::B_WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
module->remove(cell);
}
} else if (cell->type == ID($fsm)) {
@ -107,7 +107,7 @@ struct CleanZeroWidthPass : public Pass {
} else if (cell->type == ID($lut)) {
// Zero-width LUT is just a const driver.
if (cell->getParam(ID::WIDTH).as_int() == 0) {
module->connect(cell->getPort(ID::Y), cell->getParam(ID::LUT)[0]);
module->connect(cell->getPort(TW::Y), cell->getParam(ID::LUT)[0]);
module->remove(cell);
}
} else if (cell->type == ID($sop)) {
@ -115,7 +115,7 @@ struct CleanZeroWidthPass : public Pass {
if (cell->getParam(ID::WIDTH).as_int() == 0) {
// The value is 1 iff DEPTH is non-0.
bool val = cell->getParam(ID::DEPTH).as_int() != 0;
module->connect(cell->getPort(ID::Y), val);
module->connect(cell->getPort(TW::Y), val);
module->remove(cell);
}
} else if (cell->hasParam(ID::WIDTH)) {
@ -132,11 +132,11 @@ struct CleanZeroWidthPass : public Pass {
// TODO: fixing zero-width A and B not supported.
} else {
if (cell->getParam(ID::A_WIDTH).as_int() == 0) {
cell->setPort(ID::A, State::S0);
cell->setPort(TW::A, State::S0);
cell->setParam(ID::A_WIDTH, 1);
}
if (cell->hasParam(ID::B_WIDTH) && cell->getParam(ID::B_WIDTH).as_int() == 0) {
cell->setPort(ID::B, State::S0);
cell->setPort(TW::B, State::S0);
cell->setParam(ID::B_WIDTH, 1);
}
}

2
passes/cmds/connect.cc
View file

@ -30,7 +30,7 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
{
CellTypes ct(design);
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
RTLIL::Wire *dummy_wire = module->addWire(NEW_TWINE, sig.size());
// (void)module->connections(); // trigger signorm flush

94
passes/cmds/dft_tag.cc
View file

@ -98,10 +98,10 @@ struct DftTagWorker {
}
for (auto cell : overwrite_cells) {
log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(ID::A)));
SigSpec orig_signal = cell->getPort(ID::A);
log_debug("Applying $overwrite_tag %s for signal %s\n", cell->name.unescape(), log_signal(cell->getPort(TW::A)));
SigSpec orig_signal = cell->getPort(TW::A);
SigSpec interposed_signal = divert_users(orig_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(ID::SET), cell->getPort(ID::CLR), interposed_signal);
auto *set_tag_cell = module->addSetTag(NEW_ID, cell->getParam(ID::TAG).decode_string(), orig_signal, cell->getPort(TW::SET), cell->getPort(TW::CLR), interposed_signal);
modwalker.add_cell(set_tag_cell); // Make sure the next $overwrite_tag sees the new connections
design_changed = true;
}
@ -123,7 +123,7 @@ struct DftTagWorker {
signal_mapped.sort_and_unify();
if (GetSize(signal_mapped) < GetSize(signal))
log_warning("Detected $overwrite_tag on signal %s which contains repeated bits, this can result in unexpected behavior.\n", log_signal(signal));
SigSpec new_wire = module->addWire(NEW_ID, GetSize(signal));
SigSpec new_wire = module->addWire(NEW_TWINE, GetSize(signal));
for (int i = 0; i < GetSize(new_wire); ++i)
divert_users(signal[i], new_wire[i]);
return new_wire;
@ -359,7 +359,7 @@ struct DftTagWorker {
// when the outer call for this tag/cell returns
for (auto &conn : cell->connections())
if (cell->output(conn.first))
emit_tag_signal(tag, conn.second, module->addWire(NEW_ID, GetSize(conn.second)));
emit_tag_signal(tag, conn.second, module->addWire(NEW_TWINE, GetSize(conn.second)));
return;
}
@ -380,8 +380,8 @@ struct DftTagWorker {
group_of_tag[tag] = tag_group;
}
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
// TODO handle constant set/clr masks
add_tags(sig_y, singleton(tag));
forward_tags(sig_y, sig_a);
@ -393,8 +393,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($not), ID($pos))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type.in(ID($not), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
}
@ -403,9 +403,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($bweqx))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -416,10 +416,10 @@ struct DftTagWorker {
}
if (cell->type.in(ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -445,7 +445,7 @@ struct DftTagWorker {
ID($reduce_bool), ID($logic_not), ID($logic_or), ID($logic_and),
ID($eq), ID($ne)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_y = cell->getPort(TW::Y);
add_tags(sig_y[0], tags(cell));
return;
@ -480,12 +480,12 @@ struct DftTagWorker {
if (cell->type == ID($set_tag)) {
IdString cell_tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
auto tag_sig_a = tag_signal(tag, cell->getPort(ID::A));
auto &sig_y = cell->getPort(ID::Y);
auto tag_sig_a = tag_signal(tag, cell->getPort(TW::A));
auto &sig_y = cell->getPort(TW::Y);
if (cell_tag == tag) {
auto &sig_set = cell->getPort(ID::SET);
auto &sig_clr = cell->getPort(ID::CLR);
auto &sig_set = cell->getPort(TW::SET);
auto &sig_clr = cell->getPort(TW::CLR);
tag_sig_a = autoAnd(NEW_ID, tag_sig_a, autoNot(NEW_ID, sig_clr));
tag_sig_a = autoOr(NEW_ID, tag_sig_a, sig_set);
}
@ -499,8 +499,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($not), ID($pos), ID($_NOT_), ID($_BUF_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type.in(ID($not), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
}
@ -512,9 +512,9 @@ struct DftTagWorker {
ID($and), ID($or),
ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -555,9 +555,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($xor), ID($xnor), ID($bweqx), ID($_XOR_), ID($_XNOR_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -573,10 +573,10 @@ struct DftTagWorker {
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -607,9 +607,9 @@ struct DftTagWorker {
}
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -636,9 +636,9 @@ struct DftTagWorker {
if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -667,8 +667,8 @@ struct DftTagWorker {
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto group_sig_a = tag_group_signal(tag, sig_a);
auto tag_sig_a = tag_signal(tag, sig_a);
@ -701,7 +701,7 @@ struct DftTagWorker {
ff.name = NEW_ID;
ff.cell = nullptr;
ff.sig_d = tag_signal(tag, ff.sig_d);
ff.sig_q = module->addWire(NEW_ID, width);
ff.sig_q = module->addWire(NEW_TWINE, width);
ff.is_anyinit = false;
ff.val_init = Const(0, width);
ff.emit();
@ -751,7 +751,7 @@ struct DftTagWorker {
get_tag_cells.push_back(cell);
for (auto cell : get_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
tag_signal(tag, sig_a);
@ -808,15 +808,15 @@ struct DftTagWorker {
}
for (auto cell : set_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_y = cell->getPort(TW::Y);
module->connect(sig_y, sig_a);
module->remove(cell);
}
for (auto cell : get_tag_cells) {
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_y = cell->getPort(TW::Y);
IdString tag = stringf("\\%s", cell->getParam(ID::TAG).decode_string());
auto tag_sig = tag_signal(tag, sig_a);

2
passes/cmds/future.cc
View file

@ -53,7 +53,7 @@ struct FutureWorker {
if (cell->type != ID($future_ff))
continue;
module->connect(cell->getPort(ID::Y), future_ff(cell->getPort(ID::A)));
module->connect(cell->getPort(TW::Y), future_ff(cell->getPort(TW::A)));
replaced_cells.push_back(cell);
}

8
passes/cmds/glift.cc
View file

@ -189,7 +189,7 @@ private:
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) {
const unsigned int A = 0, B = 1, Y = 2;
const unsigned int NUM_PORTS = 3;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1)
@ -254,7 +254,7 @@ private:
else if (cell->type.in(ID($_XOR_), ID($_XNOR_))) {
const unsigned int A = 0, B = 1, Y = 2;
const unsigned int NUM_PORTS = 3;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[Y].size() != 1)
@ -310,7 +310,7 @@ private:
else if (cell->type.in(ID($_MUX_), ID($_NMUX_))) {
const unsigned int A = 0, B = 1, S = 2, Y = 3;
const unsigned int NUM_PORTS = 4;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::B), cell->getPort(ID::S), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::B), cell->getPort(TW::S), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[B].size() != 1 || ports[S].size() != 1 || ports[Y].size() != 1)
@ -323,7 +323,7 @@ private:
else if (cell->type.in(ID($_NOT_))) {
const unsigned int A = 0, Y = 1;
const unsigned int NUM_PORTS = 2;
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(ID::A), cell->getPort(ID::Y)};
RTLIL::SigSpec ports[NUM_PORTS] = {cell->getPort(TW::A), cell->getPort(TW::Y)};
RTLIL::SigSpec port_taints[NUM_PORTS];
if (ports[A].size() != 1 || ports[Y].size() != 1)

10
passes/cmds/portarcs.cc
View file

@ -32,7 +32,7 @@ static RTLIL::SigBit canonical_bit(RTLIL::SigBit bit)
RTLIL::Wire *w;
while ((w = bit.wire) != NULL && !w->port_input &&
w->driverCell()->type.in(ID($buf), ID($_BUF_))) {
bit = w->driverCell()->getPort(ID::A)[bit.offset];
bit = w->driverCell()->getPort(TW::A)[bit.offset];
}
return bit;
}
@ -292,7 +292,7 @@ struct PortarcsPass : Pass {
int *p = annotations.at(canonical_bit(bit));
for (auto i = 0; i < inputs.size(); i++) {
if (p[i] >= 0) {
Cell *spec = m->addCell(NEW_ID, ID($specify2));
Cell *spec = m->addCell(NEW_TWINE, ID($specify2));
spec->setParam(ID::SRC_WIDTH, 1);
spec->setParam(ID::DST_WIDTH, 1);
spec->setParam(ID::T_FALL_MAX, p[i]);
@ -304,9 +304,9 @@ struct PortarcsPass : Pass {
spec->setParam(ID::SRC_DST_POL, false);
spec->setParam(ID::SRC_DST_PEN, false);
spec->setParam(ID::FULL, false);
spec->setPort(ID::EN, Const(1, 1));
spec->setPort(ID::SRC, inputs[i]);
spec->setPort(ID::DST, bit);
spec->setPort(TW::EN, Const(1, 1));
spec->setPort(TW::SRC, inputs[i]);
spec->setPort(TW::DST, bit);
}
}
}

2
passes/cmds/scatter.cc
View file

@ -51,7 +51,7 @@ struct ScatterPass : public Pass {
for (auto cell : module->cells()) {
dict<RTLIL::IdString, RTLIL::SigSig> new_connections;
for (auto conn : cell->connections())
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_ID, GetSize(conn.second))));
new_connections.emplace(conn.first, RTLIL::SigSig(conn.second, module->addWire(NEW_TWINE, GetSize(conn.second))));
for (auto &it : new_connections) {
if (ct.cell_output(cell->type, it.first))
module->connect(RTLIL::SigSig(it.second.first, it.second.second));

4
passes/cmds/scc.cc
View file

@ -152,14 +152,14 @@ struct SccWorker
if (subcell->type != ID($specify2))
continue;
for (auto bit : subcell->getPort(ID::SRC))
for (auto bit : subcell->getPort(TW::SRC))
{
if (!bit.wire || !cell->hasPort(bit.wire->name))
continue;
inputSignals.append(sigmap(cell->getPort(bit.wire->name)));
}
for (auto bit : subcell->getPort(ID::DST))
for (auto bit : subcell->getPort(TW::DST))
{
if (!bit.wire || !cell->hasPort(bit.wire->name))
continue;

4
passes/cmds/setundef.cc
View file

@ -371,13 +371,13 @@ struct SetundefPass : public Pass {
bool cell_selected = design->selected(module, cell);
bool wire_selected = false;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
if (bit.wire && design->selected(module, bit.wire))
wire_selected = true;
if (!cell_selected && !wire_selected)
continue;
for (auto bit : sigmap(cell->getPort(ID::Q)))
for (auto bit : sigmap(cell->getPort(TW::Q)))
ffbits.insert(bit);
}

18
passes/cmds/splice.cc
View file

@ -75,13 +75,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = sig;
if (sig_a.size() != sig.size()) {
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($slice));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($slice));
cell->parameters[ID::OFFSET] = offset;
cell->parameters[ID::A_WIDTH] = sig_a.size();
cell->parameters[ID::Y_WIDTH] = sig.size();
cell->setPort(ID::A, sig_a);
cell->setPort(ID::Y, module->addWire(NEW_ID, sig.size()));
new_sig = cell->getPort(ID::Y);
cell->setPort(TW::A, sig_a);
cell->setPort(TW::Y, module->addWire(NEW_TWINE, sig.size()));
new_sig = cell->getPort(TW::Y);
}
sliced_signals_cache[sig] = new_sig;
@ -132,13 +132,13 @@ struct SpliceWorker
RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
for (size_t i = 1; i < chunks.size(); i++) {
RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($concat));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($concat));
cell->parameters[ID::A_WIDTH] = new_sig.size();
cell->parameters[ID::B_WIDTH] = sig2.size();
cell->setPort(ID::A, new_sig);
cell->setPort(ID::B, sig2);
cell->setPort(ID::Y, module->addWire(NEW_ID, new_sig.size() + sig2.size()));
new_sig = cell->getPort(ID::Y);
cell->setPort(TW::A, new_sig);
cell->setPort(TW::B, sig2);
cell->setPort(TW::Y, module->addWire(NEW_TWINE, new_sig.size() + sig2.size()));
new_sig = cell->getPort(TW::Y);
}
spliced_signals_cache[sig] = new_sig;

30
passes/cmds/splitcells.cc
View file

@ -70,16 +70,16 @@ struct SplitcellsWorker
{
if (cell->type.in("$and", "$mux", "$not", "$or", "$pmux", "$xnor", "$xor"))
{
SigSpec outsig = sigmap(cell->getPort(ID::Y));
SigSpec outsig = sigmap(cell->getPort(TW::Y));
if (GetSize(outsig) <= 1) return 0;
std::vector<int> slices;
slices.push_back(0);
int width = GetSize(outsig);
width = std::min(width, GetSize(cell->getPort(ID::A)));
width = std::min(width, GetSize(cell->getPort(TW::A)));
if (cell->hasPort(ID::B))
width = std::min(width, GetSize(cell->getPort(ID::B)));
width = std::min(width, GetSize(cell->getPort(TW::B)));
for (int i = 1; i < width; i++) {
auto &last_users = bit_users_db[outsig[slices.back()]];
@ -110,23 +110,23 @@ struct SplitcellsWorker
return new_sig;
};
slice->setPort(ID::A, slice_signal(slice->getPort(ID::A)));
slice->setPort(TW::A, slice_signal(slice->getPort(TW::A)));
if (slice->hasParam(ID::A_WIDTH))
slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(ID::A)));
slice->setParam(ID::A_WIDTH, GetSize(slice->getPort(TW::A)));
if (slice->hasPort(ID::B)) {
slice->setPort(ID::B, slice_signal(slice->getPort(ID::B)));
slice->setPort(TW::B, slice_signal(slice->getPort(TW::B)));
if (slice->hasParam(ID::B_WIDTH))
slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(ID::B)));
slice->setParam(ID::B_WIDTH, GetSize(slice->getPort(TW::B)));
}
slice->setPort(ID::Y, slice_signal(slice->getPort(ID::Y)));
slice->setPort(TW::Y, slice_signal(slice->getPort(TW::Y)));
if (slice->hasParam(ID::Y_WIDTH))
slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(ID::Y)));
slice->setParam(ID::Y_WIDTH, GetSize(slice->getPort(TW::Y)));
if (slice->hasParam(ID::WIDTH))
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Y)));
slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Y)));
log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(ID::Y)));
log(" slice %d: %s => %s\n", i, slice_name, log_signal(slice->getPort(TW::Y)));
}
module->remove(cell);
@ -139,7 +139,7 @@ struct SplitcellsWorker
auto splitports = {ID::D, ID::Q, ID::AD, ID::SET, ID::CLR};
auto splitparams = {ID::ARST_VALUE, ID::SRST_VALUE};
SigSpec outsig = sigmap(cell->getPort(ID::Q));
SigSpec outsig = sigmap(cell->getPort(TW::Q));
if (GetSize(outsig) <= 1) return 0;
int width = GetSize(outsig);
@ -167,7 +167,7 @@ struct SplitcellsWorker
Cell *slice = module->addCell(slice_name, cell);
for (IdString portname : splitports) {
for (TwineRef portname : splitports) {
if (slice->hasPort(portname)) {
SigSpec sig = slice->getPort(portname);
sig = sig.extract(slice_lsb, slice_msb-slice_lsb+1);
@ -183,9 +183,9 @@ struct SplitcellsWorker
}
}
slice->setParam(ID::WIDTH, GetSize(slice->getPort(ID::Q)));
slice->setParam(ID::WIDTH, GetSize(slice->getPort(TW::Q)));
log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(ID::Q)));
log(" slice %d: %s => %s\n", i, slice_name.unescape(), log_signal(slice->getPort(TW::Q)));
}
module->remove(cell);

24
passes/cmds/stat.cc
View file

@ -190,22 +190,22 @@ struct statdata_t {
ID($xor), ID($xnor), ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx), ID($lt),
ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt), ID($add), ID($sub), ID($mul),
ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow), ID($alu))) {
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
cell_type = stringf("%s_%d", cell_type, max<int>({width_a, width_b, width_y}));
} else if (cell_type.in(ID($mux)))
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Y)));
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Y)));
else if (cell_type.in(ID($bmux), ID($pmux)))
cell_type =
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::Y)), GetSize(cell->getPort(ID::S)));
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::Y)), GetSize(cell->getPort(TW::S)));
else if (cell_type == ID($demux))
cell_type =
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::S)));
stringf("%s_%d_%d", cell_type, GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::S)));
else if (cell_type.in(ID($sr), ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($dffsre), ID($adff), ID($adffe),
ID($sdff), ID($sdffe), ID($sdffce), ID($aldff), ID($aldffe), ID($dlatch), ID($adlatch),
ID($dlatchsr)))
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(ID::Q)));
cell_type = stringf("%s_%d", cell_type, GetSize(cell->getPort(TW::Q)));
}
if (!cell_area.empty()) {
@ -215,10 +215,10 @@ struct statdata_t {
if (cell_data.single_parameter_area.size() > 0) {
// assume that we just take the max of the A,B,Y ports
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(ID::Y)) : 0;
int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(ID::Q)) : 0;
int width_a = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : 0;
int width_b = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : 0;
int width_y = cell->hasPort(ID::Y) ? GetSize(cell->getPort(TW::Y)) : 0;
int width_q = cell->hasPort(ID::Q) ? GetSize(cell->getPort(TW::Q)) : 0;
int max_width = max<int>({width_a, width_b, width_y, width_q});
if (!cell_area.count(cell_type)) {
cell_area[cell_type] = cell_data;
@ -237,7 +237,7 @@ struct statdata_t {
vector<double> widths;
if (cell_data.parameter_names.size() > 0) {
for (auto &it : cell_data.parameter_names) {
RTLIL::IdString port_name;
TwineRef port_name;
if (it == "A") {
port_name = ID::A;
} else if (it == "B") {

18
passes/cmds/test_patch.cc
View file

@ -19,18 +19,18 @@ struct TestPatchPass : public Pass {
for (auto cell : module->selected_cells()) {
if (cell->type == ID($add)) {
Cell* add = cell;
log_assert(add->getPort(ID::B).is_wire());
log_assert(add->getPort(ID::B).known_driver());
auto neg = add->getPort(ID::B)[0].wire->driverCell();
log_assert(add->getPort(TW::B).is_wire());
log_assert(add->getPort(TW::B).known_driver());
auto neg = add->getPort(TW::B)[0].wire->driverCell();
log_assert(neg->type == ID($not));
RTLIL::Patch patcher(module, nullptr);
int width = cell->getPort(ID::A).size();
int width = cell->getPort(TW::A).size();
auto sub = patcher.addSub(NEW_ID,
neg->getPort(ID::A),
add->getPort(ID::A),
patcher.addWire(NEW_ID, width));
auto new_out_wire = patcher.addWire(NEW_ID, width);
auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(ID::Y), new_out_wire);
neg->getPort(TW::A),
add->getPort(TW::A),
patcher.addWire(NEW_TWINE, width));
auto new_out_wire = patcher.addWire(NEW_TWINE, width);
auto new_cell = patcher.addNeg(NEW_ID, sub->getPort(TW::Y), new_out_wire);
log_cell(new_cell);
patcher.patch(add, ID::Y, new_out_wire);
}

2
passes/cmds/trace.cc
View file

@ -36,7 +36,7 @@ struct TraceMonitor : public RTLIL::Monitor
log("#TRACE# Module delete: %s\n", module);
}
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", cell->module, cell, port.unescape(), log_signal(sig), log_signal(old_sig));
}

180
passes/cmds/xprop.cc
View file

@ -202,9 +202,9 @@ struct XpropWorker
EncodedSig new_sigs;
if (new_bits > 0) {
new_sigs.is_0 = module->addWire(NEW_ID, new_bits);
new_sigs.is_1 = module->addWire(NEW_ID, new_bits);
new_sigs.is_x = module->addWire(NEW_ID, new_bits);
new_sigs.is_0 = module->addWire(NEW_TWINE, new_bits);
new_sigs.is_1 = module->addWire(NEW_TWINE, new_bits);
new_sigs.is_x = module->addWire(NEW_TWINE, new_bits);
}
int invert_pos = 0;
@ -319,8 +319,8 @@ struct XpropWorker
}
if (cell->type == ID($not)) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]))
mark_maybe_x(sig_y[i]);
@ -328,9 +328,9 @@ struct XpropWorker
}
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto sig_b = cell->getPort(ID::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A); sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
auto sig_b = cell->getPort(TW::B); sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]))
mark_maybe_x(sig_y[i]);
@ -338,10 +338,10 @@ struct XpropWorker
}
if (cell->type.in(ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
for (int i = 0; i < GetSize(sig_y); i++)
if (maybe_x(sig_a[i]) || maybe_x(sig_b[i]) || maybe_x(sig_s[i]))
mark_maybe_x(sig_y[i]);
@ -349,10 +349,10 @@ struct XpropWorker
}
if (cell->type.in(ID($_MUX_), ID($mux), ID($bmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
if (maybe_x(sig_s)) {
mark_maybe_x(sig_y);
return;
@ -373,9 +373,9 @@ struct XpropWorker
}
if (cell->type.in(ID($demux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_s = cell->getPort(TW::S);
if (maybe_x(sig_s)) {
mark_maybe_x(sig_y);
return;
@ -388,15 +388,15 @@ struct XpropWorker
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift))) {
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_b = cell->getPort(TW::B);
auto &sig_y = cell->getPort(TW::Y);
if (maybe_x(sig_b)) {
mark_maybe_x(sig_y);
return;
}
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
if (maybe_x(sig_a)) {
// We could be more precise for shifts, but that's not required
@ -408,15 +408,15 @@ struct XpropWorker
}
if (cell->type.in(ID($shiftx))) {
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(ID::Y);
auto &sig_b = cell->getPort(TW::B);
auto &sig_y = cell->getPort(TW::Y);
if (cell->getParam(ID::B_SIGNED).as_bool() || GetSize(sig_b) >= 30) {
mark_maybe_x(sig_y);
} else {
int max_shift = (1 << GetSize(sig_b)) - 1;
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
for (int i = 0; i < GetSize(sig_y); i++)
if (i + max_shift >= GetSize(sig_a))
@ -428,7 +428,7 @@ struct XpropWorker
return;
}
auto &sig_a = cell->getPort(ID::A);
auto &sig_a = cell->getPort(TW::A);
if (maybe_x(sig_a)) {
// We could be more precise for shifts, but that's not required
// for correctness, so let's keep it simple
@ -457,7 +457,7 @@ struct XpropWorker
ID($_NOT_), ID($_AND_), ID($_NAND_), ID($_ANDNOT_), ID($_OR_), ID($_NOR_), ID($_ORNOT_), ID($_XOR_), ID($_XNOR_)
)) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_y = cell->getPort(TW::Y);
if (inputs_maybe_x(cell))
mark_maybe_x(sig_y[0]);
return;
@ -482,9 +482,9 @@ struct XpropWorker
if (!ports_maybe_x(cell)) {
if (cell->type == ID($bweq)) {
auto sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
RTLIL::IdString name(cell->name);
module->remove(cell);
@ -493,9 +493,9 @@ struct XpropWorker
}
if (cell->type.in(ID($nex), ID($eqx))) {
auto sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
RTLIL::IdString name(cell->name);
auto type = cell->type;
@ -511,8 +511,8 @@ struct XpropWorker
}
if (cell->type.in(ID($not), ID($_NOT_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
if (cell->type == ID($not))
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
@ -528,9 +528,9 @@ struct XpropWorker
}
if (cell->type.in(ID($and), ID($or), ID($_AND_), ID($_OR_), ID($_NAND_), ID($_NOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($and), ID($or))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -555,8 +555,8 @@ struct XpropWorker
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool), ID($logic_not))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto enc_a = encoded(sig_a);
auto enc_y = encoded(sig_y, true);
@ -577,8 +577,8 @@ struct XpropWorker
}
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto enc_a = encoded(sig_a);
auto enc_y = encoded(sig_y, true);
@ -597,9 +597,9 @@ struct XpropWorker
}
if (cell->type.in(ID($logic_and), ID($logic_or))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -623,9 +623,9 @@ struct XpropWorker
}
if (cell->type.in(ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($xor), ID($xnor))) {
sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
@ -646,9 +646,9 @@ struct XpropWorker
}
if (cell->type.in(ID($eq), ID($ne))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -672,9 +672,9 @@ struct XpropWorker
}
if (cell->type.in(ID($eqx), ID($nex))) {
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
int width = std::max(GetSize(sig_a), GetSize(sig_b));
sig_a.extend_u0(width, cell->getParam(ID::A_SIGNED).as_bool());
sig_b.extend_u0(width, cell->getParam(ID::B_SIGNED).as_bool());
@ -697,9 +697,9 @@ struct XpropWorker
}
if (cell->type.in(ID($bweqx))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -712,10 +712,10 @@ struct XpropWorker
}
if (cell->type.in(ID($_MUX_), ID($mux), ID($bwmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto sig_s = cell->getPort(TW::S);
if (cell->type == ID($mux))
sig_s = SigSpec(sig_s[0], GetSize(sig_y));
@ -737,10 +737,10 @@ struct XpropWorker
}
if (cell->type.in(ID($pmux))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_s = cell->getPort(ID::S);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto &sig_s = cell->getPort(TW::S);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -772,9 +772,9 @@ struct XpropWorker
}
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx))) {
auto &sig_y = cell->getPort(ID::Y);
auto &sig_a = cell->getPort(ID::A);
auto &sig_b = cell->getPort(ID::B);
auto &sig_y = cell->getPort(TW::Y);
auto &sig_a = cell->getPort(TW::A);
auto &sig_b = cell->getPort(TW::B);
auto enc_a = encoded(sig_a);
auto enc_b = encoded(sig_b);
@ -783,9 +783,9 @@ struct XpropWorker
auto all_x = module->ReduceOr(NEW_ID, enc_b.is_x)[0];
auto not_all_x = module->Not(NEW_ID, all_x)[0];
SigSpec y_not_0 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_ID, GetSize(sig_y));
SigSpec y_not_0 = module->addWire(NEW_TWINE, GetSize(sig_y));
SigSpec y_1 = module->addWire(NEW_TWINE, GetSize(sig_y));
SigSpec y_x = module->addWire(NEW_TWINE, GetSize(sig_y));
auto encoded_type = cell->type == ID($shiftx) ? ID($shift) : cell->type;
@ -793,23 +793,23 @@ struct XpropWorker
std::swap(enc_a.is_0, enc_a.is_x);
}
auto shift_0 = module->addCell(NEW_ID, encoded_type);
auto shift_0 = module->addCell(NEW_TWINE, encoded_type);
shift_0->parameters = cell->parameters;
shift_0->setPort(ID::A, module->Not(NEW_ID, enc_a.is_0));
shift_0->setPort(ID::B, enc_b.is_1);
shift_0->setPort(ID::Y, y_not_0);
shift_0->setPort(TW::A, module->Not(NEW_ID, enc_a.is_0));
shift_0->setPort(TW::B, enc_b.is_1);
shift_0->setPort(TW::Y, y_not_0);
auto shift_1 = module->addCell(NEW_ID, encoded_type);
auto shift_1 = module->addCell(NEW_TWINE, encoded_type);
shift_1->parameters = cell->parameters;
shift_1->setPort(ID::A, enc_a.is_1);
shift_1->setPort(ID::B, enc_b.is_1);
shift_1->setPort(ID::Y, y_1);
shift_1->setPort(TW::A, enc_a.is_1);
shift_1->setPort(TW::B, enc_b.is_1);
shift_1->setPort(TW::Y, y_1);
auto shift_x = module->addCell(NEW_ID, encoded_type);
auto shift_x = module->addCell(NEW_TWINE, encoded_type);
shift_x->parameters = cell->parameters;
shift_x->setPort(ID::A, enc_a.is_x);
shift_x->setPort(ID::B, enc_b.is_1);
shift_x->setPort(ID::Y, y_x);
shift_x->setPort(TW::A, enc_a.is_x);
shift_x->setPort(TW::B, enc_b.is_1);
shift_x->setPort(TW::Y, y_x);
SigSpec y_0 = module->Not(NEW_ID, y_not_0);
@ -825,8 +825,8 @@ struct XpropWorker
}
if (cell->type.in(ID($ff))) {
auto &sig_d = cell->getPort(ID::D);
auto &sig_q = cell->getPort(ID::Q);
auto &sig_d = cell->getPort(TW::D);
auto &sig_q = cell->getPort(TW::Q);
auto init_q = initvals(sig_q);
auto init_q_is_1 = init_q;
@ -842,7 +842,7 @@ struct XpropWorker
auto enc_d = encoded(sig_d);
auto enc_q = encoded(sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(sig_q));
auto data_q = module->addWire(NEW_TWINE, GetSize(sig_q));
module->addFf(NEW_ID, enc_d.is_1, data_q);
module->addFf(NEW_ID, enc_d.is_x, enc_q.is_x);
@ -885,7 +885,7 @@ struct XpropWorker
auto enc_d = encoded(ff.sig_d);
auto enc_q = encoded(ff.sig_q, true);
auto data_q = module->addWire(NEW_ID, GetSize(ff.sig_q));
auto data_q = module->addWire(NEW_TWINE, GetSize(ff.sig_q));
ff.sig_d = enc_d.is_1;
ff.sig_q = data_q;
@ -928,11 +928,11 @@ struct XpropWorker
}
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
auto sig_b = cell->getPort(ID::B);
auto sig_b = cell->getPort(TW::B);
auto invalid = module->LogicNot(NEW_ID, sig_b);
inbits_x.append(invalid);
sig_b[0] = module->Or(NEW_ID, sig_b[0], invalid);
cell->setPort(ID::B, sig_b);
cell->setPort(TW::B, sig_b);
}
SigBit outbits_x = (GetSize(inbits_x) == 1 ? inbits_x : module->ReduceOr(NEW_ID, inbits_x));
@ -945,7 +945,7 @@ struct XpropWorker
if (bool_out)
enc_port.connect_as_bool();
SigSpec new_output = module->addWire(NEW_ID, GetSize(conn.second));
SigSpec new_output = module->addWire(NEW_TWINE, GetSize(conn.second));
enc_port.connect_1_under_x(bool_out ? new_output.extract(0) : new_output);
enc_port.connect_x(SigSpec(outbits_x, GetSize(enc_port)));

8
passes/equiv/equiv_add.cc
View file

@ -84,7 +84,7 @@ struct EquivAddPass : public Pass {
if (gold_cell->input(port) && gate_cell->input(port))
{
SigSpec combined_sig = module->addWire(NEW_ID, width);
SigSpec combined_sig = module->addWire(NEW_TWINE, width);
for (int i = 0; i < width; i++) {
module->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], combined_sig[i]);
@ -98,8 +98,8 @@ struct EquivAddPass : public Pass {
if (gold_cell->output(port) && gate_cell->output(port))
{
SigSpec new_gold_wire = module->addWire(NEW_ID, width);
SigSpec new_gate_wire = module->addWire(NEW_ID, width);
SigSpec new_gold_wire = module->addWire(NEW_TWINE, width);
SigSpec new_gate_wire = module->addWire(NEW_TWINE, width);
SigSig gg_conn;
for (int i = 0; i < width; i++) {
@ -141,7 +141,7 @@ struct EquivAddPass : public Pass {
}
log_assert(GetSize(gold_signal) == GetSize(gate_signal));
SigSpec equiv_signal = module->addWire(NEW_ID, GetSize(gold_signal));
SigSpec equiv_signal = module->addWire(NEW_TWINE, GetSize(gold_signal));
SigMap sigmap(module);
sigmap.apply(gold_signal);

16
passes/equiv/equiv_induct.cc
View file

@ -48,8 +48,8 @@ struct EquivInductWorker : public EquivWorker<>
report_missing_model(cfg.ignore_unknown_cells, cell);
}
if (cell->type == ID($equiv)) {
SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit();
if (bit_a != bit_b) {
int ez_a = satgen.importSigBit(bit_a, step);
int ez_b = satgen.importSigBit(bit_b, step);
@ -126,7 +126,7 @@ struct EquivInductWorker : public EquivWorker<>
if (!ez->solve(new_step_not_consistent)) {
log(" Proof for induction step holds. Entire workset of %d cells proven!\n", GetSize(workset));
for (auto cell : workset)
cell->setPort(ID::B, cell->getPort(ID::A));
cell->setPort(TW::B, cell->getPort(TW::A));
success_counter += GetSize(workset);
return;
}
@ -138,10 +138,10 @@ struct EquivInductWorker : public EquivWorker<>
for (auto cell : workset)
{
SigBit bit_a = sigmap(cell->getPort(ID::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(ID::B)).as_bit();
SigBit bit_a = sigmap(cell->getPort(TW::A)).as_bit();
SigBit bit_b = sigmap(cell->getPort(TW::B)).as_bit();
log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(ID::Y))));
log(" Trying to prove $equiv for %s:", log_signal(sigmap(cell->getPort(TW::Y))));
int ez_a = satgen.importSigBit(bit_a, cfg.max_seq+1);
int ez_b = satgen.importSigBit(bit_b, cfg.max_seq+1);
@ -152,7 +152,7 @@ struct EquivInductWorker : public EquivWorker<>
if (!ez->solve(cond)) {
log(" success!\n");
cell->setPort(ID::B, cell->getPort(ID::A));
cell->setPort(TW::B, cell->getPort(TW::A));
success_counter++;
} else {
log(" failed.\n");
@ -212,7 +212,7 @@ struct EquivInductPass : public Pass {
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->getPort(ID::A) != cell->getPort(ID::B))
if (cell->getPort(TW::A) != cell->getPort(TW::B))
unproven_equiv_cells.insert(cell);
}

6
passes/equiv/equiv_make.cc
View file

@ -210,8 +210,8 @@ struct EquivMakeWorker
for (auto &bit : enc_result)
if (bit != State::S1) bit = State::S0;
SigSpec dec_eq = equiv_mod->addWire(NEW_ID);
SigSpec enc_eq = equiv_mod->addWire(NEW_ID);
SigSpec dec_eq = equiv_mod->addWire(NEW_TWINE);
SigSpec enc_eq = equiv_mod->addWire(NEW_TWINE);
equiv_mod->addEq(NEW_ID, reduced_dec_sig, reduced_dec_pat, dec_eq);
cells_list.push_back(equiv_mod->addEq(NEW_ID, reduced_enc_sig, reduced_enc_pat, enc_eq));
@ -370,7 +370,7 @@ struct EquivMakeWorker
{
for (int i = 0; i < GetSize(gold_sig); i++)
if (gold_sig[i] != gate_sig[i]) {
Wire *w = equiv_mod->addWire(NEW_ID);
Wire *w = equiv_mod->addWire(NEW_TWINE);
equiv_mod->addEquiv(NEW_ID, gold_sig[i], gate_sig[i], w);
gold_sig[i] = w;
}

8
passes/equiv/equiv_mark.cc
View file

@ -122,8 +122,8 @@ struct EquivMarkWorker
{
auto cell = module->cell(cell_name);
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
if (sig_a == sig_b) {
for (auto bit : sig_a)
@ -142,8 +142,8 @@ struct EquivMarkWorker
if (cell_regions.count(cell->name) || cell->type != ID($equiv))
continue;
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
log_assert(sig_a != sig_b);

10
passes/equiv/equiv_miter.cc
View file

@ -214,18 +214,18 @@ struct EquivMiterWorker
vector<Cell*> equiv_cells;
for (auto c : miter_module->cells())
if (c->type == ID($equiv) && c->getPort(ID::A) != c->getPort(ID::B))
if (c->type == ID($equiv) && c->getPort(TW::A) != c->getPort(TW::B))
equiv_cells.push_back(c);
for (auto c : equiv_cells)
{
SigSpec cmp = mode_undef ?
miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(ID::A), State::Sx),
miter_module->Eqx(NEW_ID, c->getPort(ID::A), c->getPort(ID::B))) :
miter_module->Eq(NEW_ID, c->getPort(ID::A), c->getPort(ID::B));
miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort(TW::A), State::Sx),
miter_module->Eqx(NEW_ID, c->getPort(TW::A), c->getPort(TW::B))) :
miter_module->Eq(NEW_ID, c->getPort(TW::A), c->getPort(TW::B));
if (mode_cmp) {
string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(ID::Y)));
string cmp_name = stringf("\\cmp%s", log_signal(c->getPort(TW::Y)));
for (int i = 1; i < GetSize(cmp_name); i++)
if (cmp_name[i] == '\\')
cmp_name[i] = '_';

14
passes/equiv/equiv_purge.cc
View file

@ -67,7 +67,7 @@ struct EquivPurgeWorker
log(" Module input: %s\n", log_signal(wire));
wire->port_input = true;
}
return module->addWire(NEW_ID, GetSize(sig));
return module->addWire(NEW_TWINE, GetSize(sig));
}
}
@ -81,7 +81,7 @@ struct EquivPurgeWorker
wire->port_input = true;
module->connect(sig, wire);
log(" Module input: %s (%s)\n", log_signal(wire), log_signal(sig));
return module->addWire(NEW_ID, GetSize(sig));
return module->addWire(NEW_TWINE, GetSize(sig));
}
}
@ -114,9 +114,9 @@ struct EquivPurgeWorker
continue;
}
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
if (sig_a == sig_b)
continue;
@ -130,7 +130,7 @@ struct EquivPurgeWorker
for (auto bit : sig_y)
visited.insert(bit);
cell->setPort(ID::Y, make_output(sig_y, cell->name));
cell->setPort(TW::Y, make_output(sig_y, cell->name));
}
SigSpec srcsig;
@ -168,7 +168,7 @@ struct EquivPurgeWorker
for (auto cell : module->cells())
if (cell->type == ID($equiv))
cell->setPort(ID::Y, rewrite_sigmap(sigmap(cell->getPort(ID::Y))));
cell->setPort(TW::Y, rewrite_sigmap(sigmap(cell->getPort(TW::Y))));
module->fixup_ports();
}

6
passes/equiv/equiv_remove.cc
View file

@ -68,9 +68,9 @@ struct EquivRemovePass : public Pass {
for (auto module : design->selected_modules())
{
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(ID::A) == cell->getPort(ID::B))) {
log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(ID::Y)));
module->connect(cell->getPort(ID::Y), mode_gate ? cell->getPort(ID::B) : cell->getPort(ID::A));
if (cell->type == ID($equiv) && (mode_gold || mode_gate || cell->getPort(TW::A) == cell->getPort(TW::B))) {
log("Removing $equiv cell %s.%s (%s).\n", module, cell, log_signal(cell->getPort(TW::Y)));
module->connect(cell->getPort(TW::Y), mode_gate ? cell->getPort(TW::B) : cell->getPort(TW::A));
module->remove(cell);
remove_count++;
}

20
passes/equiv/equiv_simple.cc
View file

@ -230,8 +230,8 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
pool<Cell*> extra_problem_cells;
for (auto assume : assume_cells) {
pool<SigBit> assume_seed, dummy_next_seed, overlap_bits;
assume_seed.insert(model.sigmap(assume->getPort(ID::A)).as_bit());
assume_seed.insert(model.sigmap(assume->getPort(ID::EN)).as_bit());
assume_seed.insert(model.sigmap(assume->getPort(TW::A)).as_bit());
assume_seed.insert(model.sigmap(assume->getPort(TW::EN)).as_bit());
for (auto& cone : {cone_a, cone_b}) {
Cone assume_cone;
@ -292,8 +292,8 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
bool prove_equiv_cell(Cell* cell)
{
SigBit bit_a = model.sigmap(cell->getPort(ID::A)).as_bit();
SigBit bit_b = model.sigmap(cell->getPort(ID::B)).as_bit();
SigBit bit_a = model.sigmap(cell->getPort(TW::A)).as_bit();
SigBit bit_b = model.sigmap(cell->getPort(TW::B)).as_bit();
int ez_context = ez->frozen_literal();
prepare_ezsat(ez_context, bit_a, bit_b);
@ -306,9 +306,9 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
if (cfg.verbose) {
log(" Trying to prove $equiv cell %s:\n", cell);
log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(cell->getPort(ID::Y)));
log(" A = %s, B = %s, Y = %s\n", log_signal(bit_a), log_signal(bit_b), log_signal(cell->getPort(TW::Y)));
} else {
log(" Trying to prove $equiv for %s:", log_signal(cell->getPort(ID::Y)));
log(" Trying to prove $equiv for %s:", log_signal(cell->getPort(TW::Y)));
}
int step = cfg.max_seq;
@ -347,7 +347,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
if (!ez->solve(ez_context)) {
log("%s", cfg.verbose ? " Proved equivalence! Marking $equiv cell as proven.\n" : " success!\n");
// Replace $equiv cell with a short
cell->setPort(ID::B, cell->getPort(ID::A));
cell->setPort(TW::B, cell->getPort(TW::A));
ez->assume(ez->NOT(ez_context));
return true;
}
@ -404,7 +404,7 @@ struct EquivSimpleWorker : public EquivWorker<EquivSimpleConfig>
if (GetSize(equiv_cells) > 1) {
SigSpec sig;
for (auto c : equiv_cells)
sig.append(model.sigmap(c->getPort(ID::Y)));
sig.append(model.sigmap(c->getPort(TW::Y)));
log(" Grouping SAT models for %s:\n", log_signal(sig));
}
@ -461,8 +461,8 @@ struct EquivSimplePass : public Pass {
int unproven_cells_counter = 0;
for (auto cell : module->selected_cells()) {
if (cell->type == ID($equiv) && cell->getPort(ID::A) != cell->getPort(ID::B)) {
auto bit = sigmap(cell->getPort(ID::Y).as_bit());
if (cell->type == ID($equiv) && cell->getPort(TW::A) != cell->getPort(TW::B)) {
auto bit = sigmap(cell->getPort(TW::Y).as_bit());
auto bit_group = bit;
if (cfg.group && bit_group.wire)
bit_group.offset = 0;

4
passes/equiv/equiv_status.cc
View file

@ -60,7 +60,7 @@ struct EquivStatusPass : public Pass {
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
if (cell->getPort(ID::A) != cell->getPort(ID::B))
if (cell->getPort(TW::A) != cell->getPort(TW::B))
unproven_equiv_cells.push_back(cell);
else
proven_equiv_cells++;
@ -77,7 +77,7 @@ struct EquivStatusPass : public Pass {
log(" Equivalence successfully proven!\n");
} else {
for (auto cell : unproven_equiv_cells)
log(" Unproven $equiv %s: %s %s\n", cell, log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
log(" Unproven $equiv %s: %s %s\n", cell, log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B)));
}
unproven_count += GetSize(unproven_equiv_cells);

12
passes/equiv/equiv_struct.cc
View file

@ -85,7 +85,7 @@ struct EquivStructWorker
for (int i = 0; i < GetSize(inputs_a); i++) {
SigBit bit_a = inputs_a[i], bit_b = inputs_b[i];
SigBit bit_y = module->addWire(NEW_ID);
SigBit bit_y = module->addWire(NEW_TWINE);
log(" New $equiv for input %s: A: %s, B: %s, Y: %s\n",
input_names[i].c_str(), log_signal(bit_a), log_signal(bit_b), log_signal(bit_y));
module->addEquiv(NEW_ID, bit_a, bit_b, bit_y);
@ -127,8 +127,8 @@ struct EquivStructWorker
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
equiv_bits.add(sig_b, sig_a);
equiv_inputs.insert(sig_a);
equiv_inputs.insert(sig_b);
@ -140,9 +140,9 @@ struct EquivStructWorker
for (auto cell : module->selected_cells())
if (cell->type == ID($equiv)) {
SigBit sig_a = sigmap(cell->getPort(ID::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(ID::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit sig_a = sigmap(cell->getPort(TW::A).as_bit());
SigBit sig_b = sigmap(cell->getPort(TW::B).as_bit());
SigBit sig_y = sigmap(cell->getPort(TW::Y).as_bit());
if (sig_a == sig_b && equiv_inputs.count(sig_y)) {
log(" Purging redundant $equiv cell %s.\n", cell);
module->connect(sig_y, sig_a);

16
passes/fsm/fsm_detect.cc
View file

@ -67,8 +67,8 @@ ret_false:
recursion_monitor.insert(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(ID::B));
RTLIL::SigSpec sig_a = assign_map(cellport.first->getPort(TW::A));
RTLIL::SigSpec sig_b = assign_map(cellport.first->getPort(TW::B));
if (!check_state_mux_tree(old_sig, sig_a, recursion_monitor, mux_tree_cache)) {
recursion_monitor.erase(cellport.first);
@ -101,7 +101,7 @@ static bool check_state_users(RTLIL::SigSpec sig)
continue;
if (cell->type.in(ID($input_port), ID($output_port), ID($public)))
continue;
if (cell->type == ID($logic_not) && assign_map(cell->getPort(ID::A)) == sig)
if (cell->type == ID($logic_not) && assign_map(cell->getPort(TW::A)) == sig)
continue;
if (cellport.second != ID::A && cellport.second != ID::B)
return false;
@ -110,9 +110,9 @@ static bool check_state_users(RTLIL::SigSpec sig)
for (auto &port_it : cell->connections())
if (port_it.first != ID::A && port_it.first != ID::B && port_it.first != ID::Y)
return false;
if (assign_map(cell->getPort(ID::A)) == sig && cell->getPort(ID::B).is_fully_const())
if (assign_map(cell->getPort(TW::A)) == sig && cell->getPort(TW::B).is_fully_const())
continue;
if (assign_map(cell->getPort(ID::B)) == sig && cell->getPort(ID::A).is_fully_const())
if (assign_map(cell->getPort(TW::B)) == sig && cell->getPort(TW::A).is_fully_const())
continue;
return false;
}
@ -150,8 +150,8 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
muxtree_cells.clear();
pool<Cell*> recursion_monitor;
RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(ID::Q));
RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(ID::D));
RTLIL::SigSpec sig_q = assign_map(cellport.first->getPort(TW::Q));
RTLIL::SigSpec sig_d = assign_map(cellport.first->getPort(TW::D));
dict<RTLIL::SigSpec, bool> mux_tree_cache;
if (sig_q != assign_map(wire))
@ -203,7 +203,7 @@ static void detect_fsm(RTLIL::Wire *wire, bool ignore_self_reset=false)
SigSpec sig_y = sig_d, sig_undef;
if (!ignore_self_reset) {
if (cellport.first->type == ID($adff)) {
SigSpec sig_arst = assign_map(cellport.first->getPort(ID::ARST));
SigSpec sig_arst = assign_map(cellport.first->getPort(TW::ARST));
if (ce.eval(sig_arst, sig_undef))
is_self_resetting = true;
}

46
passes/fsm/fsm_expand.cc
View file

@ -35,12 +35,12 @@ struct FsmExpand
bool full_mode;
SigMap assign_map;
SigSet<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> sig2driver, sig2user;
SigSet<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> sig2driver, sig2user;
CellTypes ct;
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> merged_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> current_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name_id<RTLIL::Cell>> no_candidate_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> merged_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> current_set;
std::set<RTLIL::Cell*, RTLIL::sort_by_name<RTLIL::Cell>> no_candidate_set;
bool already_optimized;
int limit_transitions;
@ -51,38 +51,38 @@ struct FsmExpand
return true;
if (cell->type.in(ID($mux), ID($pmux)))
if (cell->getPort(ID::A).size() < 2)
if (cell->getPort(TW::A).size() < 2)
return true;
int in_bits = 0;
RTLIL::SigSpec new_signals;
if (cell->hasPort(ID::A)) {
in_bits += GetSize(cell->getPort(ID::A));
new_signals.append(assign_map(cell->getPort(ID::A)));
in_bits += GetSize(cell->getPort(TW::A));
new_signals.append(assign_map(cell->getPort(TW::A)));
}
if (cell->hasPort(ID::B)) {
in_bits += GetSize(cell->getPort(ID::B));
new_signals.append(assign_map(cell->getPort(ID::B)));
in_bits += GetSize(cell->getPort(TW::B));
new_signals.append(assign_map(cell->getPort(TW::B)));
}
if (cell->hasPort(ID::S)) {
in_bits += GetSize(cell->getPort(ID::S));
new_signals.append(assign_map(cell->getPort(ID::S)));
in_bits += GetSize(cell->getPort(TW::S));
new_signals.append(assign_map(cell->getPort(TW::S)));
}
if (in_bits > 8)
return false;
if (cell->hasPort(ID::Y))
new_signals.append(assign_map(cell->getPort(ID::Y)));
new_signals.append(assign_map(cell->getPort(TW::Y)));
new_signals.sort_and_unify();
new_signals.remove_const();
new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_IN)));
new_signals.remove(assign_map(fsm_cell->getPort(ID::CTRL_OUT)));
new_signals.remove(assign_map(fsm_cell->getPort(TW::CTRL_IN)));
new_signals.remove(assign_map(fsm_cell->getPort(TW::CTRL_OUT)));
if (new_signals.size() > 3)
return false;
@ -94,10 +94,10 @@ struct FsmExpand
{
std::vector<RTLIL::Cell*> cell_list;
for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(ID::CTRL_IN))))
for (auto c : sig2driver.find(assign_map(fsm_cell->getPort(TW::CTRL_IN))))
cell_list.push_back(c);
for (auto c : sig2user.find(assign_map(fsm_cell->getPort(ID::CTRL_OUT))))
for (auto c : sig2user.find(assign_map(fsm_cell->getPort(TW::CTRL_OUT))))
cell_list.push_back(c);
current_set.clear();
@ -160,11 +160,11 @@ struct FsmExpand
RTLIL::Const in_val(i, input_sig.size());
RTLIL::SigSpec A, B, S;
if (cell->hasPort(ID::A))
A = assign_map(cell->getPort(ID::A));
A = assign_map(cell->getPort(TW::A));
if (cell->hasPort(ID::B))
B = assign_map(cell->getPort(ID::B));
B = assign_map(cell->getPort(TW::B));
if (cell->hasPort(ID::S))
S = assign_map(cell->getPort(ID::S));
S = assign_map(cell->getPort(TW::S));
A.replace(input_sig, RTLIL::SigSpec(in_val));
B.replace(input_sig, RTLIL::SigSpec(in_val));
S.replace(input_sig, RTLIL::SigSpec(in_val));
@ -178,14 +178,14 @@ struct FsmExpand
fsm_data.copy_from_cell(fsm_cell);
fsm_data.num_inputs += input_sig.size();
RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec new_ctrl_in = fsm_cell->getPort(TW::CTRL_IN);
new_ctrl_in.append(input_sig);
fsm_cell->setPort(ID::CTRL_IN, new_ctrl_in);
fsm_cell->setPort(TW::CTRL_IN, new_ctrl_in);
fsm_data.num_outputs += output_sig.size();
RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
RTLIL::SigSpec new_ctrl_out = fsm_cell->getPort(TW::CTRL_OUT);
new_ctrl_out.append(output_sig);
fsm_cell->setPort(ID::CTRL_OUT, new_ctrl_out);
fsm_cell->setPort(TW::CTRL_OUT, new_ctrl_out);
if (GetSize(input_sig) > 10)
log_warning("Cell %s.%s (%s) has %d input bits, merging into FSM %s.%s might be problematic.\n",

34
passes/fsm/fsm_extract.cc
View file

@ -75,10 +75,10 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
return false;
}
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y));
RTLIL::SigSpec sig_aa = sig;
sig_aa.replace(sig_y, sig_a);
@ -275,12 +275,12 @@ static void extract_fsm(RTLIL::Wire *wire)
if ((cell->type != ID($dff) && cell->type != ID($adff)) || cellport.second != ID::Q)
continue;
log(" found %s cell for state register: %s\n", cell->type, cell->name);
RTLIL::SigSpec sig_q = assign_map(cell->getPort(ID::Q));
RTLIL::SigSpec sig_d = assign_map(cell->getPort(ID::D));
clk = cell->getPort(ID::CLK);
RTLIL::SigSpec sig_q = assign_map(cell->getPort(TW::Q));
RTLIL::SigSpec sig_d = assign_map(cell->getPort(TW::D));
clk = cell->getPort(TW::CLK);
clk_polarity = cell->parameters[ID::CLK_POLARITY].as_bool();
if (cell->type == ID($adff)) {
arst = cell->getPort(ID::ARST);
arst = cell->getPort(TW::ARST);
arst_polarity = cell->parameters[ID::ARST_POLARITY].as_bool();
reset_state = cell->parameters[ID::ARST_VALUE];
}
@ -320,11 +320,11 @@ static void extract_fsm(RTLIL::Wire *wire)
sig2trigger.find(dff_out, cellport_list);
for (auto &cellport : cellport_list) {
RTLIL::Cell *cell = module->cell(cellport.first);
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
RTLIL::SigSpec sig_b;
if (cell->hasPort(ID::B))
sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y));
if (cellport.second == ID::A && !sig_b.is_fully_const())
continue;
if (cellport.second == ID::B && !sig_a.is_fully_const())
@ -369,12 +369,12 @@ static void extract_fsm(RTLIL::Wire *wire)
// create fsm cell
RTLIL::Cell *fsm_cell = module->addCell(stringf("$fsm$%s$%d", wire->name, autoidx++), ID($fsm));
fsm_cell->setPort(ID::CLK, clk);
fsm_cell->setPort(ID::ARST, arst);
fsm_cell->setPort(TW::CLK, clk);
fsm_cell->setPort(TW::ARST, arst);
fsm_cell->parameters[ID::CLK_POLARITY] = clk_polarity ? State::S1 : State::S0;
fsm_cell->parameters[ID::ARST_POLARITY] = arst_polarity ? State::S1 : State::S0;
fsm_cell->setPort(ID::CTRL_IN, ctrl_in);
fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
fsm_cell->setPort(TW::CTRL_IN, ctrl_in);
fsm_cell->setPort(TW::CTRL_OUT, ctrl_out);
fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
fsm_cell->attributes = wire->attributes;
if(fsm_cell->attributes.count(ID::hdlname)) {
@ -452,14 +452,14 @@ struct FsmExtractPass : public Pass {
sig2driver.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
if (ct.cell_input(cell->type, conn_it.first) && cell->hasPort(ID::Y) &&
cell->getPort(ID::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) {
cell->getPort(TW::Y).size() == 1 && (conn_it.first == ID::A || conn_it.first == ID::B)) {
RTLIL::SigSpec sig = conn_it.second;
assign_map.apply(sig);
sig2trigger.insert(sig, sig2driver_entry_t(cell->name, conn_it.first));
}
}
if (cell->type == ID($pmux)) {
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sel_sig = assign_map(cell->getPort(TW::S));
for (auto &bit1 : sel_sig)
for (auto &bit2 : sel_sig)
if (bit1 != bit2)

74
passes/fsm/fsm_map.cc
View file

@ -71,13 +71,13 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
if (eq_sig_a.size() > 0)
{
RTLIL::Wire *eq_wire = module->addWire(NEW_ID);
RTLIL::Wire *eq_wire = module->addWire(NEW_TWINE);
and_sig.append(RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
eq_cell->setPort(ID::A, eq_sig_a);
eq_cell->setPort(ID::B, eq_sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(eq_wire));
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
eq_cell->setPort(TW::A, eq_sig_a);
eq_cell->setPort(TW::B, eq_sig_b);
eq_cell->setPort(TW::Y, RTLIL::SigSpec(eq_wire));
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(eq_sig_a.size());
@ -99,12 +99,12 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
else
{
RTLIL::Wire *or_wire = module->addWire(NEW_ID);
RTLIL::Wire *or_wire = module->addWire(NEW_TWINE);
and_sig.append(RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
or_cell->setPort(ID::A, or_sig);
or_cell->setPort(ID::Y, RTLIL::SigSpec(or_wire));
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
or_cell->setPort(TW::A, or_sig);
or_cell->setPort(TW::Y, RTLIL::SigSpec(or_wire));
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(or_sig.size());
or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
@ -115,13 +115,13 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
{
case 2:
{
RTLIL::Wire *and_wire = module->addWire(NEW_ID);
RTLIL::Wire *and_wire = module->addWire(NEW_TWINE);
cases_vector.append(RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_ID, ID($and));
and_cell->setPort(ID::A, and_sig.extract(0, 1));
and_cell->setPort(ID::B, and_sig.extract(1, 1));
and_cell->setPort(ID::Y, RTLIL::SigSpec(and_wire));
RTLIL::Cell *and_cell = module->addCell(NEW_TWINE, ID($and));
and_cell->setPort(TW::A, and_sig.extract(0, 1));
and_cell->setPort(TW::B, and_sig.extract(1, 1));
and_cell->setPort(TW::Y, RTLIL::SigSpec(and_wire));
and_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
and_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
and_cell->parameters[ID::A_WIDTH] = RTLIL::Const(1);
@ -141,9 +141,9 @@ static void implement_pattern_cache(RTLIL::Module *module, std::map<RTLIL::Const
}
if (cases_vector.size() > 1) {
RTLIL::Cell *or_cell = module->addCell(NEW_ID, ID($reduce_or));
or_cell->setPort(ID::A, cases_vector);
or_cell->setPort(ID::Y, output);
RTLIL::Cell *or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
or_cell->setPort(TW::A, cases_vector);
or_cell->setPort(TW::Y, output);
or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cases_vector.size());
or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
@ -161,16 +161,16 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
FsmData fsm_data;
fsm_data.copy_from_cell(fsm_cell);
RTLIL::SigSpec ctrl_in = fsm_cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec ctrl_out = fsm_cell->getPort(ID::CTRL_OUT);
RTLIL::SigSpec ctrl_in = fsm_cell->getPort(TW::CTRL_IN);
RTLIL::SigSpec ctrl_out = fsm_cell->getPort(TW::CTRL_OUT);
// create state register
RTLIL::Wire *state_wire = module->addWire(module->uniquify(fsm_cell->parameters[ID::NAME].decode_string()), fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_ID, fsm_data.state_bits);
RTLIL::Wire *next_state_wire = module->addWire(NEW_TWINE, fsm_data.state_bits);
RTLIL::Cell *state_dff = module->addCell(NEW_ID, "");
if (fsm_cell->getPort(ID::ARST).is_fully_const()) {
RTLIL::Cell *state_dff = module->addCell(NEW_TWINE, "");
if (fsm_cell->getPort(TW::ARST).is_fully_const()) {
state_dff->type = ID($dff);
} else {
state_dff->type = ID($adff);
@ -179,19 +179,19 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
for (auto bit : state_dff->parameters[ID::ARST_VALUE])
if (bit != RTLIL::State::S1)
bit = RTLIL::State::S0;
state_dff->setPort(ID::ARST, fsm_cell->getPort(ID::ARST));
state_dff->setPort(TW::ARST, fsm_cell->getPort(TW::ARST));
}
state_dff->parameters[ID::WIDTH] = RTLIL::Const(fsm_data.state_bits);
state_dff->parameters[ID::CLK_POLARITY] = fsm_cell->parameters[ID::CLK_POLARITY];
state_dff->setPort(ID::CLK, fsm_cell->getPort(ID::CLK));
state_dff->setPort(ID::D, RTLIL::SigSpec(next_state_wire));
state_dff->setPort(ID::Q, RTLIL::SigSpec(state_wire));
state_dff->setPort(TW::CLK, fsm_cell->getPort(TW::CLK));
state_dff->setPort(TW::D, RTLIL::SigSpec(next_state_wire));
state_dff->setPort(TW::Q, RTLIL::SigSpec(state_wire));
// decode state register
bool encoding_is_onehot = true;
RTLIL::Wire *state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
RTLIL::Wire *state_onehot = module->addWire(NEW_TWINE, fsm_data.state_table.size());
for (size_t i = 0; i < fsm_data.state_table.size(); i++)
{
@ -212,10 +212,10 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
{
encoding_is_onehot = false;
RTLIL::Cell *eq_cell = module->addCell(NEW_ID, ID($eq));
eq_cell->setPort(ID::A, sig_a);
eq_cell->setPort(ID::B, sig_b);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(state_onehot, i));
RTLIL::Cell *eq_cell = module->addCell(NEW_TWINE, ID($eq));
eq_cell->setPort(TW::A, sig_a);
eq_cell->setPort(TW::B, sig_b);
eq_cell->setPort(TW::Y, RTLIL::SigSpec(state_onehot, i));
eq_cell->parameters[ID::A_SIGNED] = RTLIL::Const(false);
eq_cell->parameters[ID::B_SIGNED] = RTLIL::Const(false);
eq_cell->parameters[ID::A_WIDTH] = RTLIL::Const(sig_a.size());
@ -235,7 +235,7 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
else
{
RTLIL::Wire *next_state_onehot = module->addWire(NEW_ID, fsm_data.state_table.size());
RTLIL::Wire *next_state_onehot = module->addWire(NEW_TWINE, fsm_data.state_table.size());
for (size_t i = 0; i < fsm_data.state_table.size(); i++)
{
@ -285,11 +285,11 @@ static void map_fsm(RTLIL::Cell *fsm_cell, RTLIL::Module *module)
}
}
RTLIL::Cell *mux_cell = module->addCell(NEW_ID, ID($pmux));
mux_cell->setPort(ID::A, sig_a);
mux_cell->setPort(ID::B, sig_b);
mux_cell->setPort(ID::S, sig_s);
mux_cell->setPort(ID::Y, RTLIL::SigSpec(next_state_wire));
RTLIL::Cell *mux_cell = module->addCell(NEW_TWINE, ID($pmux));
mux_cell->setPort(TW::A, sig_a);
mux_cell->setPort(TW::B, sig_b);
mux_cell->setPort(TW::S, sig_s);
mux_cell->setPort(TW::Y, RTLIL::SigSpec(next_state_wire));
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(sig_a.size());
mux_cell->parameters[ID::S_WIDTH] = RTLIL::Const(sig_s.size());
}

14
passes/fsm/fsm_opt.cc
View file

@ -98,7 +98,7 @@ struct FsmOpt
void opt_const_and_unused_inputs()
{
RTLIL::SigSpec ctrl_in = cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec ctrl_in = cell->getPort(TW::CTRL_IN);
std::vector<bool> ctrl_in_used(ctrl_in.size());
std::vector<FsmData::transition_t> new_transition_table;
@ -119,15 +119,15 @@ struct FsmOpt
for (int i = int(ctrl_in_used.size())-1; i >= 0; i--) {
if (!ctrl_in_used[i]) {
log(" Removing unused input signal %s.\n", log_signal(cell->getPort(ID::CTRL_IN).extract(i, 1)));
log(" Removing unused input signal %s.\n", log_signal(cell->getPort(TW::CTRL_IN).extract(i, 1)));
for (auto &tr : new_transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_in);
tmp.remove(i, 1);
tr.ctrl_in = tmp.as_const();
}
RTLIL::SigSpec new_ctrl_in = cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec new_ctrl_in = cell->getPort(TW::CTRL_IN);
new_ctrl_in.remove(i, 1);
cell->setPort(ID::CTRL_IN, new_ctrl_in);
cell->setPort(TW::CTRL_IN, new_ctrl_in);
fsm_data.num_inputs--;
}
}
@ -139,12 +139,12 @@ struct FsmOpt
void opt_unused_outputs()
{
for (int i = 0; i < fsm_data.num_outputs; i++) {
RTLIL::SigSpec sig = cell->getPort(ID::CTRL_OUT).extract(i, 1);
RTLIL::SigSpec sig = cell->getPort(TW::CTRL_OUT).extract(i, 1);
if (signal_is_unused(sig)) {
log(" Removing unused output signal %s.\n", log_signal(sig));
RTLIL::SigSpec new_ctrl_out = cell->getPort(ID::CTRL_OUT);
RTLIL::SigSpec new_ctrl_out = cell->getPort(TW::CTRL_OUT);
new_ctrl_out.remove(i, 1);
cell->setPort(ID::CTRL_OUT, new_ctrl_out);
cell->setPort(TW::CTRL_OUT, new_ctrl_out);
for (auto &tr : fsm_data.transition_table) {
RTLIL::SigSpec tmp(tr.ctrl_out);
tmp.remove(i, 1);

4
passes/fsm/fsmdata.h
View file

@ -127,13 +127,13 @@ struct FsmData
log("\n");
log(" Input signals:\n");
RTLIL::SigSpec sig_in = cell->getPort(ID::CTRL_IN);
RTLIL::SigSpec sig_in = cell->getPort(TW::CTRL_IN);
for (int i = 0; i < GetSize(sig_in); i++)
log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n");
log(" Output signals:\n");
RTLIL::SigSpec sig_out = cell->getPort(ID::CTRL_OUT);
RTLIL::SigSpec sig_out = cell->getPort(TW::CTRL_OUT);
for (int i = 0; i < GetSize(sig_out); i++)
log(" %3d: %s\n", i, log_signal(sig_out[i]));

2
passes/hierarchy/flatten.cc
View file

@ -275,7 +275,7 @@ struct FlattenWorker
if (create_scopeinfo && cell_name.isPublic())
{
// The $scopeinfo's name will be changed below after removing the flattened cell
scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo));
scopeinfo->setParam(ID::TYPE, RTLIL::Const("module"));
for (auto const &attr : cell->attributes)

8
passes/hierarchy/hierarchy.cc
View file

@ -98,7 +98,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
}
while (portnames.size() > 0) {
RTLIL::IdString portname = *portnames.begin();
TwineRef portname = *portnames.begin();
for (auto &decl : portdecls)
if (decl.index == 0 && patmatch(decl.portname.c_str(), portname.unescape().c_str())) {
generate_port_decl_t d = decl;
@ -604,7 +604,7 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
for (auto &conn : cell->connections_) {
int conn_size = conn.second.size();
RTLIL::IdString portname = conn.first;
TwineRef portname = conn.first;
if (portname.begins_with("$")) {
int port_id = atoi(portname.substr(1).c_str());
for (auto wire : mod->wires())
@ -1421,7 +1421,7 @@ struct HierarchyPass : public Pass {
continue;
}
Wire *t = module->addWire(NEW_ID, GetSize(c));
Wire *t = module->addWire(NEW_TWINE, GetSize(c));
new_sig.append(t);
update_port = true;
@ -1524,7 +1524,7 @@ struct HierarchyPass : public Pass {
if (w->port_input && !w->port_output)
sig.extend_u0(GetSize(w), sig.is_wire() && sig.as_wire()->is_signed);
else
sig.append(module->addWire(NEW_ID, n));
sig.append(module->addWire(NEW_TWINE, n));
}
if (!conn.second.is_fully_const() || !w->port_input || w->port_output)

4
passes/hierarchy/submod.cc
View file

@ -233,10 +233,10 @@ struct SubmodWorker
auto &b = old_sig[i];
// Prevents "ERROR: Mismatch in directionality ..." when flattening
if (!b.wire)
b = module->addWire(NEW_ID);
b = module->addWire(NEW_TWINE);
// Prevents "Warning: multiple conflicting drivers ..."
else if (!it.second.is_int_driven[i])
b = module->addWire(NEW_ID);
b = module->addWire(NEW_TWINE);
}
new_cell->setPort(new_wire->name, old_sig);
}

6
passes/memory/memory_bmux2rom.cc
View file

@ -50,7 +50,7 @@ struct MemoryBmux2RomPass : public Pass {
if (cell->type != ID($bmux))
continue;
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_a = cell->getPort(TW::A);
if (!sig_a.is_fully_const())
continue;
@ -70,8 +70,8 @@ struct MemoryBmux2RomPass : public Pass {
mem.inits.push_back(std::move(init));
MemRd rd;
rd.addr = cell->getPort(ID::S);
rd.data = cell->getPort(ID::Y);
rd.addr = cell->getPort(TW::S);
rd.data = cell->getPort(TW::Y);
rd.init_value = Const(State::Sx, width);
rd.arst_value = Const(State::Sx, width);
rd.srst_value = Const(State::Sx, width);

6
passes/memory/memory_bram.cc
View file

@ -903,7 +903,7 @@ grow_read_ports:;
// Swizzle read ports.
for (auto &port : mem.rd_ports) {
SigSpec new_data = module->addWire(NEW_ID, mem.width);
SigSpec new_data = module->addWire(NEW_TWINE, mem.width);
Const new_init_value = Const(State::Sx, mem.width);
Const new_arst_value = Const(State::Sx, mem.width);
Const new_srst_value = Const(State::Sx, mem.width);
@ -1023,12 +1023,12 @@ grow_read_ports:;
auto &port = mem.rd_ports[pi.mapped_port];
SigSpec sig_data = port.data.extract(grid_d * bram.dbits, bram.dbits);
SigSpec bram_dout = module->addWire(NEW_ID, bram.dbits);
SigSpec bram_dout = module->addWire(NEW_TWINE, bram.dbits);
c->setPort(stringf("\\%sDATA", pf), bram_dout);
SigSpec addr_ok_q = addr_ok;
if (port.clk_enable && !addr_ok.empty()) {
addr_ok_q = module->addWire(NEW_ID);
addr_ok_q = module->addWire(NEW_TWINE);
module->addDffe(NEW_ID, port.clk, port.en, addr_ok, addr_ok_q, port.clk_polarity);
}

10
passes/memory/memory_dff.cc
View file

@ -177,7 +177,7 @@ struct MemQueryCache
if (!driver.cell->type.in(ID($mux), ID($pmux)))
return false;
log_assert(driver.port == ID::Y);
SigSpec sig_s = driver.cell->getPort(ID::S);
SigSpec sig_s = driver.cell->getPort(TW::S);
int sel_sat = qcsat.importSigBit(sel);
if (neg_sel)
sel_sat = qcsat.ez->NOT(sel_sat);
@ -187,14 +187,14 @@ struct MemQueryCache
int sbit = qcsat.importSigBit(sig_s[i]);
qcsat.prepare();
if (!qcsat.ez->solve(port_ren, sel_sat, qcsat.ez->NOT(sbit))) {
bit = driver.cell->getPort(ID::B)[i * width + driver.offset];
bit = driver.cell->getPort(TW::B)[i * width + driver.offset];
return true;
}
if (qcsat.ez->solve(port_ren, sel_sat, sbit))
all_0 = false;
}
if (all_0) {
bit = driver.cell->getPort(ID::A)[driver.offset];
bit = driver.cell->getPort(TW::A)[driver.offset];
return true;
}
return false;
@ -264,7 +264,7 @@ struct MemoryDffWorker
} else {
continue;
}
SigSpec y = consumer.cell->getPort(ID::Y);
SigSpec y = consumer.cell->getPort(TW::Y);
int mux_width = GetSize(y);
SigBit ybit = y.extract(consumer.offset);
if (prev_cell != consumer.cell || prev_idx+1 != i || prev_is_b != is_b) {
@ -272,7 +272,7 @@ struct MemoryDffWorker
md.base_idx = i;
md.size = 0;
md.is_b = is_b;
md.sig_s = consumer.cell->getPort(ID::S);
md.sig_s = consumer.cell->getPort(TW::S);
md.sig_other.resize(GetSize(md.sig_s));
prev_cell = consumer.cell;
prev_is_b = is_b;

16
passes/memory/memory_libmap.cc
View file

@ -142,13 +142,13 @@ struct MapWorker {
{
if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
if (sig_a.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
sigmap_xmux.add(cell->getPort(TW::Y), sig_b);
else if (sig_b.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
}
}
@ -1665,14 +1665,14 @@ std::vector<SigSpec> generate_mux(Mem &mem, int rpidx, const Swizzle &swz) {
return {port.data};
}
if (port.clk_enable) {
SigSpec new_sig_s = mem.module->addWire(NEW_ID, GetSize(sig_s));
SigSpec new_sig_s = mem.module->addWire(NEW_TWINE, GetSize(sig_s));
mem.module->addDffe(NEW_ID, port.clk, port.en, sig_s, new_sig_s, port.clk_polarity);
sig_s = new_sig_s;
}
SigSpec sig_a = Const(State::Sx, GetSize(port.data) << hi_bits << GetSize(swz.addr_mux_bits));
for (int i = 0; i < ((swz.addr_end - swz.addr_start) >> swz.addr_shift); i++) {
for (int j = 0; j < (1 << GetSize(swz.addr_mux_bits)); j++) {
SigSpec sig = mem.module->addWire(NEW_ID, GetSize(port.data));
SigSpec sig = mem.module->addWire(NEW_TWINE, GetSize(port.data));
int hi = ((swz.addr_start >> swz.addr_shift) + i) & ((1 << hi_bits) - 1);
int pos = (hi << GetSize(swz.addr_mux_bits) | j) * GetSize(port.data);
for (int k = 0; k < GetSize(port.data); k++)
@ -1948,7 +1948,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), hw_val);
}
}
SigSpec hw_rdata = mem.module->addWire(NEW_ID, width);
SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width);
cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata);
SigSpec lhs;
SigSpec rhs;
@ -1983,7 +1983,7 @@ void MemMapping::emit_port(const MemConfig &cfg, std::vector<Cell*> &cells, cons
else if (pdef.rdsrstval == ResetValKind::NoUndef)
cell->setParam(stringf("\\PORT_%s_RD_SRST_VALUE", name), Const(State::S0, width));
}
SigSpec hw_rdata = mem.module->addWire(NEW_ID, width);
SigSpec hw_rdata = mem.module->addWire(NEW_TWINE, width);
cell->setPort(stringf("\\PORT_%s_RD_DATA", name), hw_rdata);
}
}

34
passes/memory/memory_map.cc
View file

@ -241,7 +241,7 @@ struct MemoryMapWorker
} else {
c = module->addCell(ff_id, ID($dff));
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(RTLIL::State::S1);
c->setPort(ID::CLK, RTLIL::SigSpec(RTLIL::State::S0));
c->setPort(TW::CLK, RTLIL::SigSpec(RTLIL::State::S0));
}
} else if (async_wr) {
log_assert(formal); // General async write not implemented yet, checked against above
@ -249,14 +249,14 @@ struct MemoryMapWorker
} else {
c = module->addCell(ff_id, ID($dff));
c->parameters[ID::CLK_POLARITY] = RTLIL::Const(refclock_pol);
c->setPort(ID::CLK, refclock);
c->setPort(TW::CLK, refclock);
}
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = mem.width;
RTLIL::Wire *w_in = module->addWire(genid(mem.memid, "", addr, "$d"), mem.width);
data_reg_in[idx] = w_in;
c->setPort(ID::D, w_in);
c->setPort(TW::D, w_in);
std::string w_out_name = stringf("%s[%d]", mem.memid, addr);
if (module->wire(RTLIL::IdString(w_out_name)) != nullptr)
@ -276,7 +276,7 @@ struct MemoryMapWorker
w_out->attributes[ID::init] = w_init.as_const();
data_reg_out[idx] = w_out;
c->setPort(ID::Q, w_out);
c->setPort(TW::Q, w_out);
if (static_only)
module->connect(RTLIL::SigSig(w_in, w_out));
@ -308,15 +308,15 @@ struct MemoryMapWorker
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$rdmux", i, "", j, "", k), ID($mux));
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = GetSize(port.data);
c->setPort(ID::Y, rd_signals[k]);
c->setPort(ID::S, rd_addr.extract(abits-j-1, 1));
c->setPort(TW::Y, rd_signals[k]);
c->setPort(TW::S, rd_addr.extract(abits-j-1, 1));
count_mux++;
c->setPort(ID::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data)));
c->setPort(ID::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data)));
c->setPort(TW::A, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$a"), GetSize(port.data)));
c->setPort(TW::B, module->addWire(genid(mem.memid, "$rdmux", i, "", j, "", k, "$b"), GetSize(port.data)));
next_rd_signals.push_back(c->getPort(ID::A));
next_rd_signals.push_back(c->getPort(ID::B));
next_rd_signals.push_back(c->getPort(TW::A));
next_rd_signals.push_back(c->getPort(TW::B));
}
next_rd_signals.swap(rd_signals);
@ -372,22 +372,22 @@ struct MemoryMapWorker
c->parameters[ID::A_WIDTH] = RTLIL::Const(1);
c->parameters[ID::B_WIDTH] = RTLIL::Const(1);
c->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
c->setPort(ID::A, w);
c->setPort(ID::B, wr_bit);
c->setPort(TW::A, w);
c->setPort(TW::B, wr_bit);
w = module->addWire(genid(mem.memid, "$wren", addr, "", j, "", wr_offset, "$y"));
c->setPort(ID::Y, RTLIL::SigSpec(w));
c->setPort(TW::Y, RTLIL::SigSpec(w));
}
RTLIL::Cell *c = module->addCell(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset), ID($mux));
c->set_src_attribute(mem_src);
c->parameters[ID::WIDTH] = wr_width;
c->setPort(ID::A, sig.extract(wr_offset, wr_width));
c->setPort(ID::B, port.data.extract(wr_offset + sub * mem.width, wr_width));
c->setPort(ID::S, RTLIL::SigSpec(w));
c->setPort(TW::A, sig.extract(wr_offset, wr_width));
c->setPort(TW::B, port.data.extract(wr_offset + sub * mem.width, wr_width));
c->setPort(TW::S, RTLIL::SigSpec(w));
w = module->addWire(genid(mem.memid, "$wrmux", addr, "", j, "", wr_offset, "$y"), wr_width);
c->setPort(ID::Y, w);
c->setPort(TW::Y, w);
sig.replace(wr_offset, w);
wr_offset += wr_width;

2
passes/memory/memory_memx.cc
View file

@ -63,7 +63,7 @@ struct MemoryMemxPass : public Pass {
module, mem.memid.unescape());
SigSpec addr_ok = make_addr_check(mem, port.addr);
Wire *raw_rdata = module->addWire(NEW_ID, GetSize(port.data));
Wire *raw_rdata = module->addWire(NEW_TWINE, GetSize(port.data));
module->addMux(NEW_ID, SigSpec(State::Sx, GetSize(port.data)), raw_rdata, addr_ok, port.data);
port.data = raw_rdata;
}

12
passes/memory/memory_share.cc
View file

@ -164,7 +164,7 @@ struct MemoryShareWorker
port2.addr = addr2;
mem.prepare_rd_merge(i, j, &initvals);
mem.widen_prep(wide_log2);
SigSpec new_data = module->addWire(NEW_ID, mem.width << wide_log2);
SigSpec new_data = module->addWire(NEW_TWINE, mem.width << wide_log2);
module->connect(port1.data, new_data.extract(sub1 * mem.width, mem.width << port1.wide_log2));
module->connect(port2.data, new_data.extract(sub2 * mem.width, mem.width << port2.wide_log2));
for (int k = 0; k < wide_log2; k++)
@ -438,7 +438,7 @@ struct MemoryShareWorker
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;
RTLIL::SigSpec grouped_last_en, grouped_this_en, en;
RTLIL::Wire *grouped_en = module->addWire(NEW_ID, 0);
RTLIL::Wire *grouped_en = module->addWire(NEW_TWINE, 0);
for (int j = 0; j < int(this_en.size()); j++) {
std::pair<RTLIL::SigBit, RTLIL::SigBit> key(last_en[j], this_en[j]);
@ -484,13 +484,13 @@ struct MemoryShareWorker
{
if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
if (sig_a.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
sigmap_xmux.add(cell->getPort(TW::Y), sig_b);
else if (sig_b.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
}

50
passes/opt/muxpack.cc
View file

@ -38,11 +38,11 @@ struct ExclusiveDatabase
pool<Cell*> reduce_or;
for (auto cell : module->cells()) {
if (cell->type == ID($eq)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
const_sig = sigmap(cell->getPort(ID::B));
nonconst_sig = sigmap(cell->getPort(TW::A));
const_sig = sigmap(cell->getPort(TW::B));
if (!const_sig.is_fully_const()) {
if (!nonconst_sig.is_fully_const())
continue;
@ -51,10 +51,10 @@ struct ExclusiveDatabase
y_port = y_sig[0];
}
else if (cell->type == ID($logic_not)) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
nonconst_sig = sigmap(cell->getPort(ID::A));
nonconst_sig = sigmap(cell->getPort(TW::A));
const_sig = Const(State::S0, GetSize(nonconst_sig));
y_port = y_sig[0];
}
@ -72,7 +72,7 @@ struct ExclusiveDatabase
for (auto cell : reduce_or) {
nonconst_sig = SigSpec();
std::vector<Const> values;
SigSpec a_port = sigmap(cell->getPort(ID::A));
SigSpec a_port = sigmap(cell->getPort(TW::A));
for (auto bit : a_port) {
auto it = sig_cmp_prev.find(bit);
if (it == sig_cmp_prev.end()) {
@ -90,7 +90,7 @@ struct ExclusiveDatabase
}
if (nonconst_sig.empty())
continue;
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (GetSize(y_sig) == 0)
continue;
y_port = y_sig[0];
@ -154,11 +154,11 @@ struct MuxpackWorker
{
if (cell->type.in(ID($mux), ID($pmux)) && !cell->get_bool_attribute(ID::keep))
{
SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec a_sig = sigmap(cell->getPort(TW::A));
SigSpec b_sig;
if (cell->type == ID($mux))
b_sig = sigmap(cell->getPort(ID::B));
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
b_sig = sigmap(cell->getPort(TW::B));
SigSpec y_sig = sigmap(cell->getPort(TW::Y));
if (sig_chain_next.count(a_sig))
for (auto a_bit : a_sig)
@ -195,9 +195,9 @@ struct MuxpackWorker
{
log_debug("Considering %s (%s)\n", cell, cell->type.unescape());
SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec a_sig = sigmap(cell->getPort(TW::A));
if (cell->type == ID($mux)) {
SigSpec b_sig = sigmap(cell->getPort(ID::B));
SigSpec b_sig = sigmap(cell->getPort(TW::B));
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
goto start_cell;
@ -217,8 +217,8 @@ struct MuxpackWorker
{
Cell *prev_cell = sig_chain_prev.at(a_sig);
log_assert(prev_cell);
SigSpec s_sig = sigmap(cell->getPort(ID::S));
s_sig.append(sigmap(prev_cell->getPort(ID::S)));
SigSpec s_sig = sigmap(cell->getPort(TW::S));
s_sig.append(sigmap(prev_cell->getPort(TW::S)));
if (!excl_db.query(s_sig))
goto start_cell;
}
@ -239,7 +239,7 @@ struct MuxpackWorker
{
chain.push_back(c);
SigSpec y_sig = sigmap(c->getPort(ID::Y));
SigSpec y_sig = sigmap(c->getPort(TW::Y));
if (sig_chain_next.count(y_sig) == 0)
break;
@ -278,28 +278,28 @@ struct MuxpackWorker
pmux_count += 1;
first_cell->type = ID($pmux);
SigSpec b_sig = first_cell->getPort(ID::B);
SigSpec s_sig = first_cell->getPort(ID::S);
SigSpec b_sig = first_cell->getPort(TW::B);
SigSpec s_sig = first_cell->getPort(TW::S);
for (int i = 1; i < cases; i++) {
Cell* prev_cell = chain[cursor+i-1];
Cell* cursor_cell = chain[cursor+i];
if (sigmap(prev_cell->getPort(ID::Y)) == sigmap(cursor_cell->getPort(ID::A))) {
b_sig.append(cursor_cell->getPort(ID::B));
s_sig.append(cursor_cell->getPort(ID::S));
if (sigmap(prev_cell->getPort(TW::Y)) == sigmap(cursor_cell->getPort(TW::A))) {
b_sig.append(cursor_cell->getPort(TW::B));
s_sig.append(cursor_cell->getPort(TW::S));
}
else {
log_assert(cursor_cell->type == ID($mux));
b_sig.append(cursor_cell->getPort(ID::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(ID::S)));
b_sig.append(cursor_cell->getPort(TW::A));
s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort(TW::S)));
}
remove_cells.insert(cursor_cell);
}
first_cell->setPort(ID::B, b_sig);
first_cell->setPort(ID::S, s_sig);
first_cell->setPort(TW::B, b_sig);
first_cell->setPort(TW::S, s_sig);
first_cell->setParam(ID::S_WIDTH, GetSize(s_sig));
first_cell->setPort(ID::Y, last_cell->getPort(ID::Y));
first_cell->setPort(TW::Y, last_cell->getPort(TW::Y));
cursor += cases;
}

26
passes/opt/opt_balance_tree.cc
View file

@ -77,7 +77,7 @@ struct OptBalanceTreeWorker {
// Base case: if we have two sources, create a single cell
if (sources.size() == 2) {
// Create a new cell of the same type
Cell* new_cell = module->addCell(NEW_ID, cell_type);
Cell* new_cell = module->addCell(NEW_TWINE, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
@ -88,12 +88,12 @@ struct OptBalanceTreeWorker {
out_width = max(sources[0].size(), sources[1].size()) + 1;
else if (cell_type == ID($mul))
out_width = sources[0].size() + sources[1].size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
Wire* out_wire = module->addWire(NEW_TWINE, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, sources[0]);
new_cell->setPort(ID::B, sources[1]);
new_cell->setPort(ID::Y, out_wire);
new_cell->setPort(TW::A, sources[0]);
new_cell->setPort(TW::B, sources[1]);
new_cell->setPort(TW::Y, out_wire);
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
@ -112,7 +112,7 @@ struct OptBalanceTreeWorker {
SigSpec right_tree = create_balanced_tree(right_sources, cell_type, cell);
// Create a cell to combine the two subtrees
Cell* new_cell = module->addCell(NEW_ID, cell_type);
Cell* new_cell = module->addCell(NEW_TWINE, cell_type);
// Copy attributes from reference cell
new_cell->attributes = cell->attributes;
@ -123,12 +123,12 @@ struct OptBalanceTreeWorker {
out_width = max(left_tree.size(), right_tree.size()) + 1;
else if (cell_type == ID($mul))
out_width = left_tree.size() + right_tree.size();
Wire* out_wire = module->addWire(NEW_ID, out_width);
Wire* out_wire = module->addWire(NEW_TWINE, out_width);
// Connect ports and fix up parameters
new_cell->setPort(ID::A, left_tree);
new_cell->setPort(ID::B, right_tree);
new_cell->setPort(ID::Y, out_wire);
new_cell->setPort(TW::A, left_tree);
new_cell->setPort(TW::B, right_tree);
new_cell->setPort(TW::Y, out_wire);
new_cell->fixup_parameters();
new_cell->setParam(ID::A_SIGNED, cell->getParam(ID::A_SIGNED));
new_cell->setParam(ID::B_SIGNED, cell->getParam(ID::B_SIGNED));
@ -185,7 +185,7 @@ struct OptBalanceTreeWorker {
// BFS, following all chains until they hit a cell of a different type
// Pick the longest one
auto y = sigmap(cell->getPort(ID::Y));
auto y = sigmap(cell->getPort(TW::Y));
pool<Cell*> sinks;
pool<Cell*> current_loads = sig_to_sink[y];
pool<Cell*> next_loads;
@ -202,7 +202,7 @@ struct OptBalanceTreeWorker {
continue;
}
auto xy = sigmap(x->getPort(ID::Y));
auto xy = sigmap(x->getPort(TW::Y));
// If this signal drives a port, add it to the sinks
// (even though it may not be the end of a chain)
@ -300,7 +300,7 @@ struct OptBalanceTreeWorker {
SigSpec tree_output = create_balanced_tree(source_signals, cell_type, head_cell);
// Connect the tree output to the head cell's output
SigSpec head_output = sigmap(head_cell->getPort(ID::Y));
SigSpec head_output = sigmap(head_cell->getPort(TW::Y));
int connect_width = std::min(head_output.size(), tree_output.size());
module->connect(head_output.extract(0, connect_width), tree_output.extract(0, connect_width));
if (head_output.size() > tree_output.size()) {

6
passes/opt/opt_clean/cells_all.cc
View file

@ -202,7 +202,7 @@ ConflictLogs explore(CellAnalysis& analysis, CellTraversal& traversal, const Sig
if (bit.wire == nullptr && clean_ctx.ct_all.cell_known(cell->type)) {
std::string msg = stringf("Driver-driver conflict "
"for %s between cell %s.%s and constant %s in %s: Resolved using constant.",
log_signal(raw_bit), cell->name.unescape(), it2.first.unescape(), log_signal(bit), actx.mod->name.unescape());
log_signal(raw_bit), cell->name.unescape(), actx.mod->design->twines.str(it2.first), log_signal(bit), actx.mod->name);
logs.logs.insert(ctx, {wire_map(raw_bit), msg});
}
if (bit.wire != nullptr)
@ -304,7 +304,7 @@ pool<Cell*> all_unused_cells(const Module *mod, const CellAnalysis& analysis, Wi
});
for (int cell_index : sharded_unused_cells)
unused_cells.insert(mod->cell_at(cell_index));
unused_cells.sort(RTLIL::sort_by_name_id<RTLIL::Cell>());
unused_cells.sort(RTLIL::sort_by_name<RTLIL::Cell>());
return unused_cells;
}
@ -314,7 +314,7 @@ void remove_cells(RTLIL::Module* mod, FfInitVals& ffinit, const pool<Cell*>& cel
log_debug(" removing unused `%s' cell `%s'.\n", cell->type, cell->name);
mod->design->scratchpad_set_bool("opt.did_something", true);
if (cell->is_builtin_ff())
ffinit.remove_init(cell->getPort(ID::Q));
ffinit.remove_init(cell->getPort(TW::Q));
mod->remove(cell);
stats.count_rm_cells++;
}

18
passes/opt/opt_clean/cells_temp.cc
View file

@ -27,8 +27,8 @@ bool is_signed(RTLIL::Cell* cell) {
}
bool trim_buf(RTLIL::Cell* cell, ShardedVector<RTLIL::SigSig>& new_connections, const ParallelDispatchThreadPool::RunCtx &ctx) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec y = cell->getPort(TW::Y);
a.extend_u0(GetSize(y), is_signed(cell));
if (a.has_const(State::Sz)) {
@ -58,20 +58,20 @@ bool remove(ShardedVector<RTLIL::Cell*>& cells, RTLIL::Module* mod, bool verbose
if (verbose) {
if (cell->type == ID($connect)) {
log_debug(" removing connect cell `%s': %s <-> %s\n", cell->name,
log_signal(cell->getPort(ID::A)), log_signal(cell->getPort(ID::B)));
log_signal(cell->getPort(TW::A)), log_signal(cell->getPort(TW::B)));
} else if (cell->type == ID($input_port)) {
log_debug(" removing input port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::Y)));
log_signal(cell->getPort(TW::Y)));
} else if (cell->type == ID($output_port)) {
log_debug(" removing output port marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::A)));
} else if (cell->type == ID($public)) {
log_debug(" removing public wire marker cell `%s': %s\n", cell->name,
log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::A)));
} else {
did_something = true;
log_debug(" removing buffer cell `%s': %s = %s\n", cell->name,
log_signal(cell->getPort(ID::Y)), log_signal(cell->getPort(ID::A)));
log_signal(cell->getPort(TW::Y)), log_signal(cell->getPort(TW::A)));
}
}
mod->remove(cell);
@ -93,8 +93,8 @@ void remove_temporary_cells(RTLIL::Module *module, ParallelDispatchThreadPool::S
if (trim_buf(cell, new_connections, ctx))
delcells.insert(ctx, cell);
} else if (cell->type.in(ID($connect)) && !cell->has_keep_attr()) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec b = cell->getPort(TW::B);
if (a.has_const() && !b.has_const())
std::swap(a, b);
new_connections.insert(ctx, {a, b});

4
passes/opt/opt_clean/inits.cc
View file

@ -27,9 +27,9 @@ ShardedVector<std::pair<SigBit, State>> build_inits(AnalysisContext& actx) {
actx.subpool.run([&results, &actx](const ParallelDispatchThreadPool::RunCtx &ctx) {
for (int i : ctx.item_range(actx.mod->cells_size())) {
RTLIL::Cell *cell = actx.mod->cell_at(i);
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q))
if (StaticCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(TW::Q))
{
SigSpec sig = cell->getPort(ID::Q);
SigSpec sig = cell->getPort(TW::Q);
for (int i = 0; i < GetSize(sig); i++)
{

4
passes/opt/opt_clean/wires.cc
View file

@ -178,7 +178,7 @@ bool check_all(const ShardedSigPool &sigs, const RTLIL::SigSpec &spec) {
struct UpdateConnection {
RTLIL::Cell *cell;
RTLIL::IdString port;
TwineRef port;
RTLIL::SigSpec spec;
};
void fixup_cell_ports(ShardedVector<UpdateConnection> &update_connections)
@ -256,7 +256,7 @@ struct SigConnKinds {
// see commit message e36c71b5
bool clk2fflogic = cell->get_bool_attribute(ID::clk2fflogic);
for (auto &[port, sig] : cell->connections())
if (clk2fflogic ? port == ID::D : clean_ctx.ct_all.cell_output(cell->type, port))
if (clk2fflogic ? port == TW::D : clean_ctx.ct_all.cell_output(cell->type, port))
add_spec(raw_register_builder, ctx, sig);
}
for (auto &[_, sig] : cell->connections())

14
passes/opt/opt_demorgan.cc
View file

@ -38,7 +38,7 @@ void demorgan_worker(
if( (cell->type != ID($reduce_and)) && (cell->type != ID($reduce_or)) )
return;
auto insig = sigmap(cell->getPort(ID::A));
auto insig = sigmap(cell->getPort(TW::A));
if (GetSize(insig) < 1)
return;
@ -99,7 +99,7 @@ void demorgan_worker(
//We are NOT inverted! Add an inverter
if(!srcinv)
{
auto inverted_b = m->addWire(NEW_ID);
auto inverted_b = m->addWire(NEW_TWINE);
m->addNot(NEW_ID, RTLIL::SigSpec(b), RTLIL::SigSpec(inverted_b));
insig[i] = inverted_b;
}
@ -107,7 +107,7 @@ void demorgan_worker(
//We ARE inverted - bypass it
//Don't automatically delete the inverter since other stuff might still use it
else
insig[i] = srcinv->getPort(ID::A);
insig[i] = srcinv->getPort(TW::A);
}
//Cosmetic fixup: If our input is just a scrambled version of one bus, rearrange it
@ -155,7 +155,7 @@ void demorgan_worker(
}
//Push the new input signal back to the reduction (after bypassing/adding inverters)
cell->setPort(ID::A, insig);
cell->setPort(TW::A, insig);
//Change the cell type
if(cell->type == ID($reduce_and))
@ -165,10 +165,10 @@ void demorgan_worker(
//don't change XOR
//Add an inverter to the output
auto inverted_output = cell->getPort(ID::Y);
auto uninverted_output = m->addWire(NEW_ID);
auto inverted_output = cell->getPort(TW::Y);
auto uninverted_output = m->addWire(NEW_TWINE);
m->addNot(NEW_ID, RTLIL::SigSpec(uninverted_output), inverted_output);
cell->setPort(ID::Y, uninverted_output);
cell->setPort(TW::Y, uninverted_output);
}
struct OptDemorganPass : public Pass {

86
passes/opt/opt_dff.cc
View file

@ -77,29 +77,29 @@ struct OptDffWorker
SigSpec create_not(SigSpec a, bool is_fine) {
if (is_fine)
return module->NotGate(NEW_ID, a);
return module->NotGate(NEW_TWINE, a);
else
return module->Not(NEW_ID, a);
return module->Not(NEW_TWINE, a);
}
SigSpec create_and(SigSpec a, SigSpec b, bool is_fine) {
if (is_fine)
return module->AndGate(NEW_ID, a, b);
return module->AndGate(NEW_TWINE, a, b);
else
return module->And(NEW_ID, a, b);
return module->And(NEW_TWINE, a, b);
}
void create_mux_to_output(SigSpec a, SigSpec b, SigSpec sel, SigSpec y, bool pol, bool is_fine) {
if (is_fine) {
if (pol)
module->addMuxGate(NEW_ID, a, b, sel, y);
module->addMuxGate(NEW_TWINE, a, b, sel, y);
else
module->addMuxGate(NEW_ID, b, a, sel, y);
module->addMuxGate(NEW_TWINE, b, a, sel, y);
} else {
if (pol)
module->addMux(NEW_ID, a, b, sel, y);
module->addMux(NEW_TWINE, a, b, sel, y);
else
module->addMux(NEW_ID, b, a, sel, y);
module->addMux(NEW_TWINE, b, a, sel, y);
}
}
@ -124,7 +124,7 @@ struct OptDffWorker
for (auto cell : module->cells()) {
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_))) {
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(sig_y); i++)
bit2mux[sig_y[i]] = cell_int_t(cell, i);
}
@ -163,9 +163,9 @@ struct OptDffWorker
return ret; // D not driven by MUX / MUX drives multiple loads
cell_int_t mbit = bit2mux.at(d);
RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(ID::S));
RTLIL::SigSpec sig_a = sigmap(mbit.first->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap(mbit.first->getPort(TW::B));
RTLIL::SigSpec sig_s = sigmap(mbit.first->getPort(TW::S));
int width = GetSize(sig_a), index = mbit.second;
// Traverse MUX tree
@ -173,9 +173,9 @@ struct OptDffWorker
if (path.count(sig_s[i]) && path.at(sig_s[i])) {
ret = find_muxtree_feedback_patterns(sig_b[i*width + index], q, path);
if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::B));
s[i*width + index] = RTLIL::Sx;
mbit.first->setPort(ID::B, s);
mbit.first->setPort(TW::B, s);
}
return ret;
@ -197,9 +197,9 @@ struct OptDffWorker
ret.insert(pat);
if (sig_b[i*width + index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::B));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::B));
s[i*width + index] = RTLIL::Sx;
mbit.first->setPort(ID::B, s);
mbit.first->setPort(TW::B, s);
}
}
@ -208,9 +208,9 @@ struct OptDffWorker
ret.insert(pat);
if (sig_a[index] == q) {
RTLIL::SigSpec s = sigmap(mbit.first->getPort(ID::A));
RTLIL::SigSpec s = sigmap(mbit.first->getPort(TW::A));
s[index] = RTLIL::Sx;
mbit.first->setPort(ID::A, s);
mbit.first->setPort(TW::A, s);
}
return ret;
@ -232,8 +232,8 @@ struct OptDffWorker
s2.append(it.second);
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addNe(NEW_ID, s1, s2, y);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = module->addNe(NEW_TWINE, s1, s2, y);
maybe_simplemap(c, make_gates);
or_input.append(y);
}
@ -249,8 +249,8 @@ struct OptDffWorker
if (GetSize(or_input) == 0) return ctrl_t(State::S1, true);
if (GetSize(or_input) == 1) return ctrl_t(or_input, true);
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::Cell *c = module->addReduceAnd(NEW_ID, or_input, y);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = module->addReduceAnd(NEW_TWINE, or_input, y);
maybe_simplemap(c, make_gates);
return ctrl_t(y, true);
}
@ -273,10 +273,10 @@ struct OptDffWorker
or_input.append(create_not(item.first, make_gates));
}
RTLIL::SigSpec y = module->addWire(NEW_ID);
RTLIL::SigSpec y = module->addWire(NEW_TWINE);
RTLIL::Cell *c = final_pol
? module->addReduceOr(NEW_ID, or_input, y)
: module->addReduceAnd(NEW_ID, or_input, y);
? module->addReduceOr(NEW_TWINE, or_input, y)
: module->addReduceAnd(NEW_TWINE, or_input, y);
maybe_simplemap(c, make_gates);
return ctrl_t(y, final_pol);
}
@ -309,9 +309,9 @@ struct OptDffWorker
if (!ff.pol_clr)
module->connect(ff.sig_q[i], ff.sig_clr[i]);
else if (ff.is_fine)
module->addNotGate(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNotGate(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
else
module->addNot(NEW_ID, ff.sig_clr[i], ff.sig_q[i]);
module->addNot(NEW_TWINE, ff.sig_clr[i], ff.sig_q[i]);
log("Handling always-active SET at position %d on %s (%s) from module %s (changing to combinatorial circuit).\n",
i, cell, cell->type.unescape(), module);
sr_removed = true;
@ -406,22 +406,22 @@ struct OptDffWorker
SigSpec tmp;
if (ff.is_fine) {
tmp = ff.pol_set
? module->MuxGate(NEW_ID, ff.sig_ad, State::S1, ff.sig_set)
: module->MuxGate(NEW_ID, State::S1, ff.sig_ad, ff.sig_set);
? module->MuxGate(NEW_TWINE, ff.sig_ad, State::S1, ff.sig_set)
: module->MuxGate(NEW_TWINE, State::S1, ff.sig_ad, ff.sig_set);
if (ff.pol_clr)
module->addMuxGate(NEW_ID, tmp, State::S0, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEW_TWINE, tmp, State::S0, ff.sig_clr, ff.sig_q);
else
module->addMuxGate(NEW_ID, State::S0, tmp, ff.sig_clr, ff.sig_q);
module->addMuxGate(NEW_TWINE, State::S0, tmp, ff.sig_clr, ff.sig_q);
} else {
tmp = ff.pol_set
? module->Or(NEW_ID, ff.sig_ad, ff.sig_set)
: module->Or(NEW_ID, ff.sig_ad, module->Not(NEW_ID, ff.sig_set));
? module->Or(NEW_TWINE, ff.sig_ad, ff.sig_set)
: module->Or(NEW_TWINE, ff.sig_ad, module->Not(NEW_TWINE, ff.sig_set));
if (ff.pol_clr)
module->addAnd(NEW_ID, tmp, module->Not(NEW_ID, ff.sig_clr), ff.sig_q);
module->addAnd(NEW_TWINE, tmp, module->Not(NEW_TWINE, ff.sig_clr), ff.sig_q);
else
module->addAnd(NEW_ID, tmp, ff.sig_clr, ff.sig_q);
module->addAnd(NEW_TWINE, tmp, ff.sig_clr, ff.sig_q);
}
} else if (ff.has_arst) {
create_mux_to_output(ff.sig_ad, ff.val_arst, ff.sig_arst, ff.sig_q, ff.pol_arst, ff.is_fine);
@ -566,12 +566,12 @@ struct OptDffWorker
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
if (GetSize(mbit.first->getPort(ID::S)) != 1)
if (GetSize(mbit.first->getPort(TW::S)) != 1)
break;
SigBit s = sigmap(mbit.first->getPort(ID::S));
SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
SigBit s = sigmap(mbit.first->getPort(TW::S));
SigBit a = sigmap(mbit.first->getPort(TW::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(TW::B)[mbit.second]);
if ((a == State::S0 || a == State::S1) && (b == State::S0 || b == State::S1))
break;
@ -649,12 +649,12 @@ struct OptDffWorker
while (bit2mux.count(ff.sig_d[i]) && bitusers[ff.sig_d[i]] == 1) {
cell_int_t mbit = bit2mux.at(ff.sig_d[i]);
if (GetSize(mbit.first->getPort(ID::S)) != 1)
if (GetSize(mbit.first->getPort(TW::S)) != 1)
break;
SigBit s = sigmap(mbit.first->getPort(ID::S));
SigBit a = sigmap(mbit.first->getPort(ID::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(ID::B)[mbit.second]);
SigBit s = sigmap(mbit.first->getPort(TW::S));
SigBit a = sigmap(mbit.first->getPort(TW::A)[mbit.second]);
SigBit b = sigmap(mbit.first->getPort(TW::B)[mbit.second]);
if (a == ff.sig_q[i]) {
enables.insert(ctrl_t(s, true));

74
passes/opt/opt_expr.cc
View file

@ -243,7 +243,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
continue;
int group_size = GetSize(per_kind[kind]);
RTLIL::SigSpec new_y = patcher.addWire(NEW_ID, group_size);
RTLIL::SigSpec new_y = patcher.addWire(NEW_TWINE, group_size);
RTLIL::SigSpec new_a, new_b;
int slot = 0;
@ -295,9 +295,9 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
else if (new_a[j] == State::S0 || new_a[j] == State::S1) {
undef_a.append(new_a[j]);
if (cell->type == ID($xor))
undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_ID, new_b[j]).as_bit() : new_b[j]);
undef_b.append(new_a[j] == State::S1 ? patcher.Not(NEW_TWINE, new_b[j]).as_bit() : new_b[j]);
else if (cell->type == ID($xnor))
undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_ID, new_b[j]).as_bit());
undef_b.append(new_a[j] == State::S1 ? new_b[j] : patcher.Not(NEW_TWINE, new_b[j]).as_bit());
else log_abort();
undef_y.append(new_y[j]);
}
@ -324,7 +324,7 @@ bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutativ
new_y = std::move(def_y);
}
RTLIL::Cell *c = patcher.addCell(NEW_ID, cell->type);
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
c->setPort(TW::A, new_a);
c->parameters[ID::A_WIDTH] = new_a.size();
@ -687,7 +687,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
sig_y.append(RTLIL::Const(State::S0, width-1));
patcher.patch(cell, TW::Y, sig_y, "xor_buffer");
} else {
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_TWINE, sig_a) : patcher.Not(NEW_TWINE, sig_a);
sig_y.append(RTLIL::Const(State::S0, width-1));
patcher.patch(cell, TW::Y, sig_y, "xor_buffer");
}
@ -699,7 +699,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
sig_y.append(RTLIL::Const(State::S1, width-1));
patcher.patch(cell, TW::Y, sig_y, "xnor_buffer");
} else {
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_ID, sig_a) : patcher.Not(NEW_ID, sig_a);
SigSpec sig_y = is_gate ? (SigSpec)patcher.NotGate(NEW_TWINE, sig_a) : patcher.Not(NEW_TWINE, sig_a);
sig_y.append(RTLIL::Const(State::S1, width-1));
patcher.patch(cell, TW::Y, sig_y, "xnor_buffer");
}
@ -771,7 +771,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!b_group_1.empty()) y_new_1 = b_group_1;
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.And(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.And(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else
y_new_x = Const(State::S0, GetSize(b_group_x));
}
@ -780,16 +780,16 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
if (!b_group_1.empty()) y_new_1 = Const(State::S1, GetSize(b_group_1));
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.Or(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.Or(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else
y_new_x = Const(State::S1, GetSize(b_group_x));
}
} else if (cell->type.in(ID($xor), ID($xnor))) {
if (!b_group_0.empty()) y_new_0 = b_group_0;
if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_ID, b_group_1);
if (!b_group_1.empty()) y_new_1 = patcher.Not(NEW_TWINE, b_group_1);
if (!b_group_x.empty()) {
if (keepdc)
y_new_x = patcher.Xor(NEW_ID, Const(State::Sx, GetSize(b_group_x)), b_group_x);
y_new_x = patcher.Xor(NEW_TWINE, Const(State::Sx, GetSize(b_group_x)), b_group_x);
else // This should be fine even with keepdc, but opt_expr_xor.ys wants to keep the xor
y_new_x = Const(State::Sx, GetSize(b_group_x));
}
@ -849,11 +849,11 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigSpec y_new_0, y_new_1;
if (flip) {
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_ID, b_group_0, patcher.Not(NEW_ID, s_group_0));
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_ID, b_group_1, s_group_1);
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_TWINE, b_group_0, patcher.Not(NEW_TWINE, s_group_0));
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_TWINE, b_group_1, s_group_1);
} else {
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_ID, b_group_0, s_group_0);
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_ID, b_group_1, patcher.Not(NEW_ID, s_group_1));
if (!b_group_0.empty()) y_new_0 = patcher.And(NEW_TWINE, b_group_0, s_group_0);
if (!b_group_1.empty()) y_new_1 = patcher.Or(NEW_TWINE, b_group_1, patcher.Not(NEW_TWINE, s_group_1));
}
RTLIL::SigSpec new_sig_y(width);
@ -1059,12 +1059,12 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
RTLIL::SigBit a = sig_a[i];
if (b == ((bi ^ ci) ? State::S1 : State::S0)) {
module->connect(sig_y[i], a);
module->connect(sig_x[i], ci ? module->Not(NEW_ID, a).as_bit() : a);
module->connect(sig_x[i], ci ? module->Not(NEW_TWINE, a).as_bit() : a);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else if (a == (ci ? State::S1 : State::S0)) {
module->connect(sig_y[i], bi ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_ID, b).as_bit() : b);
module->connect(sig_y[i], bi ? module->Not(NEW_TWINE, b).as_bit() : b);
module->connect(sig_x[i], (bi ^ ci) ? module->Not(NEW_TWINE, b).as_bit() : b);
module->connect(sig_co[i], ci ? State::S1 : State::S0);
}
else
@ -1486,7 +1486,7 @@ skip_fine_alu:
/* sub, b is 0 */
RTLIL::SigSpec a = cell->getPort(TW::A);
a.extend_u0(y_width, is_signed);
new_x = patcher.Not(NEW_ID, a);
new_x = patcher.Not(NEW_TWINE, a);
new_co = RTLIL::Const(State::S1, y_width);
a_port = cell->getPort(TW::A);
a_port_signed = a_signed;
@ -1503,8 +1503,8 @@ skip_fine_alu:
}
IdString new_type = arith_inverse ? ID($neg) : ID($pos);
SigSpec new_y = patcher.addWire(NEW_ID, y_width);
Cell *new_cell = patcher.addCell(NEW_ID, new_type);
SigSpec new_y = patcher.addWire(NEW_TWINE, y_width);
Cell *new_cell = patcher.addCell(NEW_TWINE, new_type);
new_cell->setPort(TW::A, a_port);
new_cell->setPort(TW::Y, new_y);
new_cell->setParam(ID::A_WIDTH, a_port_width);
@ -1805,8 +1805,8 @@ skip_identity:
OptExprPatcher patcher(module, &assign_map);
int a_width = cell->parameters[ID::A_WIDTH].as_int();
SigSpec y_wire = patcher.addWire(NEW_ID, y_size);
Cell *mul = patcher.addCell(NEW_ID, ID($mul));
SigSpec y_wire = patcher.addWire(NEW_TWINE, y_size);
Cell *mul = patcher.addCell(NEW_TWINE, ID($mul));
mul->setPort(TW::A, Const(bit_idx, a_width));
mul->setPort(TW::B, cell->getPort(TW::B));
mul->setPort(TW::Y, y_wire);
@ -1816,8 +1816,8 @@ skip_identity:
mul->parameters[ID::B_SIGNED] = cell->parameters[ID::B_SIGNED];
mul->parameters[ID::Y_WIDTH] = y_size;
SigSpec new_y = patcher.addWire(NEW_ID, y_size);
patcher.addShl(NEW_ID, Const(State::S1, 1), y_wire, new_y);
SigSpec new_y = patcher.addWire(NEW_TWINE, y_size);
patcher.addShl(NEW_TWINE, Const(State::S1, 1), y_wire, new_y);
patcher.patch(cell, TW::Y, new_y, "pow_to_mul_shl");
goto next_cell;
@ -1954,13 +1954,13 @@ skip_identity:
// Truncating division is the same as flooring division, except when
// the result is negative and there is a remainder - then trunc = floor + 1
if (is_truncating && a_signed && GetSize(sig_a) != 0 && exp != 0) {
Wire *flooring = module->addWire(NEW_ID, sig_y.size());
Wire *flooring = module->addWire(NEW_TWINE, sig_y.size());
cell->setPort(TW::Y, flooring);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = module->ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_ID, a_sign, rem_nonzero);
module->addAdd(NEW_ID, flooring, should_add, sig_y);
SigSpec rem_nonzero = module->ReduceOr(NEW_TWINE, sig_a.extract(0, exp));
SigSpec should_add = module->And(NEW_TWINE, a_sign, rem_nonzero);
module->addAdd(NEW_TWINE, flooring, should_add, sig_y);
}
cell->check();
@ -1980,8 +1980,8 @@ skip_identity:
SigSpec truncating = sig_a.extract(0, exp);
SigSpec a_sign = sig_a[sig_a.size()-1];
SigSpec rem_nonzero = patcher.ReduceOr(NEW_ID, sig_a.extract(0, exp));
SigSpec extend_bit = patcher.And(NEW_ID, a_sign, rem_nonzero);
SigSpec rem_nonzero = patcher.ReduceOr(NEW_TWINE, sig_a.extract(0, exp));
SigSpec extend_bit = patcher.And(NEW_TWINE, a_sign, rem_nonzero);
truncating.append(extend_bit);
SigSpec new_y = truncating;
@ -2071,11 +2071,11 @@ skip_identity:
int sz = cur - prev;
bool last = cur == GetSize(sig_y);
SigSpec slice_y = patcher.addWire(NEW_ID, sz);
SigSpec slice_x = patcher.addWire(NEW_ID, sz);
SigSpec slice_co = patcher.addWire(NEW_ID, sz);
SigSpec slice_y = patcher.addWire(NEW_TWINE, sz);
SigSpec slice_x = patcher.addWire(NEW_TWINE, sz);
SigSpec slice_co = patcher.addWire(NEW_TWINE, sz);
RTLIL::Cell *c = patcher.addCell(NEW_ID, cell->type);
RTLIL::Cell *c = patcher.addCell(NEW_TWINE, cell->type);
c->setPort(TW::A, sig_a.extract(prev, sz));
c->setPort(TW::B, sig_b.extract(prev, sz));
c->setPort(TW::BI, sig_bi);
@ -2248,14 +2248,14 @@ skip_alu_split:
{
condition = stringf("unsigned X<%s", log_signal(const_sig));
replacement = stringf("!X[%d:%d]", var_width - 1, const_bit_hot);
replace_sig[0] = patcher.LogicNot(NEW_ID, var_high_sig).as_bit();
replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_high_sig).as_bit();
replace = true;
}
if (cmp_type == ID($ge))
{
condition = stringf("unsigned X>=%s", log_signal(const_sig));
replacement = stringf("|X[%d:%d]", var_width - 1, const_bit_hot);
replace_sig[0] = patcher.ReduceOr(NEW_ID, var_high_sig).as_bit();
replace_sig[0] = patcher.ReduceOr(NEW_TWINE, var_high_sig).as_bit();
replace = true;
}
}
@ -2297,7 +2297,7 @@ skip_alu_split:
{
condition = "signed X>=0";
replacement = stringf("X[%d]", var_width - 1);
replace_sig[0] = patcher.LogicNot(NEW_ID, var_sig[var_width - 1]).as_bit();
replace_sig[0] = patcher.LogicNot(NEW_TWINE, var_sig[var_width - 1]).as_bit();
replace = true;
}
}

14
passes/opt/opt_ffinv.cc
View file

@ -84,12 +84,12 @@ struct OptFfInvWorker
}
ff.flip_rst_bits({0});
ff.sig_d = d_inv->getPort(ID::A);
ff.sig_d = d_inv->getPort(TW::A);
for (Cell *lut: q_luts) {
if (lut->type == ID($lut)) {
int flip_mask = 0;
SigSpec sig_a = lut->getPort(ID::A);
SigSpec sig_a = lut->getPort(TW::A);
for (int i = 0; i < GetSize(sig_a); i++) {
if (index.sigmap(sig_a[i]) == index.sigmap(ff.sig_q[0])) {
flip_mask |= 1 << i;
@ -101,14 +101,14 @@ struct OptFfInvWorker
new_mask_builder.push_back(mask[j ^ flip_mask]);
Const new_mask = new_mask_builder.build();
if (GetSize(sig_a) == 1 && new_mask.as_int() == 2) {
module->connect(lut->getPort(ID::Y), ff.sig_q);
module->connect(lut->getPort(TW::Y), ff.sig_q);
module->remove(lut);
} else {
lut->setParam(ID::LUT, new_mask);
}
} else {
// it was an inverter
module->connect(lut->getPort(ID::Y), ff.sig_q);
module->connect(lut->getPort(TW::Y), ff.sig_q);
module->remove(lut);
}
}
@ -173,7 +173,7 @@ struct OptFfInvWorker
if (!q_inv) return false;
ff.flip_rst_bits({0});
ff.sig_q = q_inv->getPort(ID::Y);
ff.sig_q = q_inv->getPort(TW::Y);
module->remove(q_inv);
if (d_lut->type == ID($lut)) {
@ -188,12 +188,12 @@ struct OptFfInvWorker
Const new_mask = new_mask_builder.build();
d_lut->setParam(ID::LUT, new_mask);
if (d_lut->getParam(ID::WIDTH) == 1 && new_mask.as_int() == 2) {
module->connect(ff.sig_d, d_lut->getPort(ID::A));
module->connect(ff.sig_d, d_lut->getPort(TW::A));
module->remove(d_lut);
}
} else {
// it was an inverter
module->connect(ff.sig_d, d_lut->getPort(ID::A));
module->connect(ff.sig_d, d_lut->getPort(TW::A));
module->remove(d_lut);
}

4
passes/opt/opt_hier.cc
View file

@ -137,7 +137,7 @@ struct ModuleIndex {
rhs.replace(constant_outputs);
log_assert(rhs.is_fully_const());
parent.module->connect(value.extract(chunk.offset, chunk.width), rhs);
SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("const_output"), chunk.width);
SigSpec dummy = parent.module->addWire(NEW_TWINE_SUFFIX("const_output"), chunk.width);
for (int i = 0; i < chunk.width; i++)
value[chunk.offset + i] = dummy[i];
}
@ -182,7 +182,7 @@ struct ModuleIndex {
severed_port_bits.sort_and_unify();
for (auto chunk : severed_port_bits.chunks()) {
SigSpec &value = instantiation->connections_.at(chunk.wire->name);
SigSpec dummy = parent.module->addWire(NEW_ID_SUFFIX("tie_together"), chunk.width);
SigSpec dummy = parent.module->addWire(NEW_TWINE_SUFFIX("tie_together"), chunk.width);
for (int i = 0; i < chunk.width; i++)
value[chunk.offset + i] = dummy[i];
}

28
passes/opt/opt_lut.cc
View file

@ -50,7 +50,7 @@ struct OptLutWorker
bool evaluate_lut(RTLIL::Cell *lut, dict<SigBit, bool> inputs)
{
SigSpec lut_input = sigmap(lut->getPort(ID::A));
SigSpec lut_input = sigmap(lut->getPort(TW::A));
int lut_width = lut->getParam(ID::WIDTH).as_int();
Const lut_table = lut->getParam(ID::LUT);
int lut_index = 0;
@ -113,12 +113,12 @@ struct OptLutWorker
{
if (cell->has_keep_attr())
continue;
SigBit lut_output = cell->getPort(ID::Y);
SigBit lut_output = cell->getPort(TW::Y);
if (lut_output.wire->get_bool_attribute(ID::keep))
continue;
int lut_width = cell->getParam(ID::WIDTH).as_int();
SigSpec lut_input = cell->getPort(ID::A);
SigSpec lut_input = cell->getPort(TW::A);
int lut_arity = 0;
log_debug("Found $lut\\WIDTH=%d cell %s.%s.\n", lut_width, module, cell);
@ -218,7 +218,7 @@ struct OptLutWorker
}
auto lut = worklist.pop();
SigSpec lut_input = sigmap(lut->getPort(ID::A));
SigSpec lut_input = sigmap(lut->getPort(TW::A));
pool<int> &lut_dlogic_inputs = luts_dlogic_inputs[lut];
vector<SigBit> lut_inputs;
@ -280,7 +280,7 @@ struct OptLutWorker
log_debug(" Not eliminating cell (connected to dedicated logic).\n");
else
{
SigSpec lut_output = lut->getPort(ID::Y);
SigSpec lut_output = lut->getPort(TW::Y);
for (auto &port : index.query_ports(lut_output))
{
if (port.cell != lut && luts.count(port.cell))
@ -317,13 +317,13 @@ struct OptLutWorker
}
auto lutA = worklist.pop();
SigSpec lutA_input = sigmap(lutA->getPort(ID::A));
SigBit lutA_output = sigmap(lutA->getPort(ID::Y)[0]);
SigSpec lutA_input = sigmap(lutA->getPort(TW::A));
SigBit lutA_output = sigmap(lutA->getPort(TW::Y)[0]);
int lutA_width = lutA->getParam(ID::WIDTH).as_int();
int lutA_arity = luts_arity[lutA];
pool<int> &lutA_dlogic_inputs = luts_dlogic_inputs[lutA];
auto lutA_output_ports = index.query_ports(lutA->getPort(ID::Y));
auto lutA_output_ports = index.query_ports(lutA->getPort(TW::Y));
if (lutA_output_ports.size() != 2)
continue;
@ -335,15 +335,15 @@ struct OptLutWorker
if (luts.count(port.cell))
{
auto lutB = port.cell;
SigSpec lutB_input = sigmap(lutB->getPort(ID::A));
SigSpec lutB_output = sigmap(lutB->getPort(ID::Y)[0]);
SigSpec lutB_input = sigmap(lutB->getPort(TW::A));
SigSpec lutB_output = sigmap(lutB->getPort(TW::Y)[0]);
int lutB_width = lutB->getParam(ID::WIDTH).as_int();
int lutB_arity = luts_arity[lutB];
pool<int> &lutB_dlogic_inputs = luts_dlogic_inputs[lutB];
log_debug("Found %s.%s (cell A) feeding %s.%s (cell B).\n", module, lutA, module, lutB);
if (index.query_is_output(lutA->getPort(ID::Y)))
if (index.query_is_output(lutA->getPort(TW::Y)))
{
log_debug(" Not combining LUTs (cascade connection feeds module output).\n");
continue;
@ -453,7 +453,7 @@ struct OptLutWorker
}
int lutM_width = lutM->getParam(ID::WIDTH).as_int();
SigSpec lutM_input = sigmap(lutM->getPort(ID::A));
SigSpec lutM_input = sigmap(lutM->getPort(TW::A));
std::vector<SigBit> lutM_new_inputs;
for (int i = 0; i < lutM_width; i++)
{
@ -499,8 +499,8 @@ struct OptLutWorker
log_debug(" Merged truth table: %s.\n", lutM_new_table.as_string());
lutM->setParam(ID::LUT, lutM_new_table);
lutM->setPort(ID::A, lutM_new_inputs);
lutM->setPort(ID::Y, lutB_output);
lutM->setPort(TW::A, lutM_new_inputs);
lutM->setPort(TW::Y, lutB_output);
luts_arity[lutM] = lutM_arity;
luts.erase(lutR);

26
passes/opt/opt_lut_ins.cc
View file

@ -79,8 +79,8 @@ struct OptLutInsPass : public Pass {
if (techname == "") {
if (cell->type != ID($lut))
continue;
inputs = cell->getPort(ID::A);
output = cell->getPort(ID::Y);
inputs = cell->getPort(TW::A);
output = cell->getPort(TW::Y);
lut = cell->getParam(ID::LUT);
} else if (techname == "xilinx" || techname == "gowin" || techname == "analogdevices") {
if (cell->type == ID(LUT1)) {
@ -128,16 +128,16 @@ struct OptLutInsPass : public Pass {
}
lut = cell->getParam(ID::INIT);
if (techname == "xilinx" || techname == "analogdevices")
output = cell->getPort(ID::O);
output = cell->getPort(TW::O);
else
output = cell->getPort(ID::F);
output = cell->getPort(TW::F);
} else if (techname == "lattice") {
if (cell->type == ID(LUT4)) {
inputs = {
cell->getPort(ID::A),
cell->getPort(ID::B),
cell->getPort(ID::C),
cell->getPort(ID::D),
cell->getPort(TW::A),
cell->getPort(TW::B),
cell->getPort(TW::C),
cell->getPort(TW::D),
};
lut = cell->getParam(ID::INIT);
output = cell->getPort(ID(Z));
@ -226,14 +226,14 @@ struct OptLutInsPass : public Pass {
if (techname == "") {
cell->setParam(ID::LUT, new_lut);
cell->setParam(ID::WIDTH, GetSize(new_inputs));
cell->setPort(ID::A, new_inputs);
cell->setPort(TW::A, new_inputs);
} else if (techname == "lattice" || techname == "ecp5") {
log_assert(GetSize(new_inputs) == 4);
cell->setParam(ID::INIT, new_lut);
cell->setPort(ID::A, new_inputs[0]);
cell->setPort(ID::B, new_inputs[1]);
cell->setPort(ID::C, new_inputs[2]);
cell->setPort(ID::D, new_inputs[3]);
cell->setPort(TW::A, new_inputs[0]);
cell->setPort(TW::B, new_inputs[1]);
cell->setPort(TW::C, new_inputs[2]);
cell->setPort(TW::D, new_inputs[3]);
} else {
// xilinx, gowin
cell->setParam(ID::INIT, new_lut);

18
passes/opt/opt_mem_feedback.cc
View file

@ -75,10 +75,10 @@ struct OptMemFeedbackWorker
RTLIL::Cell *cell = sig_to_mux.at(sig).first;
int bit_idx = sig_to_mux.at(sig).second;
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(ID::B));
std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(ID::S));
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
std::vector<RTLIL::SigBit> sig_a = sigmap(cell->getPort(TW::A));
std::vector<RTLIL::SigBit> sig_b = sigmap(cell->getPort(TW::B));
std::vector<RTLIL::SigBit> sig_s = sigmap(cell->getPort(TW::S));
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(TW::Y));
log_assert(sig_y.at(bit_idx) == sig);
for (int i = 0; i < GetSize(sig_s); i++)
@ -295,18 +295,18 @@ struct OptMemFeedbackWorker
{
if (cell->type == ID($mux))
{
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(ID::B));
RTLIL::SigSpec sig_a = sigmap_xmux(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = sigmap_xmux(cell->getPort(TW::B));
if (sig_a.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_b);
sigmap_xmux.add(cell->getPort(TW::Y), sig_b);
else if (sig_b.is_fully_undef())
sigmap_xmux.add(cell->getPort(ID::Y), sig_a);
sigmap_xmux.add(cell->getPort(TW::Y), sig_a);
}
if (cell->type.in(ID($mux), ID($pmux)))
{
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(ID::Y));
std::vector<RTLIL::SigBit> sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < int(sig_y.size()); i++)
sig_to_mux[sig_y[i]] = std::pair<RTLIL::Cell*, int>(cell, i);
}

2
passes/opt/opt_merge.cc
View file

@ -298,7 +298,7 @@ struct OptMergeWorker
for (auto [remove_cell, keep_cell] : cell_ptrs)
{
log_debug(" Cell `%s' is identical to cell `%s'.\n", remove_cell->name, keep_cell->name);
std::vector<std::pair<RTLIL::IdString, RTLIL::SigSpec>> port_replacements;
std::vector<std::pair<TwineRef, RTLIL::SigSpec>> port_replacements;
for (auto &it : remove_cell->connections()) {
if (remove_cell->output(it.first)) {
RTLIL::SigSpec keep_sig = keep_cell->getPort(it.first);

50
passes/opt/opt_merge_common.h
View file

@ -64,10 +64,10 @@ struct CellHasher
return comm.hash_into(h);
}
static void sort_pmux_conn(dict<RTLIL::IdString, RTLIL::SigSpec> &conn)
static void sort_pmux_conn(dict<TwineRef, RTLIL::SigSpec> &conn)
{
const SigSpec &sig_s = conn.at(ID::S);
const SigSpec &sig_b = conn.at(ID::B);
const SigSpec &sig_s = conn.at(TW::S);
const SigSpec &sig_b = conn.at(TW::B);
int s_width = GetSize(sig_s);
int width = GetSize(sig_b) / s_width;
@ -78,12 +78,12 @@ struct CellHasher
std::sort(sb_pairs.begin(), sb_pairs.end());
conn[ID::S] = SigSpec();
conn[ID::B] = SigSpec();
conn[TW::S] = SigSpec();
conn[TW::B] = SigSpec();
for (auto &it : sb_pairs) {
conn[ID::S].append(it.first);
conn[ID::B].append(it.second);
conn[TW::S].append(it.first);
conn[TW::B].append(it.second);
}
}
@ -94,22 +94,22 @@ struct CellHasher
if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
hashlib::commutative_hash comm;
comm.eat(map_sig(cell->getPort(ID::A)));
comm.eat(map_sig(cell->getPort(ID::B)));
comm.eat(map_sig(cell->getPort(TW::A)));
comm.eat(map_sig(cell->getPort(TW::B)));
h = comm.hash_into(h);
} else if (cell->type.in(ID($reduce_xor), ID($reduce_xnor))) {
SigSpec a = map_sig(cell->getPort(ID::A));
SigSpec a = map_sig(cell->getPort(TW::A));
a.sort();
h = a.hash_into(h);
} else if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
SigSpec a = map_sig(cell->getPort(ID::A));
SigSpec a = map_sig(cell->getPort(TW::A));
a.sort_and_unify();
h = a.hash_into(h);
} else if (cell->type == ID($pmux)) {
SigSpec sig_s = map_sig(cell->getPort(ID::S));
SigSpec sig_b = map_sig(cell->getPort(ID::B));
SigSpec sig_s = map_sig(cell->getPort(TW::S));
SigSpec sig_b = map_sig(cell->getPort(TW::B));
h = hash_pmux_in(sig_s, sig_b, h);
h = map_sig(cell->getPort(ID::A)).hash_into(h);
h = map_sig(cell->getPort(TW::A)).hash_into(h);
} else {
hashlib::commutative_hash comm;
for (const auto& [port, sig] : cell->connections()) {
@ -119,7 +119,7 @@ struct CellHasher
}
h = comm.hash_into(h);
if (cell->is_builtin_ff())
h = initvals(cell->getPort(ID::Q)).hash_into(h);
h = initvals(cell->getPort(TW::Q)).hash_into(h);
}
return h;
}
@ -160,7 +160,7 @@ struct CellHasher
for (const auto &it : cell1->connections_) {
if (cell1->output(it.first)) {
if (it.first == ID::Q && cell1->is_builtin_ff()) {
if (it.first == TW::Q && cell1->is_builtin_ff()) {
// For the 'Q' output of state elements,
// use the (* init *) attribute value
conn1[it.first] = initvals(it.second);
@ -179,20 +179,20 @@ struct CellHasher
if (cell1->type.in(ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul),
ID($logic_and), ID($logic_or), ID($_AND_), ID($_OR_), ID($_XOR_))) {
if (conn1.at(ID::A) < conn1.at(ID::B)) {
std::swap(conn1[ID::A], conn1[ID::B]);
if (conn1.at(TW::A) < conn1.at(TW::B)) {
std::swap(conn1[TW::A], conn1[TW::B]);
}
if (conn2.at(ID::A) < conn2.at(ID::B)) {
std::swap(conn2[ID::A], conn2[ID::B]);
if (conn2.at(TW::A) < conn2.at(TW::B)) {
std::swap(conn2[TW::A], conn2[TW::B]);
}
} else
if (cell1->type.in(ID($reduce_xor), ID($reduce_xnor))) {
conn1[ID::A].sort();
conn2[ID::A].sort();
conn1[TW::A].sort();
conn2[TW::A].sort();
} else
if (cell1->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool))) {
conn1[ID::A].sort_and_unify();
conn2[ID::A].sort_and_unify();
conn1[TW::A].sort_and_unify();
conn2[TW::A].sort_and_unify();
} else
if (cell1->type == ID($pmux)) {
sort_pmux_conn(conn1);
@ -207,7 +207,7 @@ struct CellHasher
if (!cell->is_builtin_ff())
return false;
return !initvals(cell->getPort(ID::Q)).is_fully_def();
return !initvals(cell->getPort(TW::Q)).is_fully_def();
}
};

2
passes/opt/opt_merge_inc.cc
View file

@ -268,7 +268,7 @@ struct OptMergeIncWorker
did_something = true;
log_debug(" Cell `%s' is identical to cell `%s'.\n", cell->name, other_cell->name);
std::vector<std::pair<RTLIL::IdString, RTLIL::SigSpec>> port_replacements;
std::vector<std::pair<TwineRef, RTLIL::SigSpec>> port_replacements;
for (auto &[port, sig] : cell->connections()) {
if (cell->output(port)) {
// TODO why was this removed before?

28
passes/opt/opt_muxtree.cc
View file

@ -113,10 +113,10 @@ struct OptMuxtreeWorker
// .input_sigs
// .const_activated
// .const_deactivated
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
muxinfo_t muxinfo;
muxinfo.cell = cell;
@ -300,10 +300,10 @@ struct OptMuxtreeWorker
continue;
}
RTLIL::SigSpec sig_a = mi.cell->getPort(ID::A);
RTLIL::SigSpec sig_b = mi.cell->getPort(ID::B);
RTLIL::SigSpec sig_s = mi.cell->getPort(ID::S);
RTLIL::SigSpec sig_y = mi.cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = mi.cell->getPort(TW::A);
RTLIL::SigSpec sig_b = mi.cell->getPort(TW::B);
RTLIL::SigSpec sig_s = mi.cell->getPort(TW::S);
RTLIL::SigSpec sig_y = mi.cell->getPort(TW::Y);
RTLIL::SigSpec sig_ports = sig_b;
sig_ports.append(sig_a);
@ -328,9 +328,9 @@ struct OptMuxtreeWorker
}
}
mi.cell->setPort(ID::A, new_sig_a);
mi.cell->setPort(ID::B, new_sig_b);
mi.cell->setPort(ID::S, new_sig_s);
mi.cell->setPort(TW::A, new_sig_a);
mi.cell->setPort(TW::B, new_sig_b);
mi.cell->setPort(TW::S, new_sig_s);
if (GetSize(new_sig_s) == 1) {
mi.cell->type = ID($mux);
mi.cell->parameters.erase(ID::S_WIDTH);
@ -465,7 +465,7 @@ struct OptMuxtreeWorker
deactivate_port(knowledge, port_idx, muxinfo);
}
void replace_known(knowledge_t &knowledge, muxinfo_t &muxinfo, IdString portname)
void replace_known(knowledge_t &knowledge, muxinfo_t &muxinfo, TwineRef portname)
{
SigSpec sig = muxinfo.cell->getPort(portname);
bool did_something = false;
@ -473,8 +473,8 @@ struct OptMuxtreeWorker
int width_if_b = 0;
idict<int> ctrl_bits;
if (portname == ID::B)
width_if_b = GetSize(muxinfo.cell->getPort(ID::A));
for (int bit : sig2bits(muxinfo.cell->getPort(ID::S), false))
width_if_b = GetSize(muxinfo.cell->getPort(TW::A));
for (int bit : sig2bits(muxinfo.cell->getPort(TW::S), false))
ctrl_bits(bit);
int slice_idx = 0, slice_off = 0;

128
passes/opt/opt_reduce.cc
View file

@ -43,7 +43,7 @@ struct OptReduceWorker
return;
cells.erase(cell);
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
sig_a.sort_and_unify();
pool<RTLIL::SigBit> new_sig_a_bits;
@ -74,8 +74,8 @@ struct OptReduceWorker
for (auto child_cell : drivers.find(bit)) {
if (child_cell->type == cell->type) {
opt_reduce(cells, drivers, child_cell);
if (child_cell->getPort(ID::Y)[0] == bit) {
pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(ID::A)).to_sigbit_pool();
if (child_cell->getPort(TW::Y)[0] == bit) {
pool<RTLIL::SigBit> child_sig_a_bits = assign_map(child_cell->getPort(TW::A)).to_sigbit_pool();
new_sig_a_bits.insert(child_sig_a_bits.begin(), child_sig_a_bits.end());
} else
new_sig_a_bits.insert(RTLIL::State::S0);
@ -92,22 +92,22 @@ struct OptReduceWorker
if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(TW::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_a));
did_something = true;
total_count++;
}
cell->setPort(ID::A, new_sig_a);
cell->setPort(TW::A, new_sig_a);
cell->parameters[ID::A_WIDTH] = RTLIL::Const(new_sig_a.size());
return;
}
void opt_pmux(RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S));
RTLIL::SigSpec new_sig_b, new_sig_s;
dict<RTLIL::SigSpec, std::vector<RTLIL::SigBit>> grouped_b_to_s;
@ -126,15 +126,15 @@ struct OptReduceWorker
RTLIL::SigSpec this_s{this_s_bit};
if (this_s.size() > 1)
{
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_ID, ID($reduce_or));
reduce_or_cell->setPort(ID::A, this_s);
RTLIL::Cell *reduce_or_cell = module->addCell(NEW_TWINE, ID($reduce_or));
reduce_or_cell->setPort(TW::A, this_s);
reduce_or_cell->parameters[ID::A_SIGNED] = RTLIL::Const(0);
reduce_or_cell->parameters[ID::A_WIDTH] = RTLIL::Const(this_s.size());
reduce_or_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_ID);
RTLIL::Wire *reduce_or_wire = module->addWire(NEW_TWINE);
this_s = RTLIL::SigSpec(reduce_or_wire);
reduce_or_cell->setPort(ID::Y, this_s);
reduce_or_cell->setPort(TW::Y, this_s);
}
new_sig_b.append(this_b);
@ -143,8 +143,8 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
module->connect(cell->getPort(ID::Y), cell->getPort(ID::A));
assign_map.add(cell->getPort(ID::Y), cell->getPort(ID::A));
module->connect(cell->getPort(TW::Y), cell->getPort(TW::A));
assign_map.add(cell->getPort(TW::Y), cell->getPort(TW::A));
module->remove(cell);
did_something = true;
total_count++;
@ -155,8 +155,8 @@ struct OptReduceWorker
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::B, new_sig_b);
cell->setPort(ID::S, new_sig_s);
cell->setPort(TW::B, new_sig_b);
cell->setPort(TW::S, new_sig_s);
if (new_sig_s.size() > 1) {
cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
} else {
@ -168,8 +168,8 @@ struct OptReduceWorker
void opt_bmux(RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_a = assign_map(cell->getPort(TW::A));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S));
int width = cell->getParam(ID::WIDTH).as_int();
RTLIL::SigSpec new_sig_a, new_sig_s;
@ -218,8 +218,8 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
module->connect(cell->getPort(ID::Y), new_sig_a);
assign_map.add(cell->getPort(ID::Y), new_sig_a);
module->connect(cell->getPort(TW::Y), new_sig_a);
assign_map.add(cell->getPort(TW::Y), new_sig_a);
module->remove(cell);
did_something = true;
total_count++;
@ -229,9 +229,9 @@ struct OptReduceWorker
if (new_sig_s.size() == 1)
{
cell->type = ID($mux);
cell->setPort(ID::A, new_sig_a.extract(0, width));
cell->setPort(ID::B, new_sig_a.extract(width, width));
cell->setPort(ID::S, new_sig_s);
cell->setPort(TW::A, new_sig_a.extract(0, width));
cell->setPort(TW::B, new_sig_a.extract(width, width));
cell->setPort(TW::S, new_sig_s);
cell->parameters.erase(ID::S_WIDTH);
did_something = true;
total_count++;
@ -242,16 +242,16 @@ struct OptReduceWorker
log(" New ctrl vector for %s cell %s: %s\n", cell->type, cell->name, log_signal(new_sig_s));
did_something = true;
total_count++;
cell->setPort(ID::A, new_sig_a);
cell->setPort(ID::S, new_sig_s);
cell->setPort(TW::A, new_sig_a);
cell->setPort(TW::S, new_sig_s);
cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
}
}
void opt_demux(RTLIL::Cell *cell)
{
RTLIL::SigSpec sig_y = assign_map(cell->getPort(ID::Y));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(ID::S));
RTLIL::SigSpec sig_y = assign_map(cell->getPort(TW::Y));
RTLIL::SigSpec sig_s = assign_map(cell->getPort(TW::S));
int width = cell->getParam(ID::WIDTH).as_int();
RTLIL::SigSpec new_sig_y, new_sig_s;
@ -319,27 +319,27 @@ struct OptReduceWorker
if (new_sig_s.size() == 0)
{
module->connect(new_sig_y, cell->getPort(ID::A));
assign_map.add(new_sig_y, cell->getPort(ID::A));
module->connect(new_sig_y, cell->getPort(TW::A));
assign_map.add(new_sig_y, cell->getPort(TW::A));
module->remove(cell);
}
else
{
cell->setPort(ID::S, new_sig_s);
cell->setPort(ID::Y, new_sig_y);
cell->setPort(TW::S, new_sig_s);
cell->setPort(TW::Y, new_sig_y);
cell->parameters[ID::S_WIDTH] = RTLIL::Const(new_sig_s.size());
}
}
bool opt_mux_bits(RTLIL::Cell *cell)
{
SigSpec sig_a = assign_map(cell->getPort(ID::A));
SigSpec sig_a = assign_map(cell->getPort(TW::A));
SigSpec sig_b;
SigSpec sig_y = assign_map(cell->getPort(ID::Y));
SigSpec sig_y = assign_map(cell->getPort(TW::Y));
int width = GetSize(sig_y);
if (cell->type != ID($bmux))
sig_b = assign_map(cell->getPort(ID::B));
sig_b = assign_map(cell->getPort(TW::B));
RTLIL::SigSig old_sig_conn;
@ -387,11 +387,11 @@ struct OptReduceWorker
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
if (cell->type != ID($bmux)) {
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
log(" Old ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
} else {
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::Y)));
}
if (swizzle.empty()) {
@ -401,29 +401,29 @@ struct OptReduceWorker
for (int i = 0; i < GetSize(sig_a); i += width)
for (int j: swizzle)
new_sig_a.append(sig_a[i+j]);
cell->setPort(ID::A, new_sig_a);
cell->setPort(TW::A, new_sig_a);
if (cell->type != ID($bmux)) {
SigSpec new_sig_b;
for (int i = 0; i < GetSize(sig_b); i += width)
for (int j: swizzle)
new_sig_b.append(sig_b[i+j]);
cell->setPort(ID::B, new_sig_b);
cell->setPort(TW::B, new_sig_b);
}
SigSpec new_sig_y;
for (int j: swizzle)
new_sig_y.append(sig_y[j]);
cell->setPort(ID::Y, new_sig_y);
cell->setPort(TW::Y, new_sig_y);
cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
if (cell->type != ID($bmux)) {
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::B)), log_signal(cell->getPort(ID::Y)));
log(" New ports: A=%s, B=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::B)), log_signal(cell->getPort(TW::Y)));
} else {
log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::Y)));
}
}
@ -437,8 +437,8 @@ struct OptReduceWorker
}
bool opt_demux_bits(RTLIL::Cell *cell) {
SigSpec sig_a = assign_map(cell->getPort(ID::A));
SigSpec sig_y = assign_map(cell->getPort(ID::Y));
SigSpec sig_a = assign_map(cell->getPort(TW::A));
SigSpec sig_y = assign_map(cell->getPort(TW::Y));
int width = GetSize(sig_a);
RTLIL::SigSig old_sig_conn;
@ -477,8 +477,8 @@ struct OptReduceWorker
if (GetSize(swizzle) != width)
{
log(" Consolidated identical input bits for %s cell %s:\n", cell->type, cell->name);
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
log(" Old ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::Y)));
if (swizzle.empty()) {
module->remove(cell);
@ -486,18 +486,18 @@ struct OptReduceWorker
SigSpec new_sig_a;
for (int j: swizzle)
new_sig_a.append(sig_a[j]);
cell->setPort(ID::A, new_sig_a);
cell->setPort(TW::A, new_sig_a);
SigSpec new_sig_y;
for (int i = 0; i < GetSize(sig_y); i += width)
for (int j: swizzle)
new_sig_y.append(sig_y[i+j]);
cell->setPort(ID::Y, new_sig_y);
cell->setPort(TW::Y, new_sig_y);
cell->parameters[ID::WIDTH] = RTLIL::Const(GetSize(swizzle));
log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(ID::A)),
log_signal(cell->getPort(ID::Y)));
log(" New ports: A=%s, Y=%s\n", log_signal(cell->getPort(TW::A)),
log_signal(cell->getPort(TW::Y)));
}
log(" New connections: %s = %s\n", log_signal(old_sig_conn.first), log_signal(old_sig_conn.second));
@ -521,14 +521,14 @@ struct OptReduceWorker
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type.in(ID($mem), ID($mem_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(ID::WR_EN)));
mem_wren_sigs.add(assign_map(cell->getPort(TW::WR_EN)));
if (cell->type.in(ID($memwr), ID($memwr_v2)))
mem_wren_sigs.add(assign_map(cell->getPort(ID::EN)));
mem_wren_sigs.add(assign_map(cell->getPort(TW::EN)));
}
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Q))))
mem_wren_sigs.add(assign_map(cell->getPort(ID::D)));
if (cell->type == ID($dff) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Q))))
mem_wren_sigs.add(assign_map(cell->getPort(TW::D)));
}
bool keep_expanding_mem_wren_sigs = true;
@ -536,12 +536,12 @@ struct OptReduceWorker
keep_expanding_mem_wren_sigs = false;
for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) {
if (!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::A))) ||
!mem_wren_sigs.check_all(assign_map(cell->getPort(ID::B))))
if (cell->type == ID($mux) && mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
if (!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::A))) ||
!mem_wren_sigs.check_all(assign_map(cell->getPort(TW::B))))
keep_expanding_mem_wren_sigs = true;
mem_wren_sigs.add(assign_map(cell->getPort(ID::A)));
mem_wren_sigs.add(assign_map(cell->getPort(ID::B)));
mem_wren_sigs.add(assign_map(cell->getPort(TW::A)));
mem_wren_sigs.add(assign_map(cell->getPort(TW::B)));
}
}
}
@ -563,7 +563,7 @@ struct OptReduceWorker
RTLIL::Cell *cell = cell_it.second;
if (cell->type != type || !design->selected(module, cell))
continue;
drivers.insert(assign_map(cell->getPort(ID::Y)), cell);
drivers.insert(assign_map(cell->getPort(TW::Y)), cell);
cells.insert(cell);
}
@ -582,7 +582,7 @@ struct OptReduceWorker
// this optimization is to aggressive for most coarse-grain applications.
// but we always want it for multiplexers driving write enable ports.
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(ID::Y)))) {
if (do_fine || mem_wren_sigs.check_any(assign_map(cell->getPort(TW::Y)))) {
if (cell->type == ID($demux)) {
if (opt_demux_bits(cell))
continue;

58
passes/opt/opt_share.cc
View file

@ -96,8 +96,8 @@ struct ExtSigSpec {
bool cell_supported(RTLIL::Cell *cell)
{
if (cell->type.in(ID($alu))) {
RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
RTLIL::SigSpec sig_bi = cell->getPort(TW::BI);
RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
return true;
@ -126,7 +126,7 @@ bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
return a_type == b_type;
}
RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_name)
RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, TwineRef port_name)
{
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($concat), SHIFT_OPS) && port_name == ID::B)
return port_name;
@ -137,17 +137,17 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
return "";
}
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, TwineRef port_name) {
if (cell->type == ID($alu) && port_name == ID::B)
return cell->getPort(ID::BI);
return cell->getPort(TW::BI);
else if (cell->type == ID($sub) && port_name == ID::B)
return RTLIL::Const(1, 1);
return RTLIL::Const(0, 1);
}
bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name)
bool decode_port_signed(RTLIL::Cell *cell, TwineRef port_name)
{
if (cell->type.in(BITWISE_OPS, LOGICAL_OPS))
return false;
@ -158,7 +158,7 @@ bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name)
return false;
}
ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, const SigMap &sigmap)
ExtSigSpec decode_port(RTLIL::Cell *cell, TwineRef port_name, const SigMap &sigmap)
{
auto sig = sigmap(cell->getPort(port_name));
@ -206,9 +206,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
module->remove(op);
}
RTLIL::SigSpec mux_a = mux->getPort(ID::A);
RTLIL::SigSpec mux_b = mux->getPort(ID::B);
RTLIL::SigSpec mux_s = mux->getPort(ID::S);
RTLIL::SigSpec mux_a = mux->getPort(TW::A);
RTLIL::SigSpec mux_b = mux->getPort(TW::B);
RTLIL::SigSpec mux_s = mux->getPort(TW::S);
int conn_width = ports[0].sig.size();
int conn_mux_offset = ports[0].mux_port_offset;
@ -219,7 +219,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
RTLIL::SigSpec shared_pmux_s;
// Make a new wire to avoid false equivalence with whatever the former shared output was connected to.
Wire *new_out = module->addWire(NEW_ID, conn_op_offset + conn_width);
Wire *new_out = module->addWire(NEW_TWINE, conn_op_offset + conn_width);
SigSpec new_sig_out = SigSpec(new_out, conn_op_offset, conn_width);
for (int i = 0; i < GetSize(ports); i++) {
@ -235,9 +235,9 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
}
}
mux->setPort(ID::A, mux_a);
mux->setPort(ID::B, mux_b);
mux->setPort(ID::S, mux_s);
mux->setPort(TW::A, mux_a);
mux->setPort(TW::B, mux_b);
mux->setPort(TW::S, mux_s);
SigSpec mux_to_oper;
if (GetSize(shared_pmux_s) == 1) {
@ -247,22 +247,22 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
}
if (shared_op->type.in(ID($alu))) {
shared_op->setPort(ID::X, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(ID::CO, module->addWire(NEW_ID, GetSize(new_out)));
shared_op->setPort(TW::X, module->addWire(NEW_TWINE, GetSize(new_out)));
shared_op->setPort(TW::CO, module->addWire(NEW_TWINE, GetSize(new_out)));
}
bool is_fine = shared_op->type.in(FINE_BITWISE_OPS);
shared_op->setPort(ID::Y, new_out);
shared_op->setPort(TW::Y, new_out);
if (!is_fine)
shared_op->setParam(ID::Y_WIDTH, GetSize(new_out));
if (decode_port(shared_op, ID::A, sigmap) == operand) {
shared_op->setPort(ID::B, mux_to_oper);
shared_op->setPort(TW::B, mux_to_oper);
if (!is_fine)
shared_op->setParam(ID::B_WIDTH, max_width);
} else {
shared_op->setPort(ID::A, mux_to_oper);
shared_op->setPort(TW::A, mux_to_oper);
if (!is_fine)
shared_op->setParam(ID::A_WIDTH, max_width);
}
@ -313,7 +313,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon
auto op_a = seed->op;
for (RTLIL::IdString port_name : {ID::A, ID::B}) {
for (TwineRef port_name : {ID::A, ID::B}) {
oper = decode_port(op_a, port_name, sigmap);
auto operand_users = operand_to_users.at(oper);
@ -386,7 +386,7 @@ struct OptSharePass : public Pass {
bool skip = false;
if (cell->type == ID($alu)) {
for (RTLIL::IdString port_name : {ID::X, ID::CO}) {
for (TwineRef port_name : {ID::X, ID::CO}) {
for (auto outbit : sigmap(cell->getPort(port_name)))
if (bit_users[outbit] > 1)
skip = true;
@ -396,11 +396,11 @@ struct OptSharePass : public Pass {
if (skip)
continue;
auto mux_insig = sigmap(cell->getPort(ID::Y));
auto mux_insig = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(mux_insig); i++)
op_outbit_to_outsig[mux_insig[i]] = std::make_pair(cell, i);
for (RTLIL::IdString port_name : {ID::A, ID::B}) {
for (TwineRef port_name : {ID::A, ID::B}) {
auto op_insig = decode_port(cell, port_name, sigmap);
operand_to_users[op_insig].insert(cell);
if (operand_to_users[op_insig].size() > 1)
@ -419,19 +419,19 @@ struct OptSharePass : public Pass {
if (!mux->type.in(ID($mux), ID($_MUX_), ID($pmux)))
continue;
int mux_port_size = GetSize(mux->getPort(ID::A));
int mux_port_num = GetSize(mux->getPort(ID::S)) + 1;
int mux_port_size = GetSize(mux->getPort(TW::A));
int mux_port_num = GetSize(mux->getPort(TW::S)) + 1;
RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(ID::B), mux->getPort(ID::A)});
RTLIL::SigSpec mux_insig = sigmap(RTLIL::SigSpec{mux->getPort(TW::B), mux->getPort(TW::A)});
std::vector<std::set<OpMuxConn>> mux_port_conns(mux_port_num);
int found = 0;
for (int mux_port_id = 0; mux_port_id < mux_port_num; mux_port_id++) {
SigSpec mux_insig;
if (mux_port_id == mux_port_num - 1) {
mux_insig = sigmap(mux->getPort(ID::A));
mux_insig = sigmap(mux->getPort(TW::A));
} else {
mux_insig = sigmap(mux->getPort(ID::B).extract(mux_port_id * mux_port_size, mux_port_size));
mux_insig = sigmap(mux->getPort(TW::B).extract(mux_port_id * mux_port_size, mux_port_size));
}
for (int mux_port_offset = 0; mux_port_offset < mux_port_size; ++mux_port_offset) {
@ -441,7 +441,7 @@ struct OptSharePass : public Pass {
RTLIL::Cell *cell;
int op_outsig_offset;
std::tie(cell, op_outsig_offset) = op_outbit_to_outsig.at(mux_insig[mux_port_offset]);
SigSpec op_outsig = sigmap(cell->getPort(ID::Y));
SigSpec op_outsig = sigmap(cell->getPort(TW::Y));
int op_outsig_size = GetSize(op_outsig);
int op_conn_width = 0;

2
passes/opt/peepopt_formal_clockgateff.pmg
View file

@ -50,7 +50,7 @@ code
// instead of the latch. We don't delete the latch in case its output is
// used to drive other nodes. If it isn't, it will be trivially removed by
// clean
SigSpec flopped_en = module->addWire(NEW_ID);
SigSpec flopped_en = module->addWire(NEW_TWINE);
module->addDff(NEW_ID, clk, en, flopped_en, true, latch->src_ref());
and_gate->setPort(latched_en_port_name, flopped_en);
did_something = true;

4
passes/opt/peepopt_shiftmul_left.pmg
View file

@ -129,7 +129,7 @@ code
if (bit == SigBit(State::Sm))
padbits++;
SigSpec padwire = module->addWire(NEW_ID, padbits);
SigSpec padwire = module->addWire(NEW_TWINE, padbits);
for (int i = new_y.size() - 1; i >= 0; i--)
if (new_y[i] == SigBit(State::Sm)) {
@ -148,7 +148,7 @@ code
shift->setPort(\B, new_b);
shift->setParam(\B_WIDTH, GetSize(new_b));
} else {
SigSpec b_neg = module->addWire(NEW_ID, GetSize(new_b) + 1);
SigSpec b_neg = module->addWire(NEW_TWINE, GetSize(new_b) + 1);
module->addNeg(NEW_ID, new_b, b_neg);
shift->setPort(\B, b_neg);
shift->setParam(\B_WIDTH, GetSize(b_neg));

44
passes/opt/pmux2shiftx.cc
View file

@ -56,19 +56,19 @@ struct OnehotDatabase
if (cell->type.in(ID($adff), ID($adffe), ID($dff), ID($dffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch), ID($ff)))
{
output = cell->getPort(ID::Q);
output = cell->getPort(TW::Q);
if (cell->type.in(ID($adff), ID($adffe), ID($adlatch)))
inputs.push_back(cell->getParam(ID::ARST_VALUE));
if (cell->type.in(ID($sdff), ID($sdffe), ID($sdffce)))
inputs.push_back(cell->getParam(ID::SRST_VALUE));
inputs.push_back(cell->getPort(ID::D));
inputs.push_back(cell->getPort(TW::D));
}
if (cell->type.in(ID($mux), ID($pmux)))
{
output = cell->getPort(ID::Y);
inputs.push_back(cell->getPort(ID::A));
SigSpec B = cell->getPort(ID::B);
output = cell->getPort(TW::Y);
inputs.push_back(cell->getPort(TW::A));
SigSpec B = cell->getPort(TW::B);
for (int i = 0; i < GetSize(B); i += GetSize(output))
inputs.push_back(B.extract(i, GetSize(output)));
}
@ -289,8 +289,8 @@ struct Pmux2ShiftxPass : public Pass {
{
dict<SigBit, State> bits;
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B));
SigSpec A = sigmap(cell->getPort(TW::A));
SigSpec B = sigmap(cell->getPort(TW::B));
int a_width = cell->getParam(ID::A_WIDTH).as_int();
int b_width = cell->getParam(ID::B_WIDTH).as_int();
@ -329,7 +329,7 @@ struct Pmux2ShiftxPass : public Pass {
}
entry.second = entry_bits_builder.build();
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
eqdb[sigmap(cell->getPort(TW::Y)[0])] = entry;
goto next_cell;
}
@ -337,7 +337,7 @@ struct Pmux2ShiftxPass : public Pass {
{
dict<SigBit, State> bits;
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec A = sigmap(cell->getPort(TW::A));
for (int i = 0; i < GetSize(A); i++)
bits[A[i]] = State::S0;
@ -351,7 +351,7 @@ struct Pmux2ShiftxPass : public Pass {
}
entry.second = entry_bits_builder.build();
eqdb[sigmap(cell->getPort(ID::Y)[0])] = entry;
eqdb[sigmap(cell->getPort(TW::Y)[0])] = entry;
goto next_cell;
}
next_cell:;
@ -372,9 +372,9 @@ struct Pmux2ShiftxPass : public Pass {
dict<SigSpec, pool<int>> seldb;
SigSpec A = cell->getPort(ID::A);
SigSpec B = cell->getPort(ID::B);
SigSpec S = sigmap(cell->getPort(ID::S));
SigSpec A = cell->getPort(TW::A);
SigSpec B = cell->getPort(TW::B);
SigSpec S = sigmap(cell->getPort(TW::S));
for (int i = 0; i < GetSize(S); i++)
{
if (!eqdb.count(S[i]))
@ -395,8 +395,8 @@ struct Pmux2ShiftxPass : public Pass {
log(" data width: %d (next power-of-2 = %d, log2 = %d)\n", width, extwidth, width_bits);
}
SigSpec updated_S = cell->getPort(ID::S);
SigSpec updated_B = cell->getPort(ID::B);
SigSpec updated_S = cell->getPort(TW::S);
SigSpec updated_B = cell->getPort(TW::B);
while (!seldb.empty())
{
@ -691,7 +691,7 @@ struct Pmux2ShiftxPass : public Pass {
Const enable_mask(State::S0, max_choice+1);
for (auto &it : perm_choices)
enable_mask.set(it.first.as_int(), State::S1);
en = module->addWire(NEW_ID);
en = module->addWire(NEW_TWINE);
module->addShift(NEW_ID, enable_mask, cmp, en, false, src);
}
@ -711,7 +711,7 @@ struct Pmux2ShiftxPass : public Pass {
// create shiftx cell
SigSpec shifted_cmp = {cmp, SigSpec(State::S0, width_bits)};
SigSpec outsig = module->addWire(NEW_ID, width);
SigSpec outsig = module->addWire(NEW_TWINE, width);
Cell *c = module->addShiftx(NEW_ID, data, shifted_cmp, outsig, false, src);
updated_S.append(en);
updated_B.append(outsig);
@ -722,8 +722,8 @@ struct Pmux2ShiftxPass : public Pass {
}
// update $pmux cell
cell->setPort(ID::S, updated_S);
cell->setPort(ID::B, updated_B);
cell->setPort(TW::S, updated_S);
cell->setPort(TW::B, updated_B);
cell->setParam(ID::S_WIDTH, GetSize(updated_S));
}
}
@ -780,8 +780,8 @@ struct OnehotPass : public Pass {
if (cell->type != ID($eq))
continue;
SigSpec A = sigmap(cell->getPort(ID::A));
SigSpec B = sigmap(cell->getPort(ID::B));
SigSpec A = sigmap(cell->getPort(TW::A));
SigSpec B = sigmap(cell->getPort(TW::B));
int a_width = cell->getParam(ID::A_WIDTH).as_int();
int b_width = cell->getParam(ID::B_WIDTH).as_int();
@ -828,7 +828,7 @@ struct OnehotPass : public Pass {
continue;
}
SigSpec Y = cell->getPort(ID::Y);
SigSpec Y = cell->getPort(TW::Y);
SigSpec replacement;
if (not_onehot)

146
passes/opt/share.cc
View file

@ -89,7 +89,7 @@ struct ShareWorker
for (auto &pbit : portbits) {
if ((pbit.cell->type == ID($mux) || pbit.cell->type == ID($pmux)) && visited_cells.count(pbit.cell) == 0) {
pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(ID::S)).to_sigbit_pool();
pool<RTLIL::SigBit> bits = modwalker.sigmap(pbit.cell->getPort(TW::S)).to_sigbit_pool();
terminal_bits.insert(bits.begin(), bits.end());
queue_bits.insert(bits.begin(), bits.end());
visited_cells.insert(pbit.cell);
@ -127,7 +127,7 @@ struct ShareWorker
static int bits_macc(RTLIL::Cell *c)
{
Macc m(c);
int width = GetSize(c->getPort(ID::Y));
int width = GetSize(c->getPort(TW::Y));
return bits_macc(m, width);
}
@ -206,12 +206,12 @@ struct ShareWorker
sig_b2.extend_u0(GetSize(sig_b), p2.is_signed);
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
sig_a = module->addWire(NEW_TWINE, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, sig_a2, sig_a1, act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
sig_b = module->addWire(NEW_TWINE, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, sig_b2, sig_b1, act, sig_b));
}
@ -241,7 +241,7 @@ struct ShareWorker
{
Macc m1(c1), m2(c2), supermacc;
int w1 = GetSize(c1->getPort(ID::Y)), w2 = GetSize(c2->getPort(ID::Y));
int w1 = GetSize(c1->getPort(TW::Y)), w2 = GetSize(c2->getPort(TW::Y));
int width = max(w1, w2);
m1.optimize(w1);
@ -283,12 +283,12 @@ struct ShareWorker
RTLIL::SigSpec sig_b = m1.terms[i].in_b;
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
sig_a = module->addWire(NEW_TWINE, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_a)), m1.terms[i].in_a, act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
sig_b = module->addWire(NEW_TWINE, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, RTLIL::SigSpec(0, GetSize(sig_b)), m1.terms[i].in_b, act, sig_b));
}
@ -306,12 +306,12 @@ struct ShareWorker
RTLIL::SigSpec sig_b = m2.terms[i].in_b;
if (supercell_aux && GetSize(sig_a)) {
sig_a = module->addWire(NEW_ID, GetSize(sig_a));
sig_a = module->addWire(NEW_TWINE, GetSize(sig_a));
supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_a, RTLIL::SigSpec(0, GetSize(sig_a)), act, sig_a));
}
if (supercell_aux && GetSize(sig_b)) {
sig_b = module->addWire(NEW_ID, GetSize(sig_b));
sig_b = module->addWire(NEW_TWINE, GetSize(sig_b));
supercell_aux->insert(module->addMux(NEW_ID, m2.terms[i].in_b, RTLIL::SigSpec(0, GetSize(sig_b)), act, sig_b));
}
@ -325,13 +325,13 @@ struct ShareWorker
if (supercell)
{
RTLIL::SigSpec sig_y = module->addWire(NEW_ID, width);
RTLIL::SigSpec sig_y = module->addWire(NEW_TWINE, width);
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(ID::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c1->getPort(TW::Y)));
supercell_aux->insert(module->addPos(NEW_ID, sig_y, c2->getPort(TW::Y)));
supercell->setParam(ID::Y_WIDTH, width);
supercell->setPort(ID::Y, sig_y);
supercell->setPort(TW::Y, sig_y);
supermacc.optimize(width);
supermacc.to_cell(supercell);
@ -365,7 +365,7 @@ struct ShareWorker
if (cell->type.in(ID($memrd), ID($memrd_v2))) {
if (cell->parameters.at(ID::CLK_ENABLE).as_bool())
continue;
if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(ID::ADDR)).is_fully_const())
if (config.opt_aggressive || !modwalker.sigmap(cell->getPort(TW::ADDR)).is_fully_const())
shareable_cells.insert(cell);
continue;
}
@ -510,11 +510,11 @@ struct ShareWorker
if (c1->parameters.at(ID::A_SIGNED).as_bool() != c2->parameters.at(ID::A_SIGNED).as_bool())
{
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort(TW::A).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
RTLIL::SigSpec new_a = unsigned_cell->getPort(TW::A);
new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
unsigned_cell->setPort(TW::A, new_a);
}
unsigned_cell->parameters.at(ID::A_SIGNED) = true;
unsigned_cell->check();
@ -523,11 +523,11 @@ struct ShareWorker
bool a_signed = c1->parameters.at(ID::A_SIGNED).as_bool();
log_assert(a_signed == c2->parameters.at(ID::A_SIGNED).as_bool());
RTLIL::SigSpec a1 = c1->getPort(ID::A);
RTLIL::SigSpec y1 = c1->getPort(ID::Y);
RTLIL::SigSpec a1 = c1->getPort(TW::A);
RTLIL::SigSpec y1 = c1->getPort(TW::Y);
RTLIL::SigSpec a2 = c2->getPort(ID::A);
RTLIL::SigSpec y2 = c2->getPort(ID::Y);
RTLIL::SigSpec a2 = c2->getPort(TW::A);
RTLIL::SigSpec y2 = c2->getPort(TW::Y);
int a_width = max(a1.size(), a2.size());
int y_width = max(y1.size(), y2.size());
@ -535,17 +535,17 @@ struct ShareWorker
a1.extend_u0(a_width, a_signed);
a2.extend_u0(a_width, a_signed);
RTLIL::SigSpec a = module->addWire(NEW_ID, a_width);
RTLIL::SigSpec a = module->addWire(NEW_TWINE, a_width);
supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID::A_WIDTH] = a_width;
supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::Y, y);
supercell->setPort(TW::A, a);
supercell->setPort(TW::Y, y);
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
@ -568,9 +568,9 @@ struct ShareWorker
if (score_flipped < score_unflipped)
{
RTLIL::SigSpec tmp = c2->getPort(ID::A);
c2->setPort(ID::A, c2->getPort(ID::B));
c2->setPort(ID::B, tmp);
RTLIL::SigSpec tmp = c2->getPort(TW::A);
c2->setPort(TW::A, c2->getPort(TW::B));
c2->setPort(TW::B, tmp);
std::swap(c2->parameters.at(ID::A_WIDTH), c2->parameters.at(ID::B_WIDTH));
std::swap(c2->parameters.at(ID::A_SIGNED), c2->parameters.at(ID::B_SIGNED));
@ -582,11 +582,11 @@ struct ShareWorker
{
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::A_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::A).to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort(TW::A).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID::A_WIDTH) = unsigned_cell->parameters.at(ID::A_WIDTH).as_int() + 1;
RTLIL::SigSpec new_a = unsigned_cell->getPort(ID::A);
RTLIL::SigSpec new_a = unsigned_cell->getPort(TW::A);
new_a.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::A, new_a);
unsigned_cell->setPort(TW::A, new_a);
}
unsigned_cell->parameters.at(ID::A_SIGNED) = true;
modified_src_cells = true;
@ -595,11 +595,11 @@ struct ShareWorker
if (c1->parameters.at(ID::B_SIGNED).as_bool() != c2->parameters.at(ID::B_SIGNED).as_bool())
{
RTLIL::Cell *unsigned_cell = c1->parameters.at(ID::B_SIGNED).as_bool() ? c2 : c1;
if (unsigned_cell->getPort(ID::B).to_sigbit_vector().back() != RTLIL::State::S0) {
if (unsigned_cell->getPort(TW::B).to_sigbit_vector().back() != RTLIL::State::S0) {
unsigned_cell->parameters.at(ID::B_WIDTH) = unsigned_cell->parameters.at(ID::B_WIDTH).as_int() + 1;
RTLIL::SigSpec new_b = unsigned_cell->getPort(ID::B);
RTLIL::SigSpec new_b = unsigned_cell->getPort(TW::B);
new_b.append(RTLIL::State::S0);
unsigned_cell->setPort(ID::B, new_b);
unsigned_cell->setPort(TW::B, new_b);
}
unsigned_cell->parameters.at(ID::B_SIGNED) = true;
modified_src_cells = true;
@ -619,13 +619,13 @@ struct ShareWorker
if (c1->type == ID($shl) || c1->type == ID($shr) || c1->type == ID($sshl) || c1->type == ID($sshr))
b_signed = false;
RTLIL::SigSpec a1 = c1->getPort(ID::A);
RTLIL::SigSpec b1 = c1->getPort(ID::B);
RTLIL::SigSpec y1 = c1->getPort(ID::Y);
RTLIL::SigSpec a1 = c1->getPort(TW::A);
RTLIL::SigSpec b1 = c1->getPort(TW::B);
RTLIL::SigSpec y1 = c1->getPort(TW::Y);
RTLIL::SigSpec a2 = c2->getPort(ID::A);
RTLIL::SigSpec b2 = c2->getPort(ID::B);
RTLIL::SigSpec y2 = c2->getPort(ID::Y);
RTLIL::SigSpec a2 = c2->getPort(TW::A);
RTLIL::SigSpec b2 = c2->getPort(TW::B);
RTLIL::SigSpec y2 = c2->getPort(TW::Y);
int a_width = max(a1.size(), a2.size());
int b_width = max(b1.size(), b2.size());
@ -650,43 +650,43 @@ struct ShareWorker
b1.extend_u0(b_width, b_signed);
b2.extend_u0(b_width, b_signed);
RTLIL::SigSpec a = module->addWire(NEW_ID, a_width);
RTLIL::SigSpec b = module->addWire(NEW_ID, b_width);
RTLIL::SigSpec a = module->addWire(NEW_TWINE, a_width);
RTLIL::SigSpec b = module->addWire(NEW_TWINE, b_width);
supercell_aux.insert(module->addMux(NEW_ID, a2, a1, act, a));
supercell_aux.insert(module->addMux(NEW_ID, b2, b1, act, b));
RTLIL::Wire *y = module->addWire(NEW_ID, y_width);
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_ID, y_width) : nullptr;
RTLIL::Wire *y = module->addWire(NEW_TWINE, y_width);
RTLIL::Wire *x = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
RTLIL::Wire *co = c1->type == ID($alu) ? module->addWire(NEW_TWINE, y_width) : nullptr;
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
supercell->parameters[ID::A_SIGNED] = a_signed;
supercell->parameters[ID::B_SIGNED] = b_signed;
supercell->parameters[ID::A_WIDTH] = a_width;
supercell->parameters[ID::B_WIDTH] = b_width;
supercell->parameters[ID::Y_WIDTH] = y_width;
supercell->setPort(ID::A, a);
supercell->setPort(ID::B, b);
supercell->setPort(ID::Y, y);
supercell->setPort(TW::A, a);
supercell->setPort(TW::B, b);
supercell->setPort(TW::Y, y);
if (c1->type == ID($alu)) {
RTLIL::Wire *ci = module->addWire(NEW_ID), *bi = module->addWire(NEW_ID);
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::CI), c1->getPort(ID::CI), act, ci));
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(ID::BI), c1->getPort(ID::BI), act, bi));
supercell->setPort(ID::CI, ci);
supercell->setPort(ID::BI, bi);
supercell->setPort(ID::CO, co);
supercell->setPort(ID::X, x);
RTLIL::Wire *ci = module->addWire(NEW_TWINE), *bi = module->addWire(NEW_TWINE);
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(TW::CI), c1->getPort(TW::CI), act, ci));
supercell_aux.insert(module->addMux(NEW_ID, c2->getPort(TW::BI), c1->getPort(TW::BI), act, bi));
supercell->setPort(TW::CI, ci);
supercell->setPort(TW::BI, bi);
supercell->setPort(TW::CO, co);
supercell->setPort(TW::X, x);
}
supercell->check();
supercell_aux.insert(module->addPos(NEW_ID, y, y1));
supercell_aux.insert(module->addPos(NEW_ID, y, y2));
if (c1->type == ID($alu)) {
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(ID::CO)));
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(ID::X)));
supercell_aux.insert(module->addPos(NEW_ID, co, c1->getPort(TW::CO)));
supercell_aux.insert(module->addPos(NEW_ID, co, c2->getPort(TW::CO)));
supercell_aux.insert(module->addPos(NEW_ID, x, c1->getPort(TW::X)));
supercell_aux.insert(module->addPos(NEW_ID, x, c2->getPort(TW::X)));
}
supercell_aux.insert(supercell);
@ -695,7 +695,7 @@ struct ShareWorker
if (c1->type == ID($macc))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1->type);
supercell_aux.insert(supercell);
share_macc(c1, c2, act, supercell, &supercell_aux);
supercell->check();
@ -704,16 +704,16 @@ struct ShareWorker
if (c1->type.in(ID($memrd), ID($memrd_v2)))
{
RTLIL::Cell *supercell = module->addCell(NEW_ID, c1);
RTLIL::SigSpec addr1 = c1->getPort(ID::ADDR);
RTLIL::SigSpec addr2 = c2->getPort(ID::ADDR);
RTLIL::Cell *supercell = module->addCell(NEW_TWINE, c1);
RTLIL::SigSpec addr1 = c1->getPort(TW::ADDR);
RTLIL::SigSpec addr2 = c2->getPort(TW::ADDR);
if (GetSize(addr1) < GetSize(addr2))
addr1.extend_u0(GetSize(addr2));
else
addr2.extend_u0(GetSize(addr1));
supercell->setPort(ID::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
supercell->setPort(TW::ADDR, addr1 != addr2 ? module->Mux(NEW_ID, addr2, addr1, act) : addr1);
supercell->parameters[ID::ABITS] = RTLIL::Const(GetSize(addr1));
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(ID::DATA), c2->getPort(ID::DATA)));
supercell_aux.insert(module->addPos(NEW_ID, supercell->getPort(TW::DATA), c2->getPort(TW::DATA)));
supercell_aux.insert(supercell);
return supercell;
}
@ -745,7 +745,7 @@ struct ShareWorker
for (auto &bit : pbits) {
if ((bit.cell->type == ID($mux) || bit.cell->type == ID($pmux)) && bit.port == ID::S)
forbidden_controls_cache[cell].insert(bit.cell->getPort(ID::S).extract(bit.offset, 1));
forbidden_controls_cache[cell].insert(bit.cell->getPort(TW::S).extract(bit.offset, 1));
consumer_cells.insert(bit.cell);
}
@ -909,9 +909,9 @@ struct ShareWorker
std::set<int> used_in_b_parts;
int width = c->parameters.at(ID::WIDTH).as_int();
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(ID::A));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(ID::B));
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(ID::S));
std::vector<RTLIL::SigBit> sig_a = modwalker.sigmap(c->getPort(TW::A));
std::vector<RTLIL::SigBit> sig_b = modwalker.sigmap(c->getPort(TW::B));
std::vector<RTLIL::SigBit> sig_s = modwalker.sigmap(c->getPort(TW::S));
for (auto &bit : sig_a)
if (cell_out_bits.count(bit))
@ -1059,7 +1059,7 @@ struct ShareWorker
RTLIL::SigSpec make_cell_activation_logic(const pool<ssc_pair_t> &activation_patterns, pool<RTLIL::Cell*> &supercell_aux)
{
RTLIL::Wire *all_cases_wire = module->addWire(NEW_ID, 0);
RTLIL::Wire *all_cases_wire = module->addWire(NEW_TWINE, 0);
for (auto &p : activation_patterns) {
all_cases_wire->width++;
@ -1069,7 +1069,7 @@ struct ShareWorker
if (all_cases_wire->width == 1)
return all_cases_wire;
RTLIL::Wire *result_wire = module->addWire(NEW_ID);
RTLIL::Wire *result_wire = module->addWire(NEW_TWINE);
supercell_aux.insert(module->addReduceOr(NEW_ID, all_cases_wire, result_wire));
return result_wire;
}

60
passes/opt/wreduce.cc
View file

@ -66,10 +66,10 @@ struct WreduceWorker
{
// Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
SigSpec sig_b = mi.sigmap(cell->getPort(ID::B));
SigSpec sig_s = mi.sigmap(cell->getPort(ID::S));
SigSpec sig_y = mi.sigmap(cell->getPort(ID::Y));
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A));
SigSpec sig_b = mi.sigmap(cell->getPort(TW::B));
SigSpec sig_s = mi.sigmap(cell->getPort(TW::S));
SigSpec sig_y = mi.sigmap(cell->getPort(TW::Y));
std::vector<SigBit> bits_removed;
if (sig_y.has_const())
@ -132,9 +132,9 @@ struct WreduceWorker
for (auto bit : new_work_queue_bits)
work_queue_bits.insert(bit);
cell->setPort(ID::A, new_sig_a);
cell->setPort(ID::B, new_sig_b);
cell->setPort(ID::Y, new_sig_y);
cell->setPort(TW::A, new_sig_a);
cell->setPort(TW::B, new_sig_b);
cell->setPort(TW::Y, new_sig_y);
cell->fixup_parameters();
module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
@ -144,8 +144,8 @@ struct WreduceWorker
{
// Reduce size of FF if inputs are just sign/zero extended or output bit is not used
SigSpec sig_d = mi.sigmap(cell->getPort(ID::D));
SigSpec sig_q = mi.sigmap(cell->getPort(ID::Q));
SigSpec sig_d = mi.sigmap(cell->getPort(TW::D));
SigSpec sig_q = mi.sigmap(cell->getPort(TW::Q));
bool has_reset = false;
Const rst_value;
std::vector<State> initval = initvals(sig_q).to_bits();
@ -234,9 +234,9 @@ struct WreduceWorker
cell->setParam(ID::SRST_VALUE, rst_value);
}
cell->setPort(ID::D, sig_d);
cell->setPort(ID::Q, sig_q);
initvals.set_init(cell->getPort(ID::Q), initval);
cell->setPort(TW::D, sig_d);
cell->setPort(TW::Q, sig_q);
initvals.set_init(cell->getPort(TW::Q), initval);
cell->fixup_parameters();
}
@ -298,7 +298,7 @@ struct WreduceWorker
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($sdff), ID($sdffe), ID($sdffce), ID($dlatch), ID($adlatch)))
return run_cell_dff(cell);
SigSpec sig = mi.sigmap(cell->getPort(ID::Y));
SigSpec sig = mi.sigmap(cell->getPort(TW::Y));
if (sig.has_const())
return;
@ -306,8 +306,8 @@ struct WreduceWorker
// Reduce size of ports A and B based on constant input bits and size of output port
int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : -1;
int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : -1;
int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(TW::A)) : -1;
int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(TW::B)) : -1;
if (cell->type.in(ID($not), ID($pos), ID($neg), ID($and), ID($or), ID($xor), ID($add), ID($sub))) {
max_port_a_size = min(max_port_a_size, GetSize(sig));
@ -322,7 +322,7 @@ struct WreduceWorker
if (cell->type.in(ID($mul), ID($add), ID($sub)) &&
max_port_a_size == GetSize(sig) &&
max_port_b_size == GetSize(sig)) {
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B));
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B));
// Remove top bits from sig_a and sig_b which are not visible on the output
sig_a.extend_u0(max_port_a_size);
@ -363,7 +363,7 @@ struct WreduceWorker
run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something);
if (cell->hasPort(ID::A) && cell->hasPort(ID::B) && port_a_signed && port_b_signed) {
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A)), sig_b = mi.sigmap(cell->getPort(ID::B));
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A)), sig_b = mi.sigmap(cell->getPort(TW::B));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 &&
GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
@ -377,7 +377,7 @@ struct WreduceWorker
}
if (cell->hasPort(ID::A) && !cell->hasPort(ID::B) && port_a_signed) {
SigSpec sig_a = mi.sigmap(cell->getPort(ID::A));
SigSpec sig_a = mi.sigmap(cell->getPort(TW::A));
if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) {
log("Converting cell %s.%s (%s) from signed to unsigned.\n",
module, cell, cell->type.unescape());
@ -414,8 +414,8 @@ struct WreduceWorker
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool() || cell->type == ID($sub);
int a_size = 0, b_size = 0;
if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A));
if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(ID::B));
if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(TW::A));
if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(TW::B));
int max_y_size = max(a_size, b_size);
@ -447,7 +447,7 @@ struct WreduceWorker
if (bits_removed) {
log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
bits_removed, GetSize(sig) + bits_removed, module, cell, cell->type.unescape());
cell->setPort(ID::Y, sig);
cell->setPort(TW::Y, sig);
did_something = true;
}
@ -519,7 +519,7 @@ struct WreduceWorker
continue;
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), module, w);
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
Wire *nw = module->addWire(NEW_TWINE, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
}
@ -591,10 +591,10 @@ struct WreducePass : public Pass {
{
if (c->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool),
ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt),
ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(ID::Y)) > 1) {
SigSpec sig = c->getPort(ID::Y);
ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(TW::Y)) > 1) {
SigSpec sig = c->getPort(TW::Y);
if (!sig.has_const()) {
c->setPort(ID::Y, sig[0]);
c->setPort(TW::Y, sig[0]);
c->setParam(ID::Y_WIDTH, 1);
sig.remove(0);
module->connect(sig, Const(0, GetSize(sig)));
@ -603,7 +603,7 @@ struct WreducePass : public Pass {
if (c->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor), ID($pow)))
{
SigSpec A = c->getPort(ID::A);
SigSpec A = c->getPort(TW::A);
int original_a_width = GetSize(A);
if (c->getParam(ID::A_SIGNED).as_bool()) {
while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0)
@ -615,11 +615,11 @@ struct WreducePass : public Pass {
if (original_a_width != GetSize(A)) {
log("Removed top %d bits (of %d) from port A of cell %s.%s (%s).\n",
original_a_width-GetSize(A), original_a_width, module, c, c->type.unescape());
c->setPort(ID::A, A);
c->setPort(TW::A, A);
c->setParam(ID::A_WIDTH, GetSize(A));
}
SigSpec B = c->getPort(ID::B);
SigSpec B = c->getPort(TW::B);
int original_b_width = GetSize(B);
if (c->getParam(ID::B_SIGNED).as_bool()) {
while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0)
@ -631,7 +631,7 @@ struct WreducePass : public Pass {
if (original_b_width != GetSize(B)) {
log("Removed top %d bits (of %d) from port B of cell %s.%s (%s).\n",
original_b_width-GetSize(B), original_b_width, module, c, c->type.unescape());
c->setPort(ID::B, B);
c->setPort(TW::B, B);
c->setParam(ID::B_WIDTH, GetSize(B));
}
}
@ -648,7 +648,7 @@ struct WreducePass : public Pass {
c->type == ID($memrd) ? "read" : c->type == ID($memwr) ? "write" : "init",
module, c, memid.unescape());
c->setParam(ID::ABITS, max_addrbits);
c->setPort(ID::ADDR, c->getPort(ID::ADDR).extract(0, max_addrbits));
c->setPort(TW::ADDR, c->getPort(TW::ADDR).extract(0, max_addrbits));
}
}
}

4
passes/pmgen/README.md
View file

@ -367,8 +367,8 @@ test-case generation. For example:
...
generate 10 0
SigSpec Y = port(ff, \D);
SigSpec A = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
SigSpec B = module->addWire(NEW_ID, GetSize(Y) - rng(GetSize(Y)/2));
SigSpec A = module->addWire(NEW_TWINE, GetSize(Y) - rng(GetSize(Y)/2));
SigSpec B = module->addWire(NEW_TWINE, GetSize(Y) - rng(GetSize(Y)/2));
module->addMul(NEW_ID, A, B, Y, rng(2));
endmatch

2
passes/pmgen/generate.h
View file

@ -131,7 +131,7 @@ void generate_pattern(std::function<void(pm&,std::function<void()>)> run, const
for (auto mod : mods) {
Cell *c = m->addCell(mod->name, mod->name);
for (auto port : mod->ports) {
Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port)));
Wire *w = m->addWire(NEW_TWINE, GetSize(mod->wire(port)));
c->setPort(port, w);
}
}

4
passes/pmgen/pmgen.py
View file

@ -451,13 +451,13 @@ with open(outfile, "w") as f:
current_pattern = None
print(" SigSpec port(Cell *cell, IdString portname) {", file=f)
print(" SigSpec port(Cell *cell, TwineRef portname) {", file=f)
print(" try {", file=f)
print(" return (*sigmap)(cell->getPort(portname));", file=f)
print(" } catch(std::out_of_range&) { log_error(\"Accessing non existing port %s\\n\",portname); }", file=f)
print(" }", file=f)
print("", file=f)
print(" SigSpec port(Cell *cell, IdString portname, const SigSpec& defval) {", file=f)
print(" SigSpec port(Cell *cell, TwineRef portname, const SigSpec& defval) {", file=f)
print(" return (*sigmap)(cell->connections_.at(portname, defval));", file=f)
print(" }", file=f)
print("", file=f)

16
passes/pmgen/test_pmgen.cc
View file

@ -40,14 +40,14 @@ void reduce_chain(test_pmgen_pm &pm)
log("Found chain of length %d (%s):\n", GetSize(ud.longest_chain), st.first->type.unescape());
SigSpec A;
SigSpec Y = ud.longest_chain.front().first->getPort(ID::Y);
SigSpec Y = ud.longest_chain.front().first->getPort(TW::Y);
auto last_cell = ud.longest_chain.back().first;
for (auto it : ud.longest_chain) {
auto cell = it.first;
if (cell == last_cell) {
A.append(cell->getPort(ID::A));
A.append(cell->getPort(ID::B));
A.append(cell->getPort(TW::A));
A.append(cell->getPort(TW::B));
} else {
A.append(cell->getPort(it.second == ID::A ? ID::B : ID::A));
}
@ -78,7 +78,7 @@ void reduce_tree(test_pmgen_pm &pm)
return;
SigSpec A = ud.leaves;
SigSpec Y = st.first->getPort(ID::Y);
SigSpec Y = st.first->getPort(TW::Y);
pm.autoremove(st.first);
log("Found %s tree with %d leaves for %s (%s).\n", st.first->type.unescape(),
@ -102,17 +102,17 @@ void opt_eqpmux(test_pmgen_pm &pm)
{
auto &st = pm.st_eqpmux;
SigSpec Y = st.pmux->getPort(ID::Y);
SigSpec Y = st.pmux->getPort(TW::Y);
int width = GetSize(Y);
SigSpec EQ = st.pmux->getPort(ID::B).extract(st.pmux_slice_eq*width, width);
SigSpec NE = st.pmux->getPort(ID::B).extract(st.pmux_slice_ne*width, width);
SigSpec EQ = st.pmux->getPort(TW::B).extract(st.pmux_slice_eq*width, width);
SigSpec NE = st.pmux->getPort(TW::B).extract(st.pmux_slice_ne*width, width);
log("Found eqpmux circuit driving %s (eq=%s, ne=%s, pmux=%s).\n",
log_signal(Y), st.eq, st.ne, st.pmux);
pm.autoremove(st.pmux);
Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(ID::Y), Y);
Cell *c = pm.module->addMux(NEW_ID, NE, EQ, st.eq->getPort(TW::Y), Y);
log(" -> %s (%s)\n", c, c->type.unescape());
}

28
passes/pmgen/test_pmgen.pmg
View file

@ -14,9 +14,9 @@ match first
select first->type.in($_AND_, $_OR_, $_XOR_)
filter !non_first_cells.count(first)
generate
SigSpec A = module->addWire(NEW_ID);
SigSpec B = module->addWire(NEW_ID);
SigSpec Y = module->addWire(NEW_ID);
SigSpec A = module->addWire(NEW_TWINE);
SigSpec B = module->addWire(NEW_TWINE);
SigSpec Y = module->addWire(NEW_TWINE);
switch (rng(3))
{
case 0:
@ -82,8 +82,8 @@ match next
index <IdString> next->type === chain.back().first->type
index <SigSpec> port(next, \Y) === port(chain.back().first, chain.back().second)
generate 10
SigSpec A = module->addWire(NEW_ID);
SigSpec B = module->addWire(NEW_ID);
SigSpec A = module->addWire(NEW_TWINE);
SigSpec B = module->addWire(NEW_TWINE);
SigSpec Y = port(chain.back().first, chain.back().second);
Cell *c = module->addAndGate(NEW_ID, A, B, Y);
c->type = chain.back().first->type;
@ -121,9 +121,9 @@ match eq
set eq_inB port(eq, \B)
set eq_ne_signed param(eq, \A_SIGNED).as_bool()
generate 100 10
SigSpec A = module->addWire(NEW_ID, rng(7)+1);
SigSpec B = module->addWire(NEW_ID, rng(7)+1);
SigSpec Y = module->addWire(NEW_ID);
SigSpec A = module->addWire(NEW_TWINE, rng(7)+1);
SigSpec B = module->addWire(NEW_TWINE, rng(7)+1);
SigSpec Y = module->addWire(NEW_TWINE);
module->addEq(NEW_ID, A, B, Y, rng(2));
endmatch
@ -137,13 +137,13 @@ generate 100 10
int numsel = rng(4) + 1;
int idx = rng(numsel);
SigSpec A = module->addWire(NEW_ID, width);
SigSpec Y = module->addWire(NEW_ID, width);
SigSpec A = module->addWire(NEW_TWINE, width);
SigSpec Y = module->addWire(NEW_TWINE, width);
SigSpec B, S;
for (int i = 0; i < numsel; i++) {
B.append(module->addWire(NEW_ID, width));
S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_ID));
B.append(module->addWire(NEW_TWINE, width));
S.append(i == idx ? port(eq, \Y) : module->addWire(NEW_TWINE));
}
module->addPmux(NEW_ID, A, B, S, Y);
@ -169,9 +169,9 @@ generate 100 10
if (GetSize(Y))
Y = Y[rng(GetSize(Y))];
else
Y = module->addWire(NEW_ID);
Y = module->addWire(NEW_TWINE);
} else {
Y = module->addWire(NEW_ID);
Y = module->addWire(NEW_TWINE);
}
module->addNe(NEW_ID, A, B, Y, rng(2));
endmatch

44
passes/proc/proc_arst.cc
View file

@ -39,45 +39,45 @@ bool check_signal(RTLIL::Module *mod, RTLIL::SigSpec signal, RTLIL::SigSpec ref,
for (auto cell : mod->cells())
{
if (cell->type == ID($reduce_or) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == ID($reduce_or) && cell->getPort(TW::Y) == signal)
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
if (cell->type == ID($reduce_bool) && cell->getPort(ID::Y) == signal)
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
if (cell->type == ID($reduce_bool) && cell->getPort(TW::Y) == signal)
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
if (cell->type == ID($logic_not) && cell->getPort(ID::Y) == signal) {
if (cell->type == ID($logic_not) && cell->getPort(TW::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
if (cell->type == ID($not) && cell->getPort(ID::Y) == signal) {
if (cell->type == ID($not) && cell->getPort(TW::Y) == signal) {
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (!cell->getPort(ID::A).as_bool())
if (cell->type.in(ID($eq), ID($eqx)) && cell->getPort(TW::Y) == signal) {
if (cell->getPort(TW::A).is_fully_const()) {
if (!cell->getPort(TW::A).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::B), ref, polarity);
return check_signal(mod, cell->getPort(TW::B), ref, polarity);
}
if (cell->getPort(ID::B).is_fully_const()) {
if (!cell->getPort(ID::B).as_bool())
if (cell->getPort(TW::B).is_fully_const()) {
if (!cell->getPort(TW::B).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
}
if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(ID::Y) == signal) {
if (cell->getPort(ID::A).is_fully_const()) {
if (cell->getPort(ID::A).as_bool())
if (cell->type.in(ID($ne), ID($nex)) && cell->getPort(TW::Y) == signal) {
if (cell->getPort(TW::A).is_fully_const()) {
if (cell->getPort(TW::A).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::B), ref, polarity);
return check_signal(mod, cell->getPort(TW::B), ref, polarity);
}
if (cell->getPort(ID::B).is_fully_const()) {
if (cell->getPort(ID::B).as_bool())
if (cell->getPort(TW::B).is_fully_const()) {
if (cell->getPort(TW::B).as_bool())
polarity = !polarity;
return check_signal(mod, cell->getPort(ID::A), ref, polarity);
return check_signal(mod, cell->getPort(TW::A), ref, polarity);
}
}
}

18
passes/proc/proc_dff.cc
View file

@ -100,11 +100,11 @@ void gen_aldff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::SigSpec sig_set
cell->parameters[ID::WIDTH] = RTLIL::Const(sig_in.size());
cell->parameters[ID::ALOAD_POLARITY] = RTLIL::Const(set_polarity, 1);
cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
cell->setPort(ID::D, sig_in);
cell->setPort(ID::Q, sig_out);
cell->setPort(ID::AD, sig_set);
cell->setPort(ID::CLK, clk);
cell->setPort(ID::ALOAD, set);
cell->setPort(TW::D, sig_in);
cell->setPort(TW::Q, sig_out);
cell->setPort(TW::AD, sig_set);
cell->setPort(TW::CLK, clk);
cell->setPort(TW::ALOAD, set);
log(" created %s cell `%s' with %s edge clock and %s level non-const reset.\n", cell->type, cell->name,
clk_polarity ? "positive" : "negative", set_polarity ? "positive" : "negative");
@ -128,12 +128,12 @@ void gen_dff(RTLIL::Module *mod, RTLIL::SigSpec sig_in, RTLIL::Const val_rst, RT
cell->parameters[ID::CLK_POLARITY] = RTLIL::Const(clk_polarity, 1);
}
cell->setPort(ID::D, sig_in);
cell->setPort(ID::Q, sig_out);
cell->setPort(TW::D, sig_in);
cell->setPort(TW::Q, sig_out);
if (arst)
cell->setPort(ID::ARST, *arst);
cell->setPort(TW::ARST, *arst);
if (!clk.empty())
cell->setPort(ID::CLK, clk);
cell->setPort(TW::CLK, clk);
if (!clk.empty())
log(" created %s cell `%s' with %s edge clock", cell->type, cell->name, clk_polarity ? "positive" : "negative");

32
passes/proc/proc_dlatch.cc
View file

@ -48,14 +48,14 @@ struct proc_dlatch_db_t
{
if (cell->type.in(ID($mux), ID($pmux), ID($bwmux)))
{
auto sig_y = sigmap(cell->getPort(ID::Y));
auto sig_y = sigmap(cell->getPort(TW::Y));
for (int i = 0; i < GetSize(sig_y); i++)
mux_drivers[sig_y[i]] = pair<Cell*, int>(cell, i);
pool<SigBit> mux_srcbits_pool;
for (auto bit : sigmap(cell->getPort(ID::A)))
for (auto bit : sigmap(cell->getPort(TW::A)))
mux_srcbits_pool.insert(bit);
for (auto bit : sigmap(cell->getPort(ID::B)))
for (auto bit : sigmap(cell->getPort(TW::B)))
mux_srcbits_pool.insert(bit);
vector<SigBit> mux_srcbits_vec;
@ -187,9 +187,9 @@ struct proc_dlatch_db_t
log_assert(cell->type.in(ID($mux), ID($pmux), ID($bwmux)));
bool is_bwmux = (cell->type == ID($bwmux));
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_s = sigmap(cell->getPort(ID::S));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_s = sigmap(cell->getPort(TW::S));
int width = GetSize(sig_a);
pool<int> children;
@ -197,9 +197,9 @@ struct proc_dlatch_db_t
int n = find_mux_feedback(sig_a[index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_a[index] == needle) {
SigSpec sig = cell->getPort(ID::A);
SigSpec sig = cell->getPort(TW::A);
sig[index] = State::Sx;
cell->setPort(ID::A, sig);
cell->setPort(TW::A, sig);
}
if (!is_bwmux) {
for (int i = 0; i < GetSize(sig_s); i++)
@ -214,9 +214,9 @@ struct proc_dlatch_db_t
n = find_mux_feedback(sig_b[i*width + index], needle, set_undef);
if (n != false_node) {
if (set_undef && sig_b[i*width + index] == needle) {
SigSpec sig = cell->getPort(ID::B);
SigSpec sig = cell->getPort(TW::B);
sig[i*width + index] = State::Sx;
cell->setPort(ID::B, sig);
cell->setPort(TW::B, sig);
}
children.insert(make_inner(sig_s[is_bwmux ? index : i], State::S1, n));
}
@ -268,9 +268,9 @@ struct proc_dlatch_db_t
void fixup_mux(Cell *cell)
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_s = cell->getPort(ID::S);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
SigSpec sig_s = cell->getPort(TW::S);
SigSpec sig_any_valid_b;
SigSpec sig_new_b, sig_new_s;
@ -289,7 +289,7 @@ struct proc_dlatch_db_t
}
if (sig_a.is_fully_undef() && !sig_any_valid_b.empty())
cell->setPort(ID::A, sig_any_valid_b);
cell->setPort(TW::A, sig_any_valid_b);
if (GetSize(sig_new_s) == 1) {
cell->type = ID($mux);
@ -299,8 +299,8 @@ struct proc_dlatch_db_t
cell->setParam(ID::S_WIDTH, GetSize(sig_new_s));
}
cell->setPort(ID::B, sig_new_b);
cell->setPort(ID::S, sig_new_s);
cell->setPort(TW::B, sig_new_b);
cell->setPort(TW::S, sig_new_s);
}
void fixup_muxes()

14
passes/proc/proc_memwr.cc
View file

@ -42,15 +42,15 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
priority_mask.set(prev_port_ids[i], State::S1);
prev_port_ids.push_back(port_id);
RTLIL::Cell *cell = mod->addCell(NEW_ID, ID($memwr_v2));
RTLIL::Cell *cell = mod->addCell(NEW_TWINE, ID($memwr_v2));
cell->attributes = memwr.attributes;
cell->setParam(ID::MEMID, Const(memwr.memid.str()));
cell->setParam(ID::ABITS, GetSize(memwr.address));
cell->setParam(ID::WIDTH, GetSize(memwr.data));
cell->setParam(ID::PORTID, port_id);
cell->setParam(ID::PRIORITY_MASK, priority_mask);
cell->setPort(ID::ADDR, memwr.address);
cell->setPort(ID::DATA, memwr.data);
cell->setPort(TW::ADDR, memwr.address);
cell->setPort(TW::DATA, memwr.data);
SigSpec enable = memwr.enable;
for (auto sr2 : proc->syncs) {
if (sr2->type == RTLIL::SyncType::ST0) {
@ -61,17 +61,17 @@ void proc_memwr(RTLIL::Module *mod, RTLIL::Process *proc, dict<IdString, int> &n
enable = mod->Mux(NEW_ID, enable, Const(State::S0, GetSize(enable)), sr2->signal);
}
}
cell->setPort(ID::EN, enable);
cell->setPort(TW::EN, enable);
if (sr->type == RTLIL::SyncType::STa) {
cell->setPort(ID::CLK, State::Sx);
cell->setPort(TW::CLK, State::Sx);
cell->setParam(ID::CLK_ENABLE, State::S0);
cell->setParam(ID::CLK_POLARITY, State::Sx);
} else if (sr->type == RTLIL::SyncType::STp) {
cell->setPort(ID::CLK, sr->signal);
cell->setPort(TW::CLK, sr->signal);
cell->setParam(ID::CLK_ENABLE, State::S1);
cell->setParam(ID::CLK_POLARITY, State::S1);
} else if (sr->type == RTLIL::SyncType::STn) {
cell->setPort(ID::CLK, sr->signal);
cell->setPort(TW::CLK, sr->signal);
cell->setParam(ID::CLK_ENABLE, State::S1);
cell->setParam(ID::CLK_POLARITY, State::S0);
} else {

32
passes/proc/proc_mux.cc
View file

@ -188,9 +188,9 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
eq_cell->parameters[ID::B_WIDTH] = RTLIL::Const(comp.size());
eq_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
eq_cell->setPort(ID::A, sig);
eq_cell->setPort(ID::B, comp);
eq_cell->setPort(ID::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
eq_cell->setPort(TW::A, sig);
eq_cell->setPort(TW::B, comp);
eq_cell->setPort(TW::Y, RTLIL::SigSpec(cmp_wire, cmp_wire->width++));
}
}
@ -211,8 +211,8 @@ RTLIL::SigSpec gen_cmp(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
any_cell->parameters[ID::A_WIDTH] = RTLIL::Const(cmp_wire->width);
any_cell->parameters[ID::Y_WIDTH] = RTLIL::Const(1);
any_cell->setPort(ID::A, cmp_wire);
any_cell->setPort(ID::Y, RTLIL::SigSpec(ctrl_wire));
any_cell->setPort(TW::A, cmp_wire);
any_cell->setPort(TW::Y, RTLIL::SigSpec(ctrl_wire));
}
return RTLIL::SigSpec(ctrl_wire);
@ -243,10 +243,10 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
apply_attrs(mux_cell, sw, cs);
mux_cell->parameters[ID::WIDTH] = RTLIL::Const(when_signal.size());
mux_cell->setPort(ID::A, else_signal);
mux_cell->setPort(ID::B, when_signal);
mux_cell->setPort(ID::S, ctrl_sig);
mux_cell->setPort(ID::Y, RTLIL::SigSpec(result_wire));
mux_cell->setPort(TW::A, else_signal);
mux_cell->setPort(TW::B, when_signal);
mux_cell->setPort(TW::S, ctrl_sig);
mux_cell->setPort(TW::Y, RTLIL::SigSpec(result_wire));
last_mux_cell = mux_cell;
return RTLIL::SigSpec(result_wire);
@ -255,24 +255,24 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s
void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector<RTLIL::SigSpec> &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode)
{
log_assert(last_mux_cell != NULL);
log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size());
log_assert(when_signal.size() == last_mux_cell->getPort(TW::A).size());
if (when_signal == last_mux_cell->getPort(ID::A))
if (when_signal == last_mux_cell->getPort(TW::A))
return;
RTLIL::SigSpec ctrl_sig = gen_cmp(mod, signal, compare, sw, cs, ifxmode);
log_assert(ctrl_sig.size() == 1);
last_mux_cell->type = ID($pmux);
RTLIL::SigSpec new_s = last_mux_cell->getPort(ID::S);
RTLIL::SigSpec new_s = last_mux_cell->getPort(TW::S);
new_s.append(ctrl_sig);
last_mux_cell->setPort(ID::S, new_s);
last_mux_cell->setPort(TW::S, new_s);
RTLIL::SigSpec new_b = last_mux_cell->getPort(ID::B);
RTLIL::SigSpec new_b = last_mux_cell->getPort(TW::B);
new_b.append(when_signal);
last_mux_cell->setPort(ID::B, new_b);
last_mux_cell->setPort(TW::B, new_b);
last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(ID::S).size();
last_mux_cell->parameters[ID::S_WIDTH] = last_mux_cell->getPort(TW::S).size();
}
const pool<SigBit> &get_full_case_bits(SnippetSwCache &swcache, RTLIL::SwitchRule *sw)

2
passes/proc/proc_rom.cc
View file

@ -151,7 +151,7 @@ struct RomWorker
}
// Ok, let's do it.
SigSpec rdata = module->addWire(NEW_ID, GetSize(lhs));
SigSpec rdata = module->addWire(NEW_TWINE, GetSize(lhs));
Mem mem(module, NEW_ID, GetSize(lhs), 0, 1 << abits);
mem.attributes = sw->attributes;

16
passes/sat/assertpmux.cc
View file

@ -59,9 +59,9 @@ struct AssertpmuxWorker
int width = cell->getParam(ID::WIDTH).as_int();
int numports = cell->type == ID($mux) ? 2 : cell->getParam(ID::S_WIDTH).as_int() + 1;
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_s = sigmap(cell->getPort(ID::S));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_s = sigmap(cell->getPort(TW::S));
for (int i = 0; i < numports; i++) {
SigSpec bits = i == 0 ? sig_a : sig_b.extract(width*(i-1), width);
@ -100,12 +100,12 @@ struct AssertpmuxWorker
if (muxport_actsignal.count(muxport) == 0) {
if (portidx == 0)
muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(ID::S));
muxport_actsignal[muxport] = module->LogicNot(NEW_ID, cell->getPort(TW::S));
else
muxport_actsignal[muxport] = cell->getPort(ID::S)[portidx-1];
muxport_actsignal[muxport] = cell->getPort(TW::S)[portidx-1];
}
output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(ID::Y)[bitidx])));
output.append(module->LogicAnd(NEW_ID, muxport_actsignal.at(muxport), get_bit_activation(cell->getPort(TW::Y)[bitidx])));
}
output.sort_and_unify();
@ -153,7 +153,7 @@ struct AssertpmuxWorker
int swidth = pmux->getParam(ID::S_WIDTH).as_int();
int cntbits = ceil_log2(swidth+1);
SigSpec sel = pmux->getPort(ID::S);
SigSpec sel = pmux->getPort(TW::S);
SigSpec cnt(State::S0, cntbits);
for (int i = 0; i < swidth; i++)
@ -166,7 +166,7 @@ struct AssertpmuxWorker
assert_en.append(module->LogicNot(NEW_ID, module->Initstate(NEW_ID)));
if (!flag_always)
assert_en.append(get_activation(pmux->getPort(ID::Y)));
assert_en.append(get_activation(pmux->getPort(TW::Y)));
if (GetSize(assert_en) == 0)
assert_en = State::S1;

40
passes/sat/async2sync.cc
View file

@ -97,30 +97,30 @@ struct Async2syncPass : public Pass {
if (initstate == State::S0)
initstate = module->Initstate(NEW_ID);
SigBit sig_en = cell->getPort(ID::EN);
cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
SigBit sig_en = cell->getPort(TW::EN);
cell->setPort(TW::EN, module->And(NEW_ID, sig_en, initstate));
} else {
SigBit sig_en = cell->getPort(ID::EN);
SigSpec sig_args = cell->getPort(ID::ARGS);
SigBit sig_en = cell->getPort(TW::EN);
SigSpec sig_args = cell->getPort(TW::ARGS);
bool trg_polarity = cell->getParam(ID(TRG_POLARITY)).as_bool();
SigBit sig_trg = cell->getPort(ID::TRG);
Wire *sig_en_q = module->addWire(NEW_ID);
Wire *sig_args_q = module->addWire(NEW_ID, GetSize(sig_args));
SigBit sig_trg = cell->getPort(TW::TRG);
Wire *sig_en_q = module->addWire(NEW_TWINE);
Wire *sig_args_q = module->addWire(NEW_TWINE, GetSize(sig_args));
sig_en_q->attributes.emplace(ID::init, State::S0);
module->addDff(NEW_ID, sig_trg, sig_en, sig_en_q, trg_polarity, cell->src_ref());
module->addDff(NEW_ID, sig_trg, sig_args, sig_args_q, trg_polarity, cell->src_ref());
cell->setPort(ID::EN, sig_en_q);
cell->setPort(ID::ARGS, sig_args_q);
cell->setPort(TW::EN, sig_en_q);
cell->setPort(TW::ARGS, sig_args_q);
if (cell->type == ID($check)) {
SigBit sig_a = cell->getPort(ID::A);
Wire *sig_a_q = module->addWire(NEW_ID);
SigBit sig_a = cell->getPort(TW::A);
Wire *sig_a_q = module->addWire(NEW_TWINE);
sig_a_q->attributes.emplace(ID::init, State::S1);
module->addDff(NEW_ID, sig_trg, sig_a, sig_a_q, trg_polarity, cell->src_ref());
cell->setPort(ID::A, sig_a_q);
cell->setPort(TW::A, sig_a_q);
}
}
cell->setPort(ID::TRG, SigSpec());
cell->setPort(TW::TRG, SigSpec());
cell->setParam(ID::TRG_ENABLE, false);
cell->setParam(ID::TRG_WIDTH, 0);
@ -152,8 +152,8 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q);
Wire *new_d = module->addWire(NEW_ID, ff.width);
Wire *new_q = module->addWire(NEW_ID, ff.width);
Wire *new_d = module->addWire(NEW_TWINE, ff.width);
Wire *new_q = module->addWire(NEW_TWINE, ff.width);
SigSpec sig_set = ff.sig_set;
SigSpec sig_clr = ff.sig_clr;
@ -217,8 +217,8 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q);
Wire *new_d = module->addWire(NEW_ID, ff.width);
Wire *new_q = module->addWire(NEW_ID, ff.width);
Wire *new_d = module->addWire(NEW_TWINE, ff.width);
Wire *new_q = module->addWire(NEW_TWINE, ff.width);
if (ff.pol_aload) {
if (!ff.is_fine) {
@ -250,7 +250,7 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q);
Wire *new_q = module->addWire(NEW_ID, ff.width);
Wire *new_q = module->addWire(NEW_TWINE, ff.width);
if (ff.pol_arst) {
if (!ff.is_fine)
@ -284,11 +284,11 @@ struct Async2syncPass : public Pass {
initvals.remove_init(ff.sig_q);
Wire *new_q = module->addWire(NEW_ID, ff.width);
Wire *new_q = module->addWire(NEW_TWINE, ff.width);
Wire *new_d;
if (ff.has_aload) {
new_d = module->addWire(NEW_ID, ff.width);
new_d = module->addWire(NEW_TWINE, ff.width);
if (ff.pol_aload) {
if (!ff.is_fine)
module->addMux(NEW_ID, new_q, ff.sig_ad, ff.sig_aload, new_d);

34
passes/sat/clk2fflogic.cc
View file

@ -72,7 +72,7 @@ struct Clk2fflogicPass : public Pass {
}
std::string sig_str = log_signal(sig);
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
Wire *sampled_sig = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = RTLIL::Const(State::S0, GetSize(sig));
if (is_fine)
module->addFfGate(NEW_ID, sig, sampled_sig);
@ -84,7 +84,7 @@ struct Clk2fflogicPass : public Pass {
SigSpec sample_control_edge(Module *module, SigSpec sig, bool polarity, bool is_fine) {
std::string sig_str = log_signal(sig);
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
Wire *sampled_sig = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = RTLIL::Const(polarity ? State::S1 : State::S0, GetSize(sig));
if (is_fine)
module->addFfGate(NEW_ID, sig, sampled_sig);
@ -98,7 +98,7 @@ struct Clk2fflogicPass : public Pass {
sig_str.erase(std::remove(sig_str.begin(), sig_str.end(), ' '), sig_str.end());
Wire *sampled_sig = module->addWire(NEW_ID_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
Wire *sampled_sig = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#sampled", sig_str)), GetSize(sig));
sampled_sig->attributes[ID::init] = init;
Cell *cell;
@ -187,7 +187,7 @@ struct Clk2fflogicPass : public Pass {
i, module, mem.memid.unescape(), log_signal(port.clk),
log_signal(port.addr), log_signal(port.data));
Wire *past_clk = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk))));
Wire *past_clk = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#past_clk#%s", mem.memid.unescape(), i, log_signal(port.clk))));
past_clk->attributes[ID::init] = port.clk_polarity ? State::S1 : State::S0;
module->addFf(NEW_ID, port.clk, past_clk);
@ -203,13 +203,13 @@ struct Clk2fflogicPass : public Pass {
SigSpec clock_edge = module->Eqx(NEW_ID, {port.clk, SigSpec(past_clk)}, clock_edge_pattern);
SigSpec en_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en));
SigSpec en_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#en_q", mem.memid.unescape(), i)), GetSize(port.en));
module->addFf(NEW_ID, port.en, en_q);
SigSpec addr_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr));
SigSpec addr_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#addr_q", mem.memid.unescape(), i)), GetSize(port.addr));
module->addFf(NEW_ID, port.addr, addr_q);
SigSpec data_q = module->addWire(NEW_ID_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data));
SigSpec data_q = module->addWire(NEW_TWINE_SUFFIX(stringf("%s#%d#data_q", mem.memid.unescape(), i)), GetSize(port.data));
module->addFf(NEW_ID, port.data, data_q);
port.clk = State::S0;
@ -243,13 +243,13 @@ struct Clk2fflogicPass : public Pass {
if (initstate == State::S0)
initstate = module->Initstate(NEW_ID);
SigBit sig_en = cell->getPort(ID::EN);
cell->setPort(ID::EN, module->And(NEW_ID, sig_en, initstate));
SigBit sig_en = cell->getPort(TW::EN);
cell->setPort(TW::EN, module->And(NEW_ID, sig_en, initstate));
} else {
SigBit sig_en = cell->getPort(ID::EN);
SigSpec sig_args = cell->getPort(ID::ARGS);
SigBit sig_en = cell->getPort(TW::EN);
SigSpec sig_args = cell->getPort(TW::ARGS);
Const trg_polarity = cell->getParam(ID(TRG_POLARITY));
SigSpec sig_trg = cell->getPort(ID::TRG);
SigSpec sig_trg = cell->getPort(TW::TRG);
SigSpec sig_trg_sampled;
@ -260,16 +260,16 @@ struct Clk2fflogicPass : public Pass {
SigBit sig_trg_combined = module->ReduceOr(NEW_ID, sig_trg_sampled);
cell->setPort(ID::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined));
cell->setPort(ID::ARGS, sig_args_sampled);
cell->setPort(TW::EN, module->And(NEW_ID, sig_en_sampled, sig_trg_combined));
cell->setPort(TW::ARGS, sig_args_sampled);
if (cell->type == ID($check)) {
SigBit sig_a = cell->getPort(ID::A);
SigBit sig_a = cell->getPort(TW::A);
SigBit sig_a_sampled = sample_data(module, sig_a, State::S1, false, false).sampled;
cell->setPort(ID::A, sig_a_sampled);
cell->setPort(TW::A, sig_a_sampled);
}
}
cell->setPort(ID::TRG, SigSpec());
cell->setPort(TW::TRG, SigSpec());
cell->setParam(ID::TRG_ENABLE, false);
cell->setParam(ID::TRG_WIDTH, 0);

8
passes/sat/cutpoint.cc
View file

@ -154,7 +154,7 @@ struct CutpointPass : public Pass {
RTLIL::Cell *scopeinfo = nullptr;
RTLIL::IdString cell_name(cell->name);
if (flag_scopeinfo && cell_name.isPublic()) {
auto scopeinfo = module->addCell(NEW_ID, ID($scopeinfo));
auto scopeinfo = module->addCell(NEW_TWINE, ID($scopeinfo));
scopeinfo->setParam(ID::TYPE, RTLIL::Const("blackbox"));
for (auto const &attr : cell->attributes)
@ -175,7 +175,7 @@ struct CutpointPass : public Pass {
for (auto wire : module->selected_wires()) {
if (wire->port_output) {
log("Making output wire %s.%s a cutpoint.\n", module, wire);
Wire *new_wire = module->addWire(NEW_ID, wire);
Wire *new_wire = module->addWire(NEW_TWINE, wire);
module->swap_names(wire, new_wire);
module->connect(new_wire, flag_undef ? Const(State::Sx, GetSize(new_wire)) : module->Anyseq(NEW_ID, GetSize(new_wire)));
wire->port_id = 0;
@ -202,7 +202,7 @@ struct CutpointPass : public Pass {
}
if (bit_count == 0)
continue;
SigSpec dummy = module->addWire(NEW_ID, bit_count);
SigSpec dummy = module->addWire(NEW_TWINE, bit_count);
bit_count = 0;
for (auto &bit : sig) {
if (cutpoint_bits.count(bit))
@ -226,7 +226,7 @@ struct CutpointPass : public Pass {
}
for (auto wire : rewrite_wires) {
Wire *new_wire = module->addWire(NEW_ID, wire);
Wire *new_wire = module->addWire(NEW_TWINE, wire);
SigSpec lhs, rhs, sig = sigmap(wire);
for (int i = 0; i < GetSize(sig); i++)
if (!cutpoint_bits.count(sig[i])) {

46
passes/sat/expose.cc
View file

@ -86,7 +86,7 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
for (auto cell : module->cells()) {
if (ct.cell_known(cell->type) && cell->hasPort(ID::Q))
dffsignals.add(sigmap(cell->getPort(ID::Q)));
dffsignals.add(sigmap(cell->getPort(TW::Q)));
}
for (auto w : module->wires()) {
@ -112,10 +112,10 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
info.cell = cell;
if (info.cell->type == ID($dff)) {
info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit();
info.bit_clk = sigmap(info.cell->getPort(TW::CLK)).as_bit();
info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(TW::D)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(TW::Q)).to_sigbit_vector();
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
bit_info[sig_q.at(i)] = info;
@ -124,12 +124,12 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
}
if (info.cell->type == ID($adff)) {
info.bit_clk = sigmap(info.cell->getPort(ID::CLK)).as_bit();
info.bit_arst = sigmap(info.cell->getPort(ID::ARST)).as_bit();
info.bit_clk = sigmap(info.cell->getPort(TW::CLK)).as_bit();
info.bit_arst = sigmap(info.cell->getPort(TW::ARST)).as_bit();
info.clk_polarity = info.cell->parameters.at(ID::CLK_POLARITY).as_bool();
info.arst_polarity = info.cell->parameters.at(ID::ARST_POLARITY).as_bool();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(ID::D)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(ID::Q)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_d = sigmap(info.cell->getPort(TW::D)).to_sigbit_vector();
std::vector<RTLIL::SigBit> sig_q = sigmap(info.cell->getPort(TW::Q)).to_sigbit_vector();
std::vector<RTLIL::State> arst_value = info.cell->parameters.at(ID::ARST_VALUE).to_bits();
for (size_t i = 0; i < sig_d.size(); i++) {
info.bit_d = sig_d.at(i);
@ -140,21 +140,21 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Mo
}
if (info.cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit();
info.bit_clk = sigmap(info.cell->getPort(TW::C)).as_bit();
info.clk_polarity = info.cell->type == ID($_DFF_P_);
info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit();
bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info;
info.bit_d = sigmap(info.cell->getPort(TW::D)).as_bit();
bit_info[sigmap(info.cell->getPort(TW::Q)).as_bit()] = info;
continue;
}
if (info.cell->type.size() == 10 && info.cell->type.begins_with("$_DFF_")) {
info.bit_clk = sigmap(info.cell->getPort(ID::C)).as_bit();
info.bit_arst = sigmap(info.cell->getPort(ID::R)).as_bit();
info.bit_clk = sigmap(info.cell->getPort(TW::C)).as_bit();
info.bit_arst = sigmap(info.cell->getPort(TW::R)).as_bit();
info.clk_polarity = info.cell->type[6] == 'P';
info.arst_polarity = info.cell->type[7] == 'P';
info.arst_value = info.cell->type[0] == '1' ? RTLIL::State::S1 : RTLIL::State::S0;
info.bit_d = sigmap(info.cell->getPort(ID::D)).as_bit();
bit_info[sigmap(info.cell->getPort(ID::Q)).as_bit()] = info;
info.bit_d = sigmap(info.cell->getPort(TW::D)).as_bit();
bit_info[sigmap(info.cell->getPort(TW::Q)).as_bit()] = info;
continue;
}
}
@ -546,11 +546,11 @@ struct ExposePass : public Pass {
for (auto &cell_name : info.cells) {
RTLIL::Cell *cell = module->cell(cell_name);
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort(ID::Q)).to_sigbit_vector();
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort(TW::Q)).to_sigbit_vector();
for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit))
bit = RTLIL::SigBit(wire_dummy_q, wire_dummy_q->width++);
cell->setPort(ID::Q, cell_q_bits);
cell->setPort(TW::Q, cell_q_bits);
}
RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
@ -578,12 +578,12 @@ struct ExposePass : public Pass {
if (info.clk_polarity) {
module->connect(RTLIL::SigSig(wire_c, info.sig_clk));
} else {
RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($not));
c->parameters[ID::A_SIGNED] = 0;
c->parameters[ID::A_WIDTH] = 1;
c->parameters[ID::Y_WIDTH] = 1;
c->setPort(ID::A, info.sig_clk);
c->setPort(ID::Y, wire_c);
c->setPort(TW::A, info.sig_clk);
c->setPort(TW::Y, wire_c);
}
if (info.sig_arst != RTLIL::State::Sm)
@ -594,12 +594,12 @@ struct ExposePass : public Pass {
if (info.arst_polarity) {
module->connect(RTLIL::SigSig(wire_r, info.sig_arst));
} else {
RTLIL::Cell *c = module->addCell(NEW_ID, ID($not));
RTLIL::Cell *c = module->addCell(NEW_TWINE, ID($not));
c->parameters[ID::A_SIGNED] = 0;
c->parameters[ID::A_WIDTH] = 1;
c->parameters[ID::Y_WIDTH] = 1;
c->setPort(ID::A, info.sig_arst);
c->setPort(ID::Y, wire_r);
c->setPort(TW::A, info.sig_arst);
c->setPort(TW::Y, wire_r);
}
RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);

4
passes/sat/fmcombine.cc
View file

@ -119,8 +119,8 @@ struct FmcombineWorker
Cell *gate = import_prim_cell(cell, "_gate");
if (opts.initeq) {
if (cell->is_builtin_ff()) {
SigSpec gold_q = gold->getPort(ID::Q);
SigSpec gate_q = gate->getPort(ID::Q);
SigSpec gold_q = gold->getPort(TW::Q);
SigSpec gate_q = gate->getPort(TW::Q);
SigSpec en = module->Initstate(NEW_ID);
SigSpec eq = module->Eq(NEW_ID, gold_q, gate_q);
module->addAssume(NEW_ID, eq, en);

4
passes/sat/fminit.cc
View file

@ -152,7 +152,7 @@ struct FminitPass : public Pass {
{
SigSpec insig = i > 0 ? ctrlsig.at(i-1) : State::S0;
Wire *outwire = module->addWire(NEW_ID);
Wire *outwire = module->addWire(NEW_TWINE);
outwire->attributes[ID::init] = i > 0 ? State::S0 : State::S1;
if (clksig.empty())
@ -166,7 +166,7 @@ struct FminitPass : public Pass {
if (i+1 == GetSize(it.second) && ctrlsig_latched[i].empty())
{
Wire *ffwire = module->addWire(NEW_ID);
Wire *ffwire = module->addWire(NEW_TWINE);
ffwire->attributes[ID::init] = State::S0;
SigSpec outsig = module->Or(NEW_ID, ffwire, ctrlsig[i]);

44
passes/sat/formalff.cc
View file

@ -53,7 +53,7 @@ struct InitValWorker
}
// Sign/Zero-extended indexing of individual port bits
static SigBit bit_in_port(RTLIL::Cell *cell, RTLIL::IdString port, RTLIL::IdString sign, int index)
static SigBit bit_in_port(RTLIL::Cell *cell, TwineRef port, RTLIL::IdString sign, int index)
{
auto sig_port = cell->getPort(port);
if (index < GetSize(sig_port))
@ -114,17 +114,17 @@ struct InitValWorker
{
if (cell->type == ID($mux))
{
SigBit sig_s = sigmap(cell->getPort(ID::S));
SigBit sig_s = sigmap(cell->getPort(TW::S));
State init_s = initconst(sig_s);
State init_y;
if (init_s == State::S0) {
init_y = initconst(cell->getPort(ID::A)[portbit.offset]);
init_y = initconst(cell->getPort(TW::A)[portbit.offset]);
} else if (init_s == State::S1) {
init_y = initconst(cell->getPort(ID::B)[portbit.offset]);
init_y = initconst(cell->getPort(TW::B)[portbit.offset]);
} else {
State init_a = initconst(cell->getPort(ID::A)[portbit.offset]);
State init_b = initconst(cell->getPort(ID::B)[portbit.offset]);
State init_a = initconst(cell->getPort(TW::A)[portbit.offset]);
State init_b = initconst(cell->getPort(TW::B)[portbit.offset]);
init_y = init_a == init_b ? init_a : State::Sx;
}
initconst_bits[bit] = init_y;
@ -156,8 +156,8 @@ struct InitValWorker
return State::S0;
}
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
State init_y = State::S1;
@ -246,21 +246,21 @@ struct InitValWorker
}
else if (cell->type == ID($mux))
{
State init_s = initconst(cell->getPort(ID::S).as_bit());
State init_s = initconst(cell->getPort(TW::S).as_bit());
if (init_s == State::S0 && portbit.port == ID::B)
continue;
if (init_s == State::S1 && portbit.port == ID::A)
continue;
auto sig_y = cell->getPort(ID::Y);
auto sig_y = cell->getPort(TW::Y);
if (is_initval_used(sig_y[portbit.offset]))
return true;
}
else if (cell->type.in(ID($and), ID($or)))
{
auto sig_a = cell->getPort(ID::A);
auto sig_b = cell->getPort(ID::B);
auto sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(TW::A);
auto sig_b = cell->getPort(TW::B);
auto sig_y = cell->getPort(TW::Y);
if (GetSize(sig_y) != GetSize(sig_a) || GetSize(sig_y) != GetSize(sig_b))
return true; // TODO handle more of this
State absorbing = cell->type == ID($and) ? State::S0 : State::S1;
@ -282,13 +282,13 @@ struct InitValWorker
if (portbit.port == ID::WR_DATA)
{
if (initconst(cell->getPort(ID::WR_EN)[portbit.offset]) == State::S0)
if (initconst(cell->getPort(TW::WR_EN)[portbit.offset]) == State::S0)
continue;
}
else if (portbit.port == ID::WR_ADDR)
{
int port = portbit.offset / cell->getParam(ID::ABITS).as_int();
auto sig_en = cell->getPort(ID::WR_EN);
auto sig_en = cell->getPort(TW::WR_EN);
int width = cell->getParam(ID::WIDTH).as_int();
for (int i = port * width; i < (port + 1) * width; i++)
@ -300,7 +300,7 @@ struct InitValWorker
else if (portbit.port == ID::RD_ADDR)
{
int port = portbit.offset / cell->getParam(ID::ABITS).as_int();
auto sig_en = cell->getPort(ID::RD_EN);
auto sig_en = cell->getPort(TW::RD_EN);
if (initconst(sig_en[port]) != State::S0)
return true;
@ -369,8 +369,8 @@ struct PropagateWorker
for (auto cell : module->cells()) {
if (cell->type.in(ID($not), ID($_NOT_))) {
auto sig_a = cell->getPort(ID::A);
auto &sig_y = cell->getPort(ID::Y);
auto sig_a = cell->getPort(TW::A);
auto &sig_y = cell->getPort(TW::Y);
sig_a.extend_u0(GetSize(sig_y), cell->hasParam(ID::A_SIGNED) && cell->parameters.at(ID::A_SIGNED).as_bool());
for (int i = 0; i < GetSize(sig_a); i++)
@ -445,7 +445,7 @@ struct PropagateWorker
if (add_attribute) {
Wire *clk_wire = bit.wire;
if (bit.offset != 0 || GetSize(bit.wire) != 1) {
clk_wire = module->addWire(NEW_ID);
clk_wire = module->addWire(NEW_TWINE);
module->connect(RTLIL::SigBit(clk_wire), bit);
}
clk_wire->attributes[ID::replaced_by_gclk] = polarity ? State::S1 : State::S0;
@ -717,8 +717,8 @@ struct FormalFfPass : public Pass {
continue;
}
SigBit gate_clock = sigmap(driver.cell->getPort(ID::A)[driver.offset]);
SigBit gate_enable = sigmap(driver.cell->getPort(ID::B)[driver.offset]);
SigBit gate_clock = sigmap(driver.cell->getPort(TW::A)[driver.offset]);
SigBit gate_enable = sigmap(driver.cell->getPort(TW::B)[driver.offset]);
std::swap(gate_clock, gate_enable);
for (int i = 0; i < 2; i++) {
@ -900,7 +900,7 @@ struct FormalFfPass : public Pass {
auto clk_wire = ff.sig_clk.is_wire() ? ff.sig_clk.as_wire() : nullptr;
if (clk_wire == nullptr) {
clk_wire = module->addWire(NEW_ID);
clk_wire = module->addWire(NEW_TWINE);
module->connect(RTLIL::SigBit(clk_wire), ff.sig_clk);
}

12
passes/sat/freduce.cc
View file

@ -632,7 +632,7 @@ struct FreduceWorker
bits_full_total += outputs.size();
}
if (inv_mode && cell->type == ID($_NOT_))
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(ID::A)), sigmap(cell->getPort(ID::Y))));
inv_pairs.insert(std::pair<RTLIL::SigBit, RTLIL::SigBit>(sigmap(cell->getPort(TW::A)), sigmap(cell->getPort(TW::Y))));
}
int bits_count = 0;
@ -716,7 +716,7 @@ struct FreduceWorker
log(" Connect slave%s: %s\n", grp[i].inverted ? " using inverter" : "", log_signal(grp[i].bit));
RTLIL::Cell *drv = drivers.at(grp[i].bit).first;
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID);
RTLIL::Wire *dummy_wire = module->addWire(NEW_TWINE);
for (auto &port : drv->connections_)
if (ct.cell_output(drv->type, port.first))
sigmap(port.second).replace(grp[i].bit, dummy_wire, &port.second);
@ -725,11 +725,11 @@ struct FreduceWorker
{
if (inv_sig.size() == 0)
{
inv_sig = module->addWire(NEW_ID);
inv_sig = module->addWire(NEW_TWINE);
RTLIL::Cell *inv_cell = module->addCell(NEW_ID, ID($_NOT_));
inv_cell->setPort(ID::A, grp[0].bit);
inv_cell->setPort(ID::Y, inv_sig);
RTLIL::Cell *inv_cell = module->addCell(NEW_TWINE, ID($_NOT_));
inv_cell->setPort(TW::A, grp[0].bit);
inv_cell->setPort(TW::Y, inv_sig);
}
module->connect(RTLIL::SigSig(grp[i].bit, inv_sig));

78
passes/sat/miter.cc
View file

@ -147,7 +147,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
SigSpec w = miter_module->addWire("\\cross_" + gold_wire->name.unescape(), gold_wire->width);
gold_cell->setPort(gold_wire->name, w);
if (flag_ignore_gold_x) {
RTLIL::SigSpec w_x = miter_module->addWire(NEW_ID, GetSize(w));
RTLIL::SigSpec w_x = miter_module->addWire(NEW_TWINE, GetSize(w));
for (int i = 0; i < GetSize(w); i++)
miter_module->addEqx(NEW_ID, w[i], State::Sx, w_x[i]);
RTLIL::SigSpec w_any = miter_module->And(NEW_ID, miter_module->Anyseq(NEW_ID, GetSize(w)), w_x);
@ -182,65 +182,65 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_ignore_gold_x)
{
RTLIL::SigSpec gold_x = miter_module->addWire(NEW_ID, w_gold->width);
RTLIL::SigSpec gold_x = miter_module->addWire(NEW_TWINE, w_gold->width);
for (int i = 0; i < w_gold->width; i++) {
RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_ID, ID($eqx));
RTLIL::Cell *eqx_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
eqx_cell->parameters[ID::A_WIDTH] = 1;
eqx_cell->parameters[ID::B_WIDTH] = 1;
eqx_cell->parameters[ID::Y_WIDTH] = 1;
eqx_cell->parameters[ID::A_SIGNED] = 0;
eqx_cell->parameters[ID::B_SIGNED] = 0;
eqx_cell->setPort(ID::A, RTLIL::SigSpec(w_gold, i));
eqx_cell->setPort(ID::B, RTLIL::State::Sx);
eqx_cell->setPort(ID::Y, gold_x.extract(i, 1));
eqx_cell->setPort(TW::A, RTLIL::SigSpec(w_gold, i));
eqx_cell->setPort(TW::B, RTLIL::State::Sx);
eqx_cell->setPort(TW::Y, gold_x.extract(i, 1));
}
RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_ID, w_gold->width);
RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_ID, w_gate->width);
RTLIL::SigSpec gold_masked = miter_module->addWire(NEW_TWINE, w_gold->width);
RTLIL::SigSpec gate_masked = miter_module->addWire(NEW_TWINE, w_gate->width);
RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_ID, ID($or));
RTLIL::Cell *or_gold_cell = miter_module->addCell(NEW_TWINE, ID($or));
or_gold_cell->parameters[ID::A_WIDTH] = w_gold->width;
or_gold_cell->parameters[ID::B_WIDTH] = w_gold->width;
or_gold_cell->parameters[ID::Y_WIDTH] = w_gold->width;
or_gold_cell->parameters[ID::A_SIGNED] = 0;
or_gold_cell->parameters[ID::B_SIGNED] = 0;
or_gold_cell->setPort(ID::A, w_gold);
or_gold_cell->setPort(ID::B, gold_x);
or_gold_cell->setPort(ID::Y, gold_masked);
or_gold_cell->setPort(TW::A, w_gold);
or_gold_cell->setPort(TW::B, gold_x);
or_gold_cell->setPort(TW::Y, gold_masked);
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_ID, ID($or));
RTLIL::Cell *or_gate_cell = miter_module->addCell(NEW_TWINE, ID($or));
or_gate_cell->parameters[ID::A_WIDTH] = w_gate->width;
or_gate_cell->parameters[ID::B_WIDTH] = w_gate->width;
or_gate_cell->parameters[ID::Y_WIDTH] = w_gate->width;
or_gate_cell->parameters[ID::A_SIGNED] = 0;
or_gate_cell->parameters[ID::B_SIGNED] = 0;
or_gate_cell->setPort(ID::A, w_gate);
or_gate_cell->setPort(ID::B, gold_x);
or_gate_cell->setPort(ID::Y, gate_masked);
or_gate_cell->setPort(TW::A, w_gate);
or_gate_cell->setPort(TW::B, gold_x);
or_gate_cell->setPort(TW::Y, gate_masked);
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
eq_cell->parameters[ID::Y_WIDTH] = 1;
eq_cell->parameters[ID::A_SIGNED] = 0;
eq_cell->parameters[ID::B_SIGNED] = 0;
eq_cell->setPort(ID::A, gold_masked);
eq_cell->setPort(ID::B, gate_masked);
eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
this_condition = eq_cell->getPort(ID::Y);
eq_cell->setPort(TW::A, gold_masked);
eq_cell->setPort(TW::B, gate_masked);
eq_cell->setPort(TW::Y, miter_module->addWire(NEW_TWINE));
this_condition = eq_cell->getPort(TW::Y);
}
else
{
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_ID, ID($eqx));
RTLIL::Cell *eq_cell = miter_module->addCell(NEW_TWINE, ID($eqx));
eq_cell->parameters[ID::A_WIDTH] = w_gold->width;
eq_cell->parameters[ID::B_WIDTH] = w_gate->width;
eq_cell->parameters[ID::Y_WIDTH] = 1;
eq_cell->parameters[ID::A_SIGNED] = 0;
eq_cell->parameters[ID::B_SIGNED] = 0;
eq_cell->setPort(ID::A, w_gold);
eq_cell->setPort(ID::B, w_gate);
eq_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
this_condition = eq_cell->getPort(ID::Y);
eq_cell->setPort(TW::A, w_gold);
eq_cell->setPort(TW::B, w_gate);
eq_cell->setPort(TW::Y, miter_module->addWire(NEW_TWINE));
this_condition = eq_cell->getPort(TW::Y);
}
if (flag_make_outcmp)
@ -261,31 +261,31 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
}
if (all_conditions.size() != 1) {
RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_ID, ID($reduce_and));
RTLIL::Cell *reduce_cell = miter_module->addCell(NEW_TWINE, ID($reduce_and));
reduce_cell->parameters[ID::A_WIDTH] = all_conditions.size();
reduce_cell->parameters[ID::Y_WIDTH] = 1;
reduce_cell->parameters[ID::A_SIGNED] = 0;
reduce_cell->setPort(ID::A, all_conditions);
reduce_cell->setPort(ID::Y, miter_module->addWire(NEW_ID));
all_conditions = reduce_cell->getPort(ID::Y);
reduce_cell->setPort(TW::A, all_conditions);
reduce_cell->setPort(TW::Y, miter_module->addWire(NEW_TWINE));
all_conditions = reduce_cell->getPort(TW::Y);
}
if (flag_make_assert) {
RTLIL::Cell *assert_cell = miter_module->addCell(NEW_ID, ID($assert));
assert_cell->setPort(ID::A, all_conditions);
assert_cell->setPort(ID::EN, State::S1);
RTLIL::Cell *assert_cell = miter_module->addCell(NEW_TWINE, ID($assert));
assert_cell->setPort(TW::A, all_conditions);
assert_cell->setPort(TW::EN, State::S1);
}
RTLIL::Wire *w_trigger = miter_module->addWire(ID(trigger));
w_trigger->port_output = true;
RTLIL::Cell *not_cell = miter_module->addCell(NEW_ID, ID($not));
RTLIL::Cell *not_cell = miter_module->addCell(NEW_TWINE, ID($not));
not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
not_cell->parameters[ID::A_WIDTH] = all_conditions.size();
not_cell->parameters[ID::Y_WIDTH] = w_trigger->width;
not_cell->parameters[ID::A_SIGNED] = 0;
not_cell->setPort(ID::A, all_conditions);
not_cell->setPort(ID::Y, w_trigger);
not_cell->setPort(TW::A, all_conditions);
not_cell->setPort(TW::Y, w_trigger);
miter_module->fixup_ports();
@ -356,8 +356,8 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
if (!cell->type.in(ID($assert), ID($assume)))
continue;
SigBit is_active = module->Nex(NEW_ID, cell->getPort(ID::A), State::S1);
SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(ID::EN), State::S1);
SigBit is_active = module->Nex(NEW_ID, cell->getPort(TW::A), State::S1);
SigBit is_enabled = module->Eqx(NEW_ID, cell->getPort(TW::EN), State::S1);
if (cell->type == ID($assert)) {
assert_signals.append(module->And(NEW_ID, is_active, is_enabled));
@ -374,7 +374,7 @@ void create_miter_assert(struct Pass *that, std::vector<std::string> args, RTLIL
}
else
{
Wire *assume_q = module->addWire(NEW_ID);
Wire *assume_q = module->addWire(NEW_TWINE);
assume_q->attributes[ID::init] = State::S0;
assume_signals.append(assume_q);

6
passes/sat/mutate.cc
View file

@ -659,7 +659,7 @@ void mutate_inv(Design *design, const mutate_opts_t &opts)
else
{
log("Add output inverter at %s.%s.%s[%d].\n", module, cell, opts.port.unescape(), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit inbit = module->addWire(NEW_TWINE);
SigBit outbit = module->Not(NEW_ID, inbit);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
bit = inbit;
@ -687,7 +687,7 @@ void mutate_const(Design *design, const mutate_opts_t &opts, bool one)
else
{
log("Add output constant %d at %s.%s.%s[%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit inbit = module->addWire(NEW_TWINE);
SigBit outbit = one ? State::S1 : State::S0;
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
bit = inbit;
@ -716,7 +716,7 @@ void mutate_cnot(Design *design, const mutate_opts_t &opts, bool one)
else
{
log("Add output cnot%d at %s.%s.%s[%d,%d].\n", one ? 1 : 0, module, cell, opts.port.unescape(), opts.portbit, opts.ctrlbit);
SigBit inbit = module->addWire(NEW_ID);
SigBit inbit = module->addWire(NEW_TWINE);
SigBit outbit = one ? module->Xor(NEW_ID, inbit, ctrl) : module->Xnor(NEW_ID, inbit, ctrl);
module->connect(bit, mutate_ctrl_mux(module, opts, inbit, outbit));
bit = inbit;

4
passes/sat/qbfsat.cc
View file

@ -111,7 +111,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) {
log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf);
RTLIL::Cell *hole_cell = hole_cell_it->second;
hole_sigbit = hole_cell->getPort(ID::Y)[hole_bit];
hole_sigbit = hole_cell->getPort(TW::Y)[hole_bit];
}
hole_assignments[hole_sigbit] = hole_value;
}
@ -165,7 +165,7 @@ void allconstify_inputs(RTLIL::Module *module, const pool<std::string> &input_wi
RTLIL::Cell *allconst = module->addCell("$allconst$" + n, "$allconst");
allconst->setParam(ID(WIDTH), input->width);
allconst->setPort(ID::Y, input);
allconst->setPort(TW::Y, input);
allconst->adopt_src_from(input);
input->port_input = false;
log("Replaced input %s with $allconst cell.\n", n);

6
passes/sat/qbfsat.h
View file

@ -69,7 +69,7 @@ struct QbfSolutionType {
pool<std::string> cell_src = module->design->src_leaves(cell);
auto pos = hole_to_value.find(cell_src);
if (pos != hole_to_value.end() && cell->type.in("$anyconst", "$anyseq")) {
RTLIL::SigSpec port_y = cell->getPort(ID::Y);
RTLIL::SigSpec port_y = cell->getPort(TW::Y);
for (int i = GetSize(port_y) - 1; i >= 0; --i) {
hole_loc_idx_to_sigbit[std::make_pair(pos->first, i)] = port_y[i];
anyconst_sigbits.insert(port_y[i]);
@ -125,7 +125,7 @@ struct QbfSolutionType {
//There is a question here: How exactly shall we identify holes?
//There are at least two reasonable options:
//1. By the source location of the $anyconst cells
//2. By the name(s) of the wire(s) connected to each SigBit of the $anyconst cell->getPort(ID::Y) SigSpec.
//2. By the name(s) of the wire(s) connected to each SigBit of the $anyconst cell->getPort(TW::Y) SigSpec.
//
//Option 1 has the benefit of being very precise. There is very limited potential for confusion, as long
//as the source attribute has been set. However, if the source attribute is not set, this won't work.
@ -143,7 +143,7 @@ struct QbfSolutionType {
//
//where '[', ']', and '=' are literal symbols, "location" is the $anyconst cell source location attribute,
//"bit" is the index of the $anyconst cell, "name" is the `wire->name` field of the SigBit corresponding
//to the current bit of the $anyconst cell->getPort(ID::Y), "offset" is the `offset` field of that same
//to the current bit of the $anyconst cell->getPort(TW::Y), "offset" is the `offset` field of that same
//SigBit, and "value", which is either '0' or '1', represents the assignment for that bit.
auto hole_loc_idx_to_sigbit = get_hole_loc_idx_sigbit_map(module);
for (auto &x : hole_to_value) {

4
passes/sat/sat.cc
View file

@ -268,7 +268,7 @@ struct SatHelper
if (set_init_undef && satgen.def_formal)
for (auto cell : module->cells())
if (cell->type == ID($anyinit))
forced_def.append(sigmap(cell->getPort(ID::Q)));
forced_def.append(sigmap(cell->getPort(TW::Q)));
for (auto wire : module->wires())
{
@ -1409,7 +1409,7 @@ struct SatPass : public Pass {
pool<Wire*> reg_wires;
for (auto cell : module->cells()) {
if (cell->type == ID($dff) || cell->type.begins_with("$_DFF_"))
for (auto bit : cell->getPort(ID::Q))
for (auto bit : cell->getPort(TW::Q))
if (bit.wire)
reg_wires.insert(bit.wire);
}

34
passes/sat/sim.cc
View file

@ -208,7 +208,7 @@ struct SimInstance
{
return std::make_tuple(
cell->getParam(ID::TRG_ENABLE).as_bool(), // Group by trigger
cell->getPort(ID::TRG),
cell->getPort(TW::TRG),
cell->getParam(ID::TRG_POLARITY),
-cell->getParam(ID::PRIORITY).as_int(), // Then sort by descending PRIORITY
cell
@ -365,8 +365,8 @@ struct SimInstance
auto &print = print_database.back();
print.cell = cell;
print.fmt.parse_rtlil(cell);
print.past_trg = Const(State::Sx, cell->getPort(ID::TRG).size());
print.past_args = Const(State::Sx, cell->getPort(ID::ARGS).size());
print.past_trg = Const(State::Sx, cell->getPort(TW::TRG).size());
print.past_args = Const(State::Sx, cell->getPort(TW::ARGS).size());
print.past_en = State::Sx;
print.initial_done = false;
}
@ -565,12 +565,12 @@ struct SimInstance
has_s = cell->hasPort(ID::S);
has_y = cell->hasPort(ID::Y);
if (has_a) sig_a = cell->getPort(ID::A);
if (has_b) sig_b = cell->getPort(ID::B);
if (has_c) sig_c = cell->getPort(ID::C);
if (has_d) sig_d = cell->getPort(ID::D);
if (has_s) sig_s = cell->getPort(ID::S);
if (has_y) sig_y = cell->getPort(ID::Y);
if (has_a) sig_a = cell->getPort(TW::A);
if (has_b) sig_b = cell->getPort(TW::B);
if (has_c) sig_c = cell->getPort(TW::C);
if (has_d) sig_d = cell->getPort(TW::D);
if (has_s) sig_s = cell->getPort(TW::S);
if (has_y) sig_y = cell->getPort(TW::Y);
if (shared->debug)
log("[%s] eval %s (%s)\n", hiername(), cell, cell->type.unescape());
@ -875,10 +875,10 @@ struct SimInstance
Cell *cell = print.cell;
bool triggered = false;
Const trg = get_state(cell->getPort(ID::TRG));
Const trg = get_state(cell->getPort(TW::TRG));
bool trg_en = cell->getParam(ID::TRG_ENABLE).as_bool();
Const en = get_state(cell->getPort(ID::EN));
Const args = get_state(cell->getPort(ID::ARGS));
Const en = get_state(cell->getPort(TW::EN));
Const args = get_state(cell->getPort(TW::ARGS));
bool sampled = trg_en && trg.size() > 0;
@ -934,8 +934,8 @@ struct SimInstance
if (cell->has_attribute(ID::src))
label = cell->get_src_attribute();
State a = get_state(cell->getPort(ID::A))[0];
State en = get_state(cell->getPort(ID::EN))[0];
State a = get_state(cell->getPort(TW::A))[0];
State en = get_state(cell->getPort(TW::EN))[0];
if (en == State::S1 && (cell->type == ID($cover) ? a == State::S1 : a != State::S1)) {
shared->triggered_assertions.emplace_back(shared->step, this, cell);
@ -964,7 +964,7 @@ struct SimInstance
void set_initstate_outputs(State state)
{
for (auto cell : initstate_database)
set_state(cell->getPort(ID::Y), state);
set_state(cell->getPort(TW::Y), state);
for (auto child : children)
child.second->set_initstate_outputs(state);
}
@ -1200,7 +1200,7 @@ struct SimInstance
for (auto cell : module->cells())
{
if (cell->type.in(ID($anyseq))) {
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
if (sig_y.is_wire()) {
bool found = false;
for(auto &item : fst_handles) {
@ -1834,7 +1834,7 @@ struct SimWorker : SimShared
if (!c)
log_warning("Wire/cell %s not present in module %s\n",escaped_s.unescape(),topmod);
else if (c->type.in(ID($anyconst), ID($anyseq))) {
SigSpec sig_y= c->getPort(ID::Y);
SigSpec sig_y= c->getPort(TW::Y);
if ((int)parts[1].size() != GetSize(sig_y))
log_error("Size of wire %s is different than provided data.\n", log_signal(sig_y));
top->set_state(sig_y, Const::from_string(parts[1]));

14
passes/sat/synthprop.cc
View file

@ -107,16 +107,16 @@ void SynthPropWorker::run()
int num = 0;
RTLIL::Wire *port_wire = data.first->wire(port_name);
if (!reset_name.empty() && data.first == module) {
port_wire = data.first->addWire(NEW_ID, data.second.names.size());
port_wire = data.first->addWire(NEW_TWINE, data.second.names.size());
output = port_wire;
}
pool<Wire*> connected;
for (auto cell : data.second.assertion_cells) {
if (cell->type == ID($assert)) {
RTLIL::Wire *neg_wire = data.first->addWire(NEW_ID);
RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
data.first->addNot(NEW_ID, cell->getPort(ID::A), neg_wire);
data.first->addAnd(NEW_ID, cell->getPort(ID::EN), neg_wire, result_wire);
RTLIL::Wire *neg_wire = data.first->addWire(NEW_TWINE);
RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE);
data.first->addNot(NEW_ID, cell->getPort(TW::A), neg_wire);
data.first->addAnd(NEW_ID, cell->getPort(TW::EN), neg_wire, result_wire);
if (!or_outputs) {
data.first->connect(SigBit(port_wire,num), result_wire);
} else {
@ -132,7 +132,7 @@ void SynthPropWorker::run()
if (!or_outputs) {
cell->setPort(port_name, SigChunk(port_wire, num, tracing_data[submod].names.size()));
} else {
RTLIL::Wire *result_wire = data.first->addWire(NEW_ID);
RTLIL::Wire *result_wire = data.first->addWire(NEW_TWINE);
cell->setPort(port_name, result_wire);
connected.emplace(result_wire);
}
@ -146,7 +146,7 @@ void SynthPropWorker::run()
if (!prev_wire) {
prev_wire = wire;
} else {
RTLIL::Wire *result = data.first->addWire(NEW_ID);
RTLIL::Wire *result = data.first->addWire(NEW_TWINE);
data.first->addOr(NEW_ID, prev_wire, wire, result);
prev_wire = result;
}

60
passes/techmap/abc.cc
View file

@ -476,8 +476,8 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_y);
@ -490,9 +490,9 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@ -526,10 +526,10 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@ -548,10 +548,10 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_c = cell->getPort(TW::C);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@ -570,11 +570,11 @@ bool AbcModuleState::extract_cell(const AbcSigMap &assign_map, RTLIL::Module *mo
if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{
RTLIL::SigSpec sig_a = cell->getPort(ID::A);
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_d = cell->getPort(ID::D);
RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
RTLIL::SigSpec sig_a = cell->getPort(TW::A);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_c = cell->getPort(TW::C);
RTLIL::SigSpec sig_d = cell->getPort(TW::D);
RTLIL::SigSpec sig_y = cell->getPort(TW::Y);
assign_map.apply(sig_a);
assign_map.apply(sig_b);
@ -1568,7 +1568,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
cell_stats[c->type.unescape()]++;
if (c->type.in(ID(ZERO), ID(ONE))) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
RTLIL::IdString name_y = remap_name(c->getPort(TW::Y).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = RTLIL::SigSpec(c->type == ID(ZERO) ? 0 : 1, 1);
connect(assign_map, module, conn);
@ -1576,8 +1576,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
}
if (c->type == ID(BUF)) {
RTLIL::SigSig conn;
RTLIL::IdString name_y = remap_name(c->getPort(ID::Y).as_wire()->name);
RTLIL::IdString name_a = remap_name(c->getPort(ID::A).as_wire()->name);
RTLIL::IdString name_y = remap_name(c->getPort(TW::Y).as_wire()->name);
RTLIL::IdString name_a = remap_name(c->getPort(TW::A).as_wire()->name);
conn.first = module->wire(name_y);
conn.second = module->wire(name_a);
connect(assign_map, module, conn);
@ -1678,7 +1678,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.pol_ce = en_polarity;
ff.sig_ce = en_sig;
}
RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
RTLIL::Const init = mapped_initvals(c->getPort(TW::Q));
if (had_init)
ff.val_init = init;
else
@ -1697,8 +1697,8 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.sig_srst = srst_sig;
ff.val_srst = init;
}
ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
ff.sig_d = module->wire(remap_name(c->getPort(TW::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(TW::Q).as_wire()->name));
RTLIL::Cell *cell = ff.emit();
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
design->select(module, cell);
@ -1729,7 +1729,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.pol_ce = en_polarity;
ff.sig_ce = en_sig;
}
RTLIL::Const init = mapped_initvals(c->getPort(ID::Q));
RTLIL::Const init = mapped_initvals(c->getPort(TW::Q));
if (had_init)
ff.val_init = init;
else
@ -1746,17 +1746,17 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
ff.sig_srst = srst_sig;
ff.val_srst = init;
}
ff.sig_d = module->wire(remap_name(c->getPort(ID::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(ID::Q).as_wire()->name));
ff.sig_d = module->wire(remap_name(c->getPort(TW::D).as_wire()->name));
ff.sig_q = module->wire(remap_name(c->getPort(TW::Q).as_wire()->name));
RTLIL::Cell *cell = ff.emit();
if (markgroups) cell->attributes[ID::abcgroup] = map_autoidx;
design->select(module, cell);
continue;
}
if (c->type == ID($lut) && GetSize(c->getPort(ID::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(ID::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(ID::Y).as_wire()->name));
if (c->type == ID($lut) && GetSize(c->getPort(TW::A)) == 1 && c->getParam(ID::LUT).as_int() == 2) {
SigSpec my_a = module->wire(remap_name(c->getPort(TW::A).as_wire()->name));
SigSpec my_y = module->wire(remap_name(c->getPort(TW::Y).as_wire()->name));
connect(assign_map, module, RTLIL::SigSig(my_a, my_y));
continue;
}

104
passes/techmap/abc9_ops.cc
View file

@ -132,7 +132,7 @@ void check(RTLIL::Design *design, bool dff_mode)
log_error("Whitebox '%s' with (* abc9_flop *) contains more than one $_DFF_[NP]_ cell.\n", derived_module);
found = true;
SigBit Q = derived_cell->getPort(ID::Q);
SigBit Q = derived_cell->getPort(TW::Q);
log_assert(GetSize(Q.wire) == 1);
if (!Q.wire->port_output)
@ -209,7 +209,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode)
if (derived_module->get_bool_attribute(ID::abc9_flop)) {
for (auto derived_cell : derived_module->cells())
if (derived_cell->type.in(ID($dff), ID($_DFF_N_), ID($_DFF_P_))) {
SigBit Q = derived_cell->getPort(ID::Q);
SigBit Q = derived_cell->getPort(TW::Q);
Const init = Q.wire->attributes.at(ID::init, State::Sx);
log_assert(GetSize(init) == 1);
@ -344,10 +344,10 @@ void prep_bypass(RTLIL::Design *design)
// For these new input ports driven by the replaced
// cell, then create a new simple-path specify entry:
// (input => output) = 0
auto specify = bypass_module->addCell(NEW_ID, ID($specify2));
specify->setPort(ID::EN, State::S1);
specify->setPort(ID::SRC, src);
specify->setPort(ID::DST, dst);
auto specify = bypass_module->addCell(NEW_TWINE, ID($specify2));
specify->setPort(TW::EN, State::S1);
specify->setPort(TW::SRC, src);
specify->setPort(TW::DST, dst);
specify->setParam(ID::FULL, 0);
specify->setParam(ID::SRC_WIDTH, GetSize(src));
specify->setParam(ID::DST_WIDTH, GetSize(dst));
@ -371,11 +371,11 @@ void prep_bypass(RTLIL::Design *design)
for (auto cell : inst_module->cells()) {
if (cell->type != ID($specify2))
continue;
auto EN = cell->getPort(ID::EN).as_bit();
auto EN = cell->getPort(TW::EN).as_bit();
SigBit newEN;
if (!EN.wire && EN != State::S1)
continue;
auto SRC = cell->getPort(ID::SRC);
auto SRC = cell->getPort(TW::SRC);
for (const auto &c : SRC.chunks())
if (c.wire && !c.wire->port_input) {
SRC = SigSpec();
@ -383,7 +383,7 @@ void prep_bypass(RTLIL::Design *design)
}
if (SRC.empty())
continue;
auto DST = cell->getPort(ID::DST);
auto DST = cell->getPort(TW::DST);
for (const auto &c : DST.chunks())
if (c.wire && !c.wire->port_output) {
DST = SigSpec();
@ -405,7 +405,7 @@ void prep_bypass(RTLIL::Design *design)
}
sig = std::move(new_sig);
};
auto specify = bypass_module->addCell(NEW_ID, cell);
auto specify = bypass_module->addCell(NEW_TWINE, cell);
specify->rewrite_sigspecs(rw);
}
bypass_module->fixup_ports();
@ -415,7 +415,7 @@ void prep_bypass(RTLIL::Design *design)
// original cell, but with additional inputs taken from the
// replaced cell
auto replace_cell = map_module->addCell(ID::_TECHMAP_REPLACE_, cell->type);
auto bypass_cell = map_module->addCell(NEW_ID, cell->type.str() + "_$abc9_byp");
auto bypass_cell = map_module->addCell(NEW_TWINE, cell->type.str() + "_$abc9_byp");
for (const auto &conn : cell->connections()) {
auto port = map_module->wire(conn.first);
if (cell->input(conn.first)) {
@ -493,7 +493,7 @@ void prep_dff_submod(RTLIL::Design *design)
if (cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
log_assert(!dff_cell);
dff_cell = cell;
Q = cell->getPort(ID::Q);
Q = cell->getPort(TW::Q);
log_assert(GetSize(Q.wire) == 1);
}
else if (cell->type.in(ID($specify3), ID($specrule)))
@ -503,17 +503,17 @@ void prep_dff_submod(RTLIL::Design *design)
// Add an always-enabled CE mux that drives $_DFF_[NP]_.D so that:
// (a) flop box will have an output
// (b) $_DFF_[NP]_.Q will be present as an input
SigBit D = module->addWire(NEW_ID);
module->addMuxGate(NEW_ID, dff_cell->getPort(ID::D), Q, State::S0, D);
dff_cell->setPort(ID::D, D);
SigBit D = module->addWire(NEW_TWINE);
module->addMuxGate(NEW_ID, dff_cell->getPort(TW::D), Q, State::S0, D);
dff_cell->setPort(TW::D, D);
// Rewrite $specify cells that end with $_DFF_[NP]_.Q
// to $_DFF_[NP]_.D since it will be moved into
// the submodule
for (auto cell : specify_cells) {
auto DST = cell->getPort(ID::DST);
auto DST = cell->getPort(TW::DST);
DST.replace(Q, D);
cell->setPort(ID::DST, DST);
cell->setPort(TW::DST, DST);
}
design->scratchpad_set_bool("abc9_ops.prep_dff_submod.did_something", true);
@ -593,7 +593,7 @@ void break_scc(RTLIL::Module *module)
for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
Wire *w = module->addWire(NEW_TWINE, GetSize(c.second));
I.append(w);
O.append(c.second);
c.second = w;
@ -603,11 +603,11 @@ void break_scc(RTLIL::Module *module)
if (!I.empty())
{
auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER));
auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER));
log_assert(GetSize(I) == GetSize(O));
cell->setParam(ID::WIDTH, GetSize(I));
cell->setPort(ID::I, std::move(I));
cell->setPort(ID::O, std::move(O));
cell->setPort(TW::I, std::move(I));
cell->setPort(TW::O, std::move(O));
}
}
@ -681,7 +681,7 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
auto rhs = cell->getPort(i.first.name);
if (offset >= rhs.size())
continue;
auto O = module->addWire(NEW_ID);
auto O = module->addWire(NEW_TWINE);
#ifndef NDEBUG
if (ys_debug(1)) {
@ -695,9 +695,9 @@ void prep_delays(RTLIL::Design *design, bool dff_mode)
r.first->second = delay_module->derive(design, {{ID::DELAY, d}});
log_assert(r.first->second.begins_with("$paramod$__ABC9_DELAY\\DELAY="));
}
auto box = module->addCell(NEW_ID, r.first->second);
box->setPort(ID::I, rhs[offset]);
box->setPort(ID::O, O);
auto box = module->addCell(NEW_TWINE, r.first->second);
box->setPort(TW::I, rhs[offset]);
box->setPort(TW::O, O);
rhs[offset] = O;
cell->setPort(i.first.name, rhs);
}
@ -819,7 +819,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
for (auto &c : cell->connections_) {
if (c.second.is_fully_const()) continue;
if (cell->output(c.first)) {
Wire *w = module->addWire(NEW_ID, GetSize(c.second));
Wire *w = module->addWire(NEW_TWINE, GetSize(c.second));
I.append(w);
O.append(c.second);
c.second = w;
@ -828,11 +828,11 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
}
if (!I.empty()) {
auto cell = module->addCell(NEW_ID, ID($__ABC9_SCC_BREAKER));
auto cell = module->addCell(NEW_TWINE, ID($__ABC9_SCC_BREAKER));
log_assert(GetSize(I) == GetSize(O));
cell->setParam(ID::WIDTH, GetSize(I));
cell->setPort(ID::I, std::move(I));
cell->setPort(ID::O, std::move(O));
cell->setPort(TW::I, std::move(I));
cell->setPort(TW::O, std::move(O));
// Rebuild topo ordering after inserting the additional breakers.
toposort.emplace();
@ -891,7 +891,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
auto &holes_cell = r.first->second;
if (r.second) {
if (box_module->get_bool_attribute(ID::whitebox)) {
holes_cell = holes_module->addCell(NEW_ID, cell->type);
holes_cell = holes_module->addCell(NEW_TWINE, cell->type);
if (box_module->has_processes())
Pass::call_on_module(design, box_module, "proc -noopt");
@ -1270,8 +1270,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// $_DFF_[NP]_ cells since flop box already has all the information
// we need to reconstruct them
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
SigBit Q = cell->getPort(ID::Q);
module->connect(Q, cell->getPort(ID::D));
SigBit Q = cell->getPort(TW::Q);
module->connect(Q, cell->getPort(TW::D));
module->remove(cell);
auto Qi = initmap(Q);
auto it = Qi.wire->attributes.find(ID::init);
@ -1295,8 +1295,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// Short out $_FF_ cells since the flop box already has
// all the information we need to reconstruct cell
if (dff_mode && mapped_cell->type == ID($_FF_)) {
SigBit D = mapped_cell->getPort(ID::D);
SigBit Q = mapped_cell->getPort(ID::Q);
SigBit D = mapped_cell->getPort(TW::D);
SigBit Q = mapped_cell->getPort(TW::Q);
if (D.wire)
D.wire = module->wire(remap_name(D.wire->name));
Q.wire = module->wire(remap_name(Q.wire->name));
@ -1308,15 +1308,15 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
toposort.node(mapped_cell->name);
if (mapped_cell->type == ID($_NOT_)) {
RTLIL::SigBit a_bit = mapped_cell->getPort(ID::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(ID::Y);
RTLIL::SigBit a_bit = mapped_cell->getPort(TW::A);
RTLIL::SigBit y_bit = mapped_cell->getPort(TW::Y);
bit_users[a_bit].insert(mapped_cell->name);
// Ignore inouts for topo ordering
if (y_bit.wire && !(y_bit.wire->port_input && y_bit.wire->port_output))
bit_drivers[y_bit].insert(mapped_cell->name);
if (!a_bit.wire) {
mapped_cell->setPort(ID::Y, module->addWire(NEW_ID));
mapped_cell->setPort(TW::Y, module->addWire(NEW_TWINE));
RTLIL::Wire *wire = module->wire(remap_name(y_bit.wire->name));
log_assert(wire);
module->connect(RTLIL::SigBit(wire, y_bit.offset), State::S1);
@ -1344,7 +1344,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
RTLIL::SigBit(module->wire(remap_name(a_bit.wire->name)), a_bit.offset),
RTLIL::SigBit(module->wire(remap_name(y_bit.wire->name)), y_bit.offset),
RTLIL::Const::from_string("01"));
bit2sinks[cell->getPort(ID::A)].push_back(cell);
bit2sinks[cell->getPort(TW::A)].push_back(cell);
cell_stats[ID($lut)]++;
}
else
@ -1560,8 +1560,8 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
if (it == not2drivers.end())
continue;
RTLIL::Cell *driver_lut = it->second;
RTLIL::SigBit a_bit = not_cell->getPort(ID::A);
RTLIL::SigBit y_bit = not_cell->getPort(ID::Y);
RTLIL::SigBit a_bit = not_cell->getPort(TW::A);
RTLIL::SigBit y_bit = not_cell->getPort(TW::Y);
RTLIL::Const driver_mask;
a_bit.wire = module->wire(remap_name(a_bit.wire->name));
@ -1577,7 +1577,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
// Push downstream LUTs past inverter
for (auto sink_cell : jt->second) {
SigSpec A = sink_cell->getPort(ID::A);
SigSpec A = sink_cell->getPort(TW::A);
RTLIL::Const mask = sink_cell->getParam(ID::LUT);
int index = 0;
for (; index < GetSize(A); index++)
@ -1594,7 +1594,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
i += 1 << (index+1);
}
A[index] = y_bit;
sink_cell->setPort(ID::A, A);
sink_cell->setPort(TW::A, A);
sink_cell->setParam(ID::LUT, mask);
}
@ -1610,7 +1610,7 @@ clone_lut:
else if (b == RTLIL::State::S1) b = RTLIL::State::S0;
}
auto cell = module->addLut(NEW_ID,
driver_lut->getPort(ID::A),
driver_lut->getPort(TW::A),
y_bit,
driver_mask);
for (auto &bit : cell->connections_.at(ID::A)) {
@ -1636,7 +1636,7 @@ static void replace_zbufs(Design *design)
for (auto cell : mod->cells()) {
if (cell->type != ID($buf))
continue;
auto &sig = cell->getPort(ID::A);
auto &sig = cell->getPort(TW::A);
for (int i = 0; i < GetSize(sig); ++i) {
if (sig[i] == State::Sz) {
zbufs.push_back(cell);
@ -1646,20 +1646,20 @@ static void replace_zbufs(Design *design)
}
for (auto cell : zbufs) {
auto sig = cell->getPort(ID::A);
auto sig = cell->getPort(TW::A);
for (int i = 0; i < GetSize(sig); ++i) {
if (sig[i] == State::Sz) {
Wire *w = mod->addWire(NEW_ID);
Cell *ud = mod->addCell(NEW_ID, ID($tribuf));
Wire *w = mod->addWire(NEW_TWINE);
Cell *ud = mod->addCell(NEW_TWINE, ID($tribuf));
ud->set_bool_attribute(ID::aiger2_zbuf);
ud->setParam(ID::WIDTH, 1);
ud->setPort(ID::Y, w);
ud->setPort(ID::EN, State::S0);
ud->setPort(ID::A, State::S0);
ud->setPort(TW::Y, w);
ud->setPort(TW::EN, State::S0);
ud->setPort(TW::A, State::S0);
sig[i] = w;
}
}
cell->setPort(ID::A, sig);
cell->setPort(TW::A, sig);
}
mod->bufNormalize();
@ -1680,7 +1680,7 @@ static void restore_zbufs(Design *design)
to_remove.push_back(cell);
for (auto cell : to_remove) {
SigSpec sig_y = cell->getPort(ID::Y);
SigSpec sig_y = cell->getPort(TW::Y);
mod->addBuf(NEW_ID, Const(State::Sz, GetSize(sig_y)), sig_y);
mod->remove(cell);
}

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