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https://github.com/YosysHQ/yosys
synced 2026-07-15 11:45:41 +00:00
WIP
This commit is contained in:
Emil J. Tywoniak
parent
015ab4e45b
commit
f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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@ -10,7 +10,7 @@ using namespace RTLIL;
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template class CellAdderMixin<Patch>;
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Cell* Patch::addCell(IdString name, IdString type) {
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Cell* Patch::addCell(TwineRef name, IdString type) {
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cells_.push_back(std::make_unique<Cell>(Cell::ConstructToken{}));
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Cell* cell = cells_.back().get();
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@ -20,7 +20,11 @@ Cell* Patch::addCell(IdString name, IdString type) {
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return cell;
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}
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Wire* Patch::addWire(IdString name, int width) {
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Cell* Patch::addCell(Twine &&name, IdString type) {
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return addCell(twine_staging.add(std::move(name)), type);
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}
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Wire* Patch::addWire(TwineRef name, int width) {
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wires_.push_back(std::make_unique<Wire>(Wire::ConstructToken{}));
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Wire* wire = wires_.back().get();
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@ -30,11 +34,15 @@ Wire* Patch::addWire(IdString name, int width) {
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return wire;
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}
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Wire* Patch::addWire(Twine &&name, int width) {
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return addWire(twine_staging.add(std::move(name)), width);
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}
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// TODO code golf
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RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
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RTLIL::Wire *RTLIL::Patch::addWire(TwineRef name, const RTLIL::Wire *other)
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{
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RTLIL::Wire *wire = addWire(std::move(name));
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RTLIL::Wire *wire = addWire(name);
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wire->width = other->width;
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wire->start_offset = other->start_offset;
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wire->port_id = other->port_id;
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@ -46,32 +54,44 @@ RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *othe
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return wire;
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}
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RTLIL::Wire *RTLIL::Patch::addWire(Twine &&name, const RTLIL::Wire *other)
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{
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return addWire(twine_staging.add(std::move(name)), other);
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}
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TwineRef Patch::new_name(const std::string *prefix) {
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TwineRef pref;
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if (auto it = staged_prefix_cache_.find(prefix); it != staged_prefix_cache_.end())
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pref = it->second;
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else
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pref = staged_prefix_cache_[prefix] = twine_staging.add(Twine{*prefix});
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return twine_staging.add(Twine{Twine::Suffix{pref, std::to_string(autoidx++)}});
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}
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Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
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Wire* raw = wire.release();
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IdString name = staged_wire_names_.at(raw);
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TwineRef id = twine_staging.resolve(staged_wire_names_.at(raw));
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staged_wire_names_.erase(raw);
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TwineRef id = mod->design->twines.intern(name.str());
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mod->design->obj_set_name_id(raw, id);
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mod->design->twines.release(id);
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mod->wires_[raw->meta_->name_id] = raw;
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raw->meta_->name = id;
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mod->wires_[raw->meta_->name] = raw;
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raw->module = mod;
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return raw;
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}
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Cell* Patch::commit_cell(std::unique_ptr<Cell> cell) {
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Cell* raw = cell.release();
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IdString name = staged_cell_names_.at(raw);
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TwineRef id = twine_staging.resolve(staged_cell_names_.at(raw));
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staged_cell_names_.erase(raw);
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TwineRef id = mod->design->twines.intern(name.str());
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mod->design->obj_set_name_id(raw, id);
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mod->design->twines.release(id);
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raw->meta_->name = id;
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raw->module = mod;
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mod->cells_[raw->meta_->name_id] = raw;
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mod->cells_[raw->meta_->name] = raw;
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raw->initIndex();
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return raw;
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}
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std::vector<Cell*> Patch::commit_staged() {
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twine_staging.commit_into(mod->design->twines);
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staged_prefix_cache_.clear();
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std::vector<Cell*> committed;
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committed.reserve(cells_.size());
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for (auto& cell : cells_) {
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@ -86,6 +106,12 @@ std::vector<Cell*> Patch::commit_staged() {
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}
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namespace {
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std::string port_name(Cell* cell, TwineRef port) {
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if (cell->module && cell->module->design)
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return cell->module->design->twines.str(port);
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return "<port#" + std::to_string(port) + ">";
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}
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void apply_src(Module* mod, Cell* root, const std::vector<Cell*>& extras,
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const std::vector<Cell*>& targets, Cell* merge_src_into)
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{
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@ -107,25 +133,24 @@ namespace {
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push(merge_src_into);
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if (ids.empty())
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return;
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TwineRef merged = pool.concat(std::span<const TwineRef>{ids});
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TwineRef merged = ids.size() == 1 ? ids[0] : pool.add(Twine{std::move(ids)});
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if (ys_debug()) {
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log_debug("twine: merge yields %s (pool size %zu)\n",
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pool.format_ref(merged).c_str(), pool.size());
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pool.str(merged).c_str(), pool.backing.size());
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if (ys_debug(2))
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pool.dump("twine pool state");
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pool.dump();
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}
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for (Cell* c : targets)
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c->set_src_id(merged);
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if (merge_src_into)
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merge_src_into->set_src_id(merged);
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pool.release(merged);
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}
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// Verifies via newcelltypes that root_cell has exactly one output port
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// and that it matches `expected_port`.
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void assert_single_output(Cell* root_cell, IdString expected_port) {
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void assert_single_output(Cell* root_cell, TwineRef expected_port) {
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int count = 0;
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IdString found;
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TwineRef found = Twine::Null;
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for (auto &[port, sig] : root_cell->connections()) {
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if (root_cell->output(port)) {
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found = port;
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@ -138,11 +163,11 @@ namespace {
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if (found != expected_port)
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log_error("Patch: cell %s of type %s sole output port %s does not match patched port %s\n",
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log_id(root_cell->name), log_id(root_cell->type),
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log_id(found), log_id(expected_port));
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port_name(root_cell, found).c_str(), port_name(root_cell, expected_port).c_str());
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}
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}
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void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
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void Patch::patch(Cell* root_cell, TwineRef old_port, SigSpec new_sig,
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const std::vector<Cell*>& extras, Cell* merge_src_into)
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{
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assert_single_output(root_cell, old_port);
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@ -150,11 +175,11 @@ void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
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SigSpec old_sig = root_cell->getPort(old_port);
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if (old_sig.size() != new_sig.size())
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log_error("patch size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
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log_id(root_cell->name), log_id(old_port),
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log_id(root_cell->name), port_name(root_cell, old_port).c_str(),
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old_sig.size(), log_signal(old_sig),
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new_sig.size(), log_signal(new_sig));
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log_debug("patching %s %s which is %s with %s\n",
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log_id(root_cell->name), log_id(old_port),
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log_id(root_cell->name), port_name(root_cell, old_port).c_str(),
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log_signal(old_sig), log_signal(new_sig));
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std::vector<Cell*> committed = commit_staged();
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@ -174,22 +199,22 @@ void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
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}
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void Patch::patch_ports(Cell* root_cell,
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const std::vector<std::pair<IdString, SigSpec>>& port_replacements,
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const std::vector<std::pair<TwineRef, SigSpec>>& port_replacements,
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const std::vector<Cell*>& extras, Cell* merge_src_into)
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{
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// Verify each listed port is an output of root_cell and that the
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// replacements cover every output port of root_cell.
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pool<IdString> listed;
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pool<TwineRef> listed;
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std::vector<SigSpec> old_sigs;
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old_sigs.reserve(port_replacements.size());
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for (auto &[port, new_sig] : port_replacements) {
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if (!root_cell->output(port))
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log_error("patch_ports: cell %s of type %s port %s is not an output\n",
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log_id(root_cell->name), log_id(root_cell->type), log_id(port));
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log_id(root_cell->name), log_id(root_cell->type), port_name(root_cell, port).c_str());
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SigSpec old_sig = root_cell->getPort(port);
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if (old_sig.size() != new_sig.size())
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log_error("patch_ports size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
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log_id(root_cell->name), log_id(port),
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log_id(root_cell->name), port_name(root_cell, port).c_str(),
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old_sig.size(), log_signal(old_sig),
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new_sig.size(), log_signal(new_sig));
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listed.insert(port);
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@ -198,7 +223,7 @@ void Patch::patch_ports(Cell* root_cell,
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for (auto &[port, sig] : root_cell->connections())
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if (root_cell->output(port) && !listed.count(port))
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log_error("patch_ports: cell %s of type %s has output port %s not in port_replacements\n",
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log_id(root_cell->name), log_id(root_cell->type), log_id(port));
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log_id(root_cell->name), log_id(root_cell->type), port_name(root_cell, port).c_str());
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std::vector<Cell*> committed = commit_staged();
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apply_src(mod, root_cell, extras, committed, merge_src_into);
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@ -207,7 +232,7 @@ void Patch::patch_ports(Cell* root_cell,
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// shell before we wire old_sigs to new_sigs. Doing this first ensures
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// the old port signals are not briefly double-driven by root_cell and
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// the new connection.
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std::vector<IdString> all_ports;
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std::vector<TwineRef> all_ports;
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all_ports.reserve(root_cell->connections().size());
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for (auto &[port, sig] : root_cell->connections())
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all_ports.push_back(port);
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@ -226,6 +251,8 @@ void Patch::patch_ports(Cell* root_cell,
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}
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void Patch::commit_inheriting_src(Cell* src_source) {
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twine_staging.commit_into(mod->design->twines);
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staged_prefix_cache_.clear();
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for (auto& cell : cells_) {
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cell->fixup_parameters();
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Cell *committed = commit_cell(std::move(cell));
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