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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions

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@ -586,9 +586,9 @@ struct NewCellTypes {
for (auto wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
inputs.insert(wire->meta_->name_id);
inputs.insert(wire->meta_->name);
if (wire->port_output)
outputs.insert(wire->meta_->name_id);
outputs.insert(wire->meta_->name);
}
setup_type(module->name, inputs, outputs);
}