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WIP
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203 changed files with 4575 additions and 4481 deletions
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@ -586,9 +586,9 @@ struct NewCellTypes {
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for (auto wire_name : module->ports) {
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RTLIL::Wire *wire = module->wire(wire_name);
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if (wire->port_input)
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inputs.insert(wire->meta_->name_id);
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inputs.insert(wire->meta_->name);
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if (wire->port_output)
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outputs.insert(wire->meta_->name_id);
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outputs.insert(wire->meta_->name);
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}
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setup_type(module->name, inputs, outputs);
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}
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