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https://github.com/YosysHQ/yosys
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WIP
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parent
015ab4e45b
commit
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203 changed files with 4575 additions and 4481 deletions
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@ -84,7 +84,7 @@ struct Macc
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void from_cell_v1(RTLIL::Cell *cell)
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{
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RTLIL::SigSpec port_a = cell->getPort(ID::A);
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RTLIL::SigSpec port_a = cell->getPort(TW::A);
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terms.clear();
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@ -129,7 +129,7 @@ struct Macc
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terms.push_back(this_port);
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}
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for (auto bit : cell->getPort(ID::B))
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for (auto bit : cell->getPort(TW::B))
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terms.push_back(term_t{{bit}, {}, false, false});
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log_assert(config_cursor == config_width);
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@ -144,9 +144,9 @@ struct Macc
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}
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log_assert(cell->type == ID($macc_v2));
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RTLIL::SigSpec port_a = cell->getPort(ID::A);
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RTLIL::SigSpec port_b = cell->getPort(ID::B);
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RTLIL::SigSpec port_c = cell->getPort(ID::C);
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RTLIL::SigSpec port_a = cell->getPort(TW::A);
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RTLIL::SigSpec port_b = cell->getPort(TW::B);
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RTLIL::SigSpec port_c = cell->getPort(TW::C);
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terms.clear();
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@ -255,9 +255,9 @@ struct Macc
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cell->setParam(ID::A_WIDTHS, a_widths);
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cell->setParam(ID::B_WIDTHS, b_widths);
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cell->setParam(ID::C_WIDTHS, c_widths);
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cell->setPort(ID::A, a);
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cell->setPort(ID::B, b);
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cell->setPort(ID::C, c);
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cell->setPort(TW::A, a);
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cell->setPort(TW::B, b);
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cell->setPort(TW::C, c);
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}
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bool eval(RTLIL::Const &result) const
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