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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions

View file

@ -84,7 +84,7 @@ struct Macc
void from_cell_v1(RTLIL::Cell *cell)
{
RTLIL::SigSpec port_a = cell->getPort(ID::A);
RTLIL::SigSpec port_a = cell->getPort(TW::A);
terms.clear();
@ -129,7 +129,7 @@ struct Macc
terms.push_back(this_port);
}
for (auto bit : cell->getPort(ID::B))
for (auto bit : cell->getPort(TW::B))
terms.push_back(term_t{{bit}, {}, false, false});
log_assert(config_cursor == config_width);
@ -144,9 +144,9 @@ struct Macc
}
log_assert(cell->type == ID($macc_v2));
RTLIL::SigSpec port_a = cell->getPort(ID::A);
RTLIL::SigSpec port_b = cell->getPort(ID::B);
RTLIL::SigSpec port_c = cell->getPort(ID::C);
RTLIL::SigSpec port_a = cell->getPort(TW::A);
RTLIL::SigSpec port_b = cell->getPort(TW::B);
RTLIL::SigSpec port_c = cell->getPort(TW::C);
terms.clear();
@ -255,9 +255,9 @@ struct Macc
cell->setParam(ID::A_WIDTHS, a_widths);
cell->setParam(ID::B_WIDTHS, b_widths);
cell->setParam(ID::C_WIDTHS, c_widths);
cell->setPort(ID::A, a);
cell->setPort(ID::B, b);
cell->setPort(ID::C, c);
cell->setPort(TW::A, a);
cell->setPort(TW::B, b);
cell->setPort(TW::C, c);
}
bool eval(RTLIL::Const &result) const