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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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38
kernel/cellaigs.cc
View file

@ -91,7 +91,7 @@ struct AigMaker
return node2index(node);
}
int inport(IdString portname, int portbit = 0, bool inverter = false)
int inport(TwineRef portname, int portbit = 0, bool inverter = false)
{
if (portbit >= GetSize(cell->getPort(portname))) {
if (cell->parameters.count(portname.str() + "_SIGNED") && cell->getParam(portname.str() + "_SIGNED").as_bool())
@ -106,7 +106,7 @@ struct AigMaker
return node2index(node);
}
vector<int> inport_vec(IdString portname, int width)
vector<int> inport_vec(TwineRef portname, int width)
{
vector<int> vec;
for (int i = 0; i < width; i++)
@ -114,7 +114,7 @@ struct AigMaker
return vec;
}
int not_inport(IdString portname, int portbit = 0)
int not_inport(TwineRef portname, int portbit = 0)
{
return inport(portname, portbit, true);
}
@ -244,20 +244,20 @@ struct AigMaker
return Y;
}
void outport(int node, IdString portname, int portbit = 0)
void outport(int node, TwineRef portname, int portbit = 0)
{
if (portbit < GetSize(cell->getPort(portname)))
aig->nodes.at(node).outports.push_back(pair<IdString, int>(portname, portbit));
}
void outport_bool(int node, IdString portname)
void outport_bool(int node, TwineRef portname)
{
outport(node, portname);
for (int i = 1; i < GetSize(cell->getPort(portname)); i++)
outport(bool_node(false), portname, i);
}
void outport_vec(const vector<int> &vec, IdString portname)
void outport_vec(const vector<int> &vec, TwineRef portname)
{
for (int i = 0; i < GetSize(vec); i++)
outport(vec.at(i), portname, i);
@ -304,7 +304,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($not), ID($_NOT_), ID($pos), ID($buf), ID($_BUF_)))
{
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
int A = mk.inport(ID::A, i);
int Y = cell->type.in(ID($not), ID($_NOT_)) ? mk.not_gate(A) : A;
mk.outport(Y, ID::Y, i);
@ -314,7 +314,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_), ID($or), ID($_OR_), ID($_NOR_), ID($xor), ID($xnor), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
int A = mk.inport(ID::A, i);
int B = mk.inport(ID::B, i);
int Y = cell->type.in(ID($and), ID($_AND_)) ? mk.and_gate(A, B) :
@ -333,7 +333,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
{
int S = mk.inport(ID::S);
for (int i = 0; i < GetSize(cell->getPort(ID::Y)); i++) {
for (int i = 0; i < GetSize(cell->getPort(TW::Y)); i++) {
int A = mk.inport(ID::A, i);
int B = mk.inport(ID::B, i);
int Y = mk.mux_gate(A, B, S);
@ -347,7 +347,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool)))
{
int Y = mk.inport(ID::A, 0);
for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++) {
for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++) {
int A = mk.inport(ID::A, i);
if (cell->type == ID($reduce_and)) Y = mk.and_gate(A, Y);
if (cell->type == ID($reduce_or)) Y = mk.or_gate(A, Y);
@ -358,7 +358,7 @@ Aig::Aig(Cell *cell)
if (cell->type == ID($reduce_xnor))
Y = mk.not_gate(Y);
mk.outport(Y, ID::Y, 0);
for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++)
mk.outport(mk.bool_node(false), ID::Y, i);
goto optimize;
}
@ -366,11 +366,11 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($logic_not), ID($logic_and), ID($logic_or)))
{
int A = mk.inport(ID::A, 0), Y = -1;
for (int i = 1; i < GetSize(cell->getPort(ID::A)); i++)
for (int i = 1; i < GetSize(cell->getPort(TW::A)); i++)
A = mk.or_gate(mk.inport(ID::A, i), A);
if (cell->type.in(ID($logic_and), ID($logic_or))) {
int B = mk.inport(ID::B, 0);
for (int i = 1; i < GetSize(cell->getPort(ID::B)); i++)
for (int i = 1; i < GetSize(cell->getPort(TW::B)); i++)
B = mk.or_gate(mk.inport(ID::B, i), B);
if (cell->type == ID($logic_and)) Y = mk.and_gate(A, B);
if (cell->type == ID($logic_or)) Y = mk.or_gate(A, B);
@ -383,7 +383,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($add), ID($sub)))
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
int carry = mk.bool_node(false);
@ -399,8 +399,8 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($lt), ID($gt), ID($le), ID($ge)))
{
int width = std::max(GetSize(cell->getPort(ID::A)),
GetSize(cell->getPort(ID::B))) + 1;
int width = std::max(GetSize(cell->getPort(TW::A)),
GetSize(cell->getPort(TW::B))) + 1;
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
@ -412,14 +412,14 @@ Aig::Aig(Cell *cell)
n = mk.not_gate(n);
vector<int> Y = mk.adder(A, B, carry);
mk.outport(Y.back(), ID::Y);
for (int i = 1; i < GetSize(cell->getPort(ID::Y)); i++)
for (int i = 1; i < GetSize(cell->getPort(TW::Y)); i++)
mk.outport(mk.bool_node(false), ID::Y, i);
goto optimize;
}
if (cell->type == ID($alu))
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
int carry = mk.inport(ID::CI);
@ -438,7 +438,7 @@ Aig::Aig(Cell *cell)
if (cell->type.in(ID($eq), ID($ne)))
{
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
vector<int> A = mk.inport_vec(ID::A, width);
vector<int> B = mk.inport_vec(ID::B, width);
int Y = mk.bool_node(false);

2
kernel/cellaigs.h
View file

@ -26,7 +26,7 @@ YOSYS_NAMESPACE_BEGIN
struct AigNode
{
IdString portname;
TwineRef portname;
int portbit;
bool inverter;
int left_parent, right_parent;

80
kernel/celledges.cc
View file

@ -25,8 +25,8 @@ PRIVATE_NAMESPACE_BEGIN
void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = (cell->type != ID($buf)) && cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int y_width = GetSize(cell->getPort(TW::Y));
for (int i = 0; i < y_width; i++)
{
@ -40,9 +40,9 @@ void bitwise_unary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int y_width = GetSize(cell->getPort(TW::Y));
if (cell->type == ID($and) && !is_signed) {
if (a_width > b_width)
@ -68,8 +68,8 @@ void bitwise_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int y_width = GetSize(cell->getPort(TW::Y));
if (is_signed && a_width == 1)
y_width = std::min(y_width, 1);
@ -82,9 +82,9 @@ void arith_neg_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int y_width = GetSize(cell->getPort(TW::Y));
if (!is_signed && cell->type != ID($sub)) {
int ab_width = std::max(a_width, b_width);
@ -106,7 +106,7 @@ void arith_binary_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int a_width = GetSize(cell->getPort(TW::A));
for (int i = 0; i < a_width; i++)
db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
@ -114,8 +114,8 @@ void reduce_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
for (int i = 0; i < a_width; i++)
db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
@ -125,8 +125,8 @@ void logic_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
for (int i = 0; i < a_width; i++)
db->add_edge(cell, ID::A, i, ID::Y, i, -1);
@ -137,8 +137,8 @@ void concat_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int offset = cell->getParam(ID::OFFSET).as_int();
int a_width = GetSize(cell->getPort(ID::A));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int y_width = GetSize(cell->getPort(TW::Y));
for (int i = 0; i < y_width; i++) {
int a_bit = offset + i;
@ -149,8 +149,8 @@ void slice_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
for (int i = 0; i < a_width; i++)
db->add_edge(cell, ID::A, i, ID::Y, 0, -1);
@ -161,9 +161,9 @@ void compare_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int s_width = GetSize(cell->getPort(ID::S));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int s_width = GetSize(cell->getPort(TW::S));
for (int i = 0; i < a_width; i++)
{
@ -179,9 +179,9 @@ void mux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void bmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(ID::A));
int s_width = GetSize(cell->getPort(ID::S));
int width = GetSize(cell->getPort(TW::Y));
int a_width = GetSize(cell->getPort(TW::A));
int s_width = GetSize(cell->getPort(TW::S));
for (int i = 0; i < width; i++)
{
@ -195,9 +195,9 @@ void bmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void demux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(ID::A));
int s_width = GetSize(cell->getPort(ID::S));
int width = GetSize(cell->getPort(TW::Y));
int a_width = GetSize(cell->getPort(TW::A));
int s_width = GetSize(cell->getPort(TW::S));
for (int i = 0; i < width; i++)
{
@ -211,9 +211,9 @@ void shift_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
bool is_signed = cell->getParam(ID::A_SIGNED).as_bool();
bool is_b_signed = cell->getParam(ID::B_SIGNED).as_bool();
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int y_width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int y_width = GetSize(cell->getPort(TW::Y));
// Behavior of the different shift cells:
//
@ -397,7 +397,7 @@ void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = cell->getPort(ID::Q).size();
int width = cell->getPort(TW::Q).size();
if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
for (int k = 0; k < width; k++) {
@ -430,7 +430,7 @@ void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
for (auto &conn : cell->connections())
{
RTLIL::IdString port = conn.first;
TwineRef port = conn.first;
RTLIL::PortDir dir = cell->port_dir(port);
if (cell->input(port) || dir == RTLIL::PortDir::PD_INOUT)
input_ports.push_back(port);
@ -455,9 +455,9 @@ void full_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int width = GetSize(cell->getPort(TW::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int max_width = std::min(width, std::min(a_width, b_width));
for (int i = 0; i < max_width; i++) {
@ -468,10 +468,10 @@ void bweqx_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
void bwmux_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
{
int width = GetSize(cell->getPort(ID::Y));
int a_width = GetSize(cell->getPort(ID::A));
int b_width = GetSize(cell->getPort(ID::B));
int s_width = GetSize(cell->getPort(ID::S));
int width = GetSize(cell->getPort(TW::Y));
int a_width = GetSize(cell->getPort(TW::A));
int b_width = GetSize(cell->getPort(TW::B));
int s_width = GetSize(cell->getPort(TW::S));
int max_width = std::min(width, std::min(a_width, std::min(b_width, s_width)));
for (int i = 0; i < max_width; i++) {

208
kernel/celltypes.h
View file

@ -28,7 +28,7 @@ YOSYS_NAMESPACE_BEGIN
struct CellType
{
RTLIL::IdString type;
pool<RTLIL::IdString> inputs, outputs;
pool<TwineRef> inputs, outputs;
bool is_evaluable;
bool is_combinatorial;
bool is_synthesizable;
@ -59,7 +59,7 @@ struct CellTypes
setup_stdcells_mem();
}
void setup_type(RTLIL::IdString type, const pool<RTLIL::IdString> &inputs, const pool<RTLIL::IdString> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)
void setup_type(RTLIL::IdString type, const pool<TwineRef> &inputs, const pool<TwineRef> &outputs, bool is_evaluable = false, bool is_combinatorial = false, bool is_synthesizable = false)
{
CellType ct = {type, inputs, outputs, is_evaluable, is_combinatorial, is_synthesizable};
cell_types[ct.type] = ct;
@ -67,13 +67,13 @@ struct CellTypes
void setup_module(RTLIL::Module *module)
{
pool<RTLIL::IdString> inputs, outputs;
pool<TwineRef> inputs, outputs;
for (auto wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
inputs.insert(wire->name);
inputs.insert(wire->meta_->name);
if (wire->port_output)
outputs.insert(wire->name);
outputs.insert(wire->meta_->name);
}
setup_type(module->name, inputs, outputs);
}
@ -88,34 +88,34 @@ struct CellTypes
{
setup_internals_eval();
setup_type(ID($tribuf), {ID::A, ID::EN}, {ID::Y});
setup_type(ID($tribuf), {TW::A, TW::EN}, {TW::Y});
setup_type(ID($assert), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($assume), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($live), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($fair), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($cover), {ID::A, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($initstate), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($anyconst), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($anyseq), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($allconst), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($allseq), pool<RTLIL::IdString>(), {ID::Y});
setup_type(ID($equiv), {ID::A, ID::B}, {ID::Y});
setup_type(ID($specify2), {ID::EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
setup_type(ID($specify3), {ID::EN, ID::SRC, ID::DST, ID::DAT}, pool<RTLIL::IdString>());
setup_type(ID($specrule), {ID::SRC_EN, ID::DST_EN, ID::SRC, ID::DST}, pool<RTLIL::IdString>());
setup_type(ID($print), {ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
setup_type(ID($check), {ID::A, ID::EN, ID::ARGS, ID::TRG}, pool<RTLIL::IdString>());
setup_type(ID($set_tag), {ID::A, ID::SET, ID::CLR}, {ID::Y});
setup_type(ID($get_tag), {ID::A}, {ID::Y});
setup_type(ID($overwrite_tag), {ID::A, ID::SET, ID::CLR}, pool<RTLIL::IdString>());
setup_type(ID($original_tag), {ID::A}, {ID::Y});
setup_type(ID($future_ff), {ID::A}, {ID::Y});
setup_type(ID($assert), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($assume), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($live), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($fair), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($cover), {TW::A, TW::EN}, pool<TwineRef>());
setup_type(ID($initstate), pool<TwineRef>(), {TW::Y});
setup_type(ID($anyconst), pool<TwineRef>(), {TW::Y});
setup_type(ID($anyseq), pool<TwineRef>(), {TW::Y});
setup_type(ID($allconst), pool<TwineRef>(), {TW::Y});
setup_type(ID($allseq), pool<TwineRef>(), {TW::Y});
setup_type(ID($equiv), {TW::A, TW::B}, {TW::Y});
setup_type(ID($specify2), {TW::EN, TW::SRC, TW::DST}, pool<TwineRef>());
setup_type(ID($specify3), {TW::EN, TW::SRC, TW::DST, TW::DAT}, pool<TwineRef>());
setup_type(ID($specrule), {TW::SRC_EN, TW::DST_EN, TW::SRC, TW::DST}, pool<TwineRef>());
setup_type(ID($print), {TW::EN, TW::ARGS, TW::TRG}, pool<TwineRef>());
setup_type(ID($check), {TW::A, TW::EN, TW::ARGS, TW::TRG}, pool<TwineRef>());
setup_type(ID($set_tag), {TW::A, TW::SET, TW::CLR}, {TW::Y});
setup_type(ID($get_tag), {TW::A}, {TW::Y});
setup_type(ID($overwrite_tag), {TW::A, TW::SET, TW::CLR}, pool<TwineRef>());
setup_type(ID($original_tag), {TW::A}, {TW::Y});
setup_type(ID($future_ff), {TW::A}, {TW::Y});
setup_type(ID($scopeinfo), {}, {});
setup_type(ID($input_port), {}, {ID::Y});
setup_type(ID($output_port), {ID::A}, {});
setup_type(ID($public), {ID::A}, {});
setup_type(ID($connect), {ID::A, ID::B}, {});
setup_type(ID($input_port), {}, {TW::Y});
setup_type(ID($output_port), {TW::A}, {});
setup_type(ID($public), {TW::A}, {});
setup_type(ID($connect), {TW::A, TW::B}, {});
}
void setup_internals_eval()
@ -136,92 +136,92 @@ struct CellTypes
};
for (auto type : unary_ops)
setup_type(type, {ID::A}, {ID::Y}, true);
setup_type(type, {TW::A}, {TW::Y}, true);
for (auto type : binary_ops)
setup_type(type, {ID::A, ID::B}, {ID::Y}, true);
setup_type(type, {TW::A, TW::B}, {TW::Y}, true);
for (auto type : std::vector<RTLIL::IdString>({ID($mux), ID($pmux), ID($bwmux)}))
setup_type(type, {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(type, {TW::A, TW::B, TW::S}, {TW::Y}, true);
for (auto type : std::vector<RTLIL::IdString>({ID($bmux), ID($demux)}))
setup_type(type, {ID::A, ID::S}, {ID::Y}, true);
setup_type(type, {TW::A, TW::S}, {TW::Y}, true);
setup_type(ID($lcu), {ID::P, ID::G, ID::CI}, {ID::CO}, true);
setup_type(ID($alu), {ID::A, ID::B, ID::CI, ID::BI}, {ID::X, ID::Y, ID::CO}, true);
setup_type(ID($macc_v2), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($fa), {ID::A, ID::B, ID::C}, {ID::X, ID::Y}, true);
setup_type(ID($lcu), {TW::P, TW::G, TW::CI}, {TW::CO}, true);
setup_type(ID($alu), {TW::A, TW::B, TW::CI, TW::BI}, {TW::X, TW::Y, TW::CO}, true);
setup_type(ID($macc_v2), {TW::A, TW::B, TW::C}, {TW::Y}, true);
setup_type(ID($fa), {TW::A, TW::B, TW::C}, {TW::X, TW::Y}, true);
}
void setup_internals_ff()
{
setup_type(ID($sr), {ID::SET, ID::CLR}, {ID::Q});
setup_type(ID($ff), {ID::D}, {ID::Q});
setup_type(ID($dff), {ID::CLK, ID::D}, {ID::Q});
setup_type(ID($dffe), {ID::CLK, ID::EN, ID::D}, {ID::Q});
setup_type(ID($dffsr), {ID::CLK, ID::SET, ID::CLR, ID::D}, {ID::Q});
setup_type(ID($dffsre), {ID::CLK, ID::SET, ID::CLR, ID::D, ID::EN}, {ID::Q});
setup_type(ID($adff), {ID::CLK, ID::ARST, ID::D}, {ID::Q});
setup_type(ID($adffe), {ID::CLK, ID::ARST, ID::D, ID::EN}, {ID::Q});
setup_type(ID($aldff), {ID::CLK, ID::ALOAD, ID::AD, ID::D}, {ID::Q});
setup_type(ID($aldffe), {ID::CLK, ID::ALOAD, ID::AD, ID::D, ID::EN}, {ID::Q});
setup_type(ID($sdff), {ID::CLK, ID::SRST, ID::D}, {ID::Q});
setup_type(ID($sdffe), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});
setup_type(ID($sdffce), {ID::CLK, ID::SRST, ID::D, ID::EN}, {ID::Q});
setup_type(ID($dlatch), {ID::EN, ID::D}, {ID::Q});
setup_type(ID($adlatch), {ID::EN, ID::D, ID::ARST}, {ID::Q});
setup_type(ID($dlatchsr), {ID::EN, ID::SET, ID::CLR, ID::D}, {ID::Q});
setup_type(ID($sr), {TW::SET, TW::CLR}, {TW::Q});
setup_type(ID($ff), {TW::D}, {TW::Q});
setup_type(ID($dff), {TW::CLK, TW::D}, {TW::Q});
setup_type(ID($dffe), {TW::CLK, TW::EN, TW::D}, {TW::Q});
setup_type(ID($dffsr), {TW::CLK, TW::SET, TW::CLR, TW::D}, {TW::Q});
setup_type(ID($dffsre), {TW::CLK, TW::SET, TW::CLR, TW::D, TW::EN}, {TW::Q});
setup_type(ID($adff), {TW::CLK, TW::ARST, TW::D}, {TW::Q});
setup_type(ID($adffe), {TW::CLK, TW::ARST, TW::D, TW::EN}, {TW::Q});
setup_type(ID($aldff), {TW::CLK, TW::ALOAD, TW::AD, TW::D}, {TW::Q});
setup_type(ID($aldffe), {TW::CLK, TW::ALOAD, TW::AD, TW::D, TW::EN}, {TW::Q});
setup_type(ID($sdff), {TW::CLK, TW::SRST, TW::D}, {TW::Q});
setup_type(ID($sdffe), {TW::CLK, TW::SRST, TW::D, TW::EN}, {TW::Q});
setup_type(ID($sdffce), {TW::CLK, TW::SRST, TW::D, TW::EN}, {TW::Q});
setup_type(ID($dlatch), {TW::EN, TW::D}, {TW::Q});
setup_type(ID($adlatch), {TW::EN, TW::D, TW::ARST}, {TW::Q});
setup_type(ID($dlatchsr), {TW::EN, TW::SET, TW::CLR, TW::D}, {TW::Q});
}
void setup_internals_anyinit()
{
setup_type(ID($anyinit), {ID::D}, {ID::Q});
setup_type(ID($anyinit), {TW::D}, {TW::Q});
}
void setup_internals_mem()
{
setup_internals_ff();
setup_type(ID($memrd), {ID::CLK, ID::EN, ID::ADDR}, {ID::DATA});
setup_type(ID($memrd_v2), {ID::CLK, ID::EN, ID::ARST, ID::SRST, ID::ADDR}, {ID::DATA});
setup_type(ID($memwr), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
setup_type(ID($memwr_v2), {ID::CLK, ID::EN, ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
setup_type(ID($meminit), {ID::ADDR, ID::DATA}, pool<RTLIL::IdString>());
setup_type(ID($meminit_v2), {ID::ADDR, ID::DATA, ID::EN}, pool<RTLIL::IdString>());
setup_type(ID($mem), {ID::RD_CLK, ID::RD_EN, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
setup_type(ID($mem_v2), {ID::RD_CLK, ID::RD_EN, ID::RD_ARST, ID::RD_SRST, ID::RD_ADDR, ID::WR_CLK, ID::WR_EN, ID::WR_ADDR, ID::WR_DATA}, {ID::RD_DATA});
setup_type(ID($memrd), {TW::CLK, TW::EN, TW::ADDR}, {TW::DATA});
setup_type(ID($memrd_v2), {TW::CLK, TW::EN, TW::ARST, TW::SRST, TW::ADDR}, {TW::DATA});
setup_type(ID($memwr), {TW::CLK, TW::EN, TW::ADDR, TW::DATA}, pool<TwineRef>());
setup_type(ID($memwr_v2), {TW::CLK, TW::EN, TW::ADDR, TW::DATA}, pool<TwineRef>());
setup_type(ID($meminit), {TW::ADDR, TW::DATA}, pool<TwineRef>());
setup_type(ID($meminit_v2), {TW::ADDR, TW::DATA, TW::EN}, pool<TwineRef>());
setup_type(ID($mem), {TW::RD_CLK, TW::RD_EN, TW::RD_ADDR, TW::WR_CLK, TW::WR_EN, TW::WR_ADDR, TW::WR_DATA}, {TW::RD_DATA});
setup_type(ID($mem_v2), {TW::RD_CLK, TW::RD_EN, TW::RD_ARST, TW::RD_SRST, TW::RD_ADDR, TW::WR_CLK, TW::WR_EN, TW::WR_ADDR, TW::WR_DATA}, {TW::RD_DATA});
setup_type(ID($fsm), {ID::CLK, ID::ARST, ID::CTRL_IN}, {ID::CTRL_OUT});
setup_type(ID($fsm), {TW::CLK, TW::ARST, TW::CTRL_IN}, {TW::CTRL_OUT});
}
void setup_stdcells()
{
setup_stdcells_eval();
setup_type(ID($_TBUF_), {ID::A, ID::E}, {ID::Y});
setup_type(ID($_TBUF_), {TW::A, TW::E}, {TW::Y});
}
void setup_stdcells_eval()
{
setup_type(ID($_BUF_), {ID::A}, {ID::Y}, true);
setup_type(ID($_NOT_), {ID::A}, {ID::Y}, true);
setup_type(ID($_AND_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_NAND_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_OR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_NOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_XOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_XNOR_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_ANDNOT_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_ORNOT_), {ID::A, ID::B}, {ID::Y}, true);
setup_type(ID($_MUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(ID($_NMUX_), {ID::A, ID::B, ID::S}, {ID::Y}, true);
setup_type(ID($_MUX4_), {ID::A, ID::B, ID::C, ID::D, ID::S, ID::T}, {ID::Y}, true);
setup_type(ID($_MUX8_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::S, ID::T, ID::U}, {ID::Y}, true);
setup_type(ID($_MUX16_), {ID::A, ID::B, ID::C, ID::D, ID::E, ID::F, ID::G, ID::H, ID::I, ID::J, ID::K, ID::L, ID::M, ID::N, ID::O, ID::P, ID::S, ID::T, ID::U, ID::V}, {ID::Y}, true);
setup_type(ID($_AOI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($_OAI3_), {ID::A, ID::B, ID::C}, {ID::Y}, true);
setup_type(ID($_AOI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
setup_type(ID($_OAI4_), {ID::A, ID::B, ID::C, ID::D}, {ID::Y}, true);
setup_type(ID($_BUF_), {TW::A}, {TW::Y}, true);
setup_type(ID($_NOT_), {TW::A}, {TW::Y}, true);
setup_type(ID($_AND_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_NAND_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_OR_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_NOR_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_XOR_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_XNOR_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_ANDNOT_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_ORNOT_), {TW::A, TW::B}, {TW::Y}, true);
setup_type(ID($_MUX_), {TW::A, TW::B, TW::S}, {TW::Y}, true);
setup_type(ID($_NMUX_), {TW::A, TW::B, TW::S}, {TW::Y}, true);
setup_type(ID($_MUX4_), {TW::A, TW::B, TW::C, TW::D, TW::S, TW::T}, {TW::Y}, true);
setup_type(ID($_MUX8_), {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::S, TW::T, TW::U}, {TW::Y}, true);
setup_type(ID($_MUX16_), {TW::A, TW::B, TW::C, TW::D, TW::E, TW::F, TW::G, TW::H, TW::I, TW::J, TW::K, TW::L, TW::M, TW::N, TW::O, TW::P, TW::S, TW::T, TW::U, TW::V}, {TW::Y}, true);
setup_type(ID($_AOI3_), {TW::A, TW::B, TW::C}, {TW::Y}, true);
setup_type(ID($_OAI3_), {TW::A, TW::B, TW::C}, {TW::Y}, true);
setup_type(ID($_AOI4_), {TW::A, TW::B, TW::C, TW::D}, {TW::Y}, true);
setup_type(ID($_OAI4_), {TW::A, TW::B, TW::C, TW::D}, {TW::Y}, true);
}
void setup_stdcells_mem()
@ -230,77 +230,77 @@ struct CellTypes
for (auto c1 : list_np)
for (auto c2 : list_np)
setup_type(stringf("$_SR_%c%c_", c1, c2), {ID::S, ID::R}, {ID::Q});
setup_type(stringf("$_SR_%c%c_", c1, c2), {TW::S, TW::R}, {TW::Q});
setup_type(ID($_FF_), {ID::D}, {ID::Q});
setup_type(ID($_FF_), {TW::D}, {TW::Q});
for (auto c1 : list_np)
setup_type(stringf("$_DFF_%c_", c1), {ID::C, ID::D}, {ID::Q});
setup_type(stringf("$_DFF_%c_", c1), {TW::C, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
setup_type(stringf("$_DFFE_%c%c_", c1, c2), {ID::C, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_DFFE_%c%c_", c1, c2), {TW::C, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {TW::C, TW::R, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
for (auto c4 : list_np)
setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_DFFE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
setup_type(stringf("$_ALDFF_%c%c_", c1, c2), {ID::C, ID::L, ID::AD, ID::D}, {ID::Q});
setup_type(stringf("$_ALDFF_%c%c_", c1, c2), {TW::C, TW::L, TW::AD, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
setup_type(stringf("$_ALDFFE_%c%c%c_", c1, c2, c3), {ID::C, ID::L, ID::AD, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_ALDFFE_%c%c%c_", c1, c2, c3), {TW::C, TW::L, TW::AD, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {ID::C, ID::S, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_DFFSR_%c%c%c_", c1, c2, c3), {TW::C, TW::S, TW::R, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
for (auto c4 : list_np)
setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::S, ID::R, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_DFFSRE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::S, TW::R, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {ID::C, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_SDFF_%c%c%c_", c1, c2, c3), {TW::C, TW::R, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
for (auto c4 : list_np)
setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_SDFFE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
for (auto c4 : list_np)
setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {ID::C, ID::R, ID::D, ID::E}, {ID::Q});
setup_type(stringf("$_SDFFCE_%c%c%c%c_", c1, c2, c3, c4), {TW::C, TW::R, TW::D, TW::E}, {TW::Q});
for (auto c1 : list_np)
setup_type(stringf("$_DLATCH_%c_", c1), {ID::E, ID::D}, {ID::Q});
setup_type(stringf("$_DLATCH_%c_", c1), {TW::E, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_01)
setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {ID::E, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_DLATCH_%c%c%c_", c1, c2, c3), {TW::E, TW::R, TW::D}, {TW::Q});
for (auto c1 : list_np)
for (auto c2 : list_np)
for (auto c3 : list_np)
setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {ID::E, ID::S, ID::R, ID::D}, {ID::Q});
setup_type(stringf("$_DLATCHSR_%c%c%c_", c1, c2, c3), {TW::E, TW::S, TW::R, TW::D}, {TW::Q});
}
void clear()
@ -313,19 +313,19 @@ struct CellTypes
return cell_types.count(type) != 0;
}
bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
bool cell_output(RTLIL::IdString type, TwineRef port) const
{
auto it = cell_types.find(type);
return it != cell_types.end() && it->second.outputs.count(port) != 0;
}
bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
bool cell_input(RTLIL::IdString type, TwineRef port) const
{
auto it = cell_types.find(type);
return it != cell_types.end() && it->second.inputs.count(port) != 0;
}
RTLIL::PortDir cell_port_dir(RTLIL::IdString type, RTLIL::IdString port) const
RTLIL::PortDir cell_port_dir(RTLIL::IdString type, TwineRef port) const
{
auto it = cell_types.find(type);
if (it == cell_types.end())

36
kernel/consteval.h
View file

@ -95,10 +95,10 @@ struct ConstEval
{
if (cell->type == ID($lcu))
{
RTLIL::SigSpec sig_p = cell->getPort(ID::P);
RTLIL::SigSpec sig_g = cell->getPort(ID::G);
RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(ID::CO)));
RTLIL::SigSpec sig_p = cell->getPort(TW::P);
RTLIL::SigSpec sig_g = cell->getPort(TW::G);
RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
RTLIL::SigSpec sig_co = values_map(assign_map(cell->getPort(TW::CO)));
if (sig_co.is_fully_const())
return true;
@ -133,19 +133,19 @@ struct ConstEval
RTLIL::SigSpec sig_a, sig_b, sig_s, sig_y;
log_assert(cell->hasPort(ID::Y));
sig_y = values_map(assign_map(cell->getPort(ID::Y)));
sig_y = values_map(assign_map(cell->getPort(TW::Y)));
if (sig_y.is_fully_const())
return true;
if (cell->hasPort(ID::S)) {
sig_s = cell->getPort(ID::S);
sig_s = cell->getPort(TW::S);
}
if (cell->hasPort(ID::A))
sig_a = cell->getPort(ID::A);
sig_a = cell->getPort(TW::A);
if (cell->hasPort(ID::B))
sig_b = cell->getPort(ID::B);
sig_b = cell->getPort(TW::B);
if (cell->type.in(ID($mux), ID($pmux), ID($_MUX_), ID($_NMUX_)))
{
@ -231,8 +231,8 @@ struct ConstEval
}
else if (cell->type == ID($fa))
{
RTLIL::SigSpec sig_c = cell->getPort(ID::C);
RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_c = cell->getPort(TW::C);
RTLIL::SigSpec sig_x = cell->getPort(TW::X);
int width = GetSize(sig_c);
if (!eval(sig_a, undef, cell))
@ -263,8 +263,8 @@ struct ConstEval
bool signed_a = cell->parameters.count(ID::A_SIGNED) > 0 && cell->parameters[ID::A_SIGNED].as_bool();
bool signed_b = cell->parameters.count(ID::B_SIGNED) > 0 && cell->parameters[ID::B_SIGNED].as_bool();
RTLIL::SigSpec sig_ci = cell->getPort(ID::CI);
RTLIL::SigSpec sig_bi = cell->getPort(ID::BI);
RTLIL::SigSpec sig_ci = cell->getPort(TW::CI);
RTLIL::SigSpec sig_bi = cell->getPort(TW::BI);
if (!eval(sig_a, undef, cell))
return false;
@ -278,8 +278,8 @@ struct ConstEval
if (!eval(sig_bi, undef, cell))
return false;
RTLIL::SigSpec sig_x = cell->getPort(ID::X);
RTLIL::SigSpec sig_co = cell->getPort(ID::CO);
RTLIL::SigSpec sig_x = cell->getPort(TW::X);
RTLIL::SigSpec sig_co = cell->getPort(TW::CO);
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
sig_a.extend_u0(GetSize(sig_y), signed_a);
@ -326,11 +326,11 @@ struct ConstEval
return false;
}
RTLIL::Const result(0, GetSize(cell->getPort(ID::Y)));
RTLIL::Const result(0, GetSize(cell->getPort(TW::Y)));
if (!macc.eval(result))
log_abort();
set(cell->getPort(ID::Y), result);
set(cell->getPort(TW::Y), result);
}
else
{
@ -338,9 +338,9 @@ struct ConstEval
if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
if (cell->hasPort(ID::C))
sig_c = cell->getPort(ID::C);
sig_c = cell->getPort(TW::C);
if (cell->hasPort(ID::D))
sig_d = cell->getPort(ID::D);
sig_d = cell->getPort(TW::D);
}
if (sig_a.size() > 0 && !eval(sig_a, undef, cell))

2
kernel/cost.cc
View file

@ -124,7 +124,7 @@ unsigned int max_inp_width(RTLIL::Cell *cell)
unsigned int port_width_sum(RTLIL::Cell *cell)
{
unsigned int sum = 0;
RTLIL::IdString port_width_params[] = {
TwineRef port_width_params[] = {
ID::WIDTH, ID::A_WIDTH, ID::B_WIDTH, ID::S_WIDTH, ID::Y_WIDTH,
};

136
kernel/ff.cc
View file

@ -36,7 +36,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
type = flop->type;
}
if constexpr (have_cell) {
info.sig_q = cell->getPort(ID::Q);
info.sig_q = cell->getPort(TW::Q);
info.width = GetSize(info.sig_q);
info.attributes = cell->attributes;
// Carry src across construction → emit() as an owning Twine
@ -58,7 +58,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
if (type.in(ID($anyinit), ID($ff))) {
info.has_gclk = true;
if constexpr (have_cell)
info.sig_d = cell->getPort(ID::D);
info.sig_d = cell->getPort(TW::D);
if (type == ID($anyinit)) {
info.is_anyinit = true;
if constexpr (have_cell)
@ -69,30 +69,30 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
} else if (type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
info.has_aload = true;
if constexpr (have_cell) {
info.sig_aload = cell->getPort(ID::EN);
info.sig_aload = cell->getPort(TW::EN);
info.pol_aload = cell->getParam(ID::EN_POLARITY).as_bool();
info.sig_ad = cell->getPort(ID::D);
info.sig_ad = cell->getPort(TW::D);
}
} else {
info.has_clk = true;
if constexpr (have_cell) {
info.sig_clk = cell->getPort(ID::CLK);
info.sig_clk = cell->getPort(TW::CLK);
info.pol_clk = cell->getParam(ID::CLK_POLARITY).as_bool();
info.sig_d = cell->getPort(ID::D);
info.sig_d = cell->getPort(TW::D);
}
}
if (type.in(ID($dffe), ID($dffsre), ID($adffe), ID($aldffe), ID($sdffe), ID($sdffce))) {
info.has_ce = true;
if constexpr (have_cell) {
info.sig_ce = cell->getPort(ID::EN);
info.sig_ce = cell->getPort(TW::EN);
info.pol_ce = cell->getParam(ID::EN_POLARITY).as_bool();
}
}
if (type.in(ID($dffsr), ID($dffsre), ID($dlatchsr), ID($sr))) {
info.has_sr = true;
if constexpr (have_cell) {
info.sig_clr = cell->getPort(ID::CLR);
info.sig_set = cell->getPort(ID::SET);
info.sig_clr = cell->getPort(TW::CLR);
info.sig_set = cell->getPort(TW::SET);
info.pol_clr = cell->getParam(ID::CLR_POLARITY).as_bool();
info.pol_set = cell->getParam(ID::SET_POLARITY).as_bool();
}
@ -100,15 +100,15 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
if (type.in(ID($aldff), ID($aldffe))) {
info.has_aload = true;
if constexpr (have_cell) {
info.sig_aload = cell->getPort(ID::ALOAD);
info.sig_aload = cell->getPort(TW::ALOAD);
info.pol_aload = cell->getParam(ID::ALOAD_POLARITY).as_bool();
info.sig_ad = cell->getPort(ID::AD);
info.sig_ad = cell->getPort(TW::AD);
}
}
if (type.in(ID($adff), ID($adffe), ID($adlatch))) {
info.has_arst = true;
if constexpr (have_cell) {
info.sig_arst = cell->getPort(ID::ARST);
info.sig_arst = cell->getPort(TW::ARST);
info.pol_arst = cell->getParam(ID::ARST_POLARITY).as_bool();
info.val_arst = cell->getParam(ID::ARST_VALUE);
}
@ -116,7 +116,7 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
if (type.in(ID($sdff), ID($sdffe), ID($sdffce))) {
info.has_srst = true;
if constexpr (have_cell) {
info.sig_srst = cell->getPort(ID::SRST);
info.sig_srst = cell->getPort(TW::SRST);
info.pol_srst = cell->getParam(ID::SRST_POLARITY).as_bool();
info.val_srst = cell->getParam(ID::SRST_VALUE);
}
@ -126,23 +126,23 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.is_fine = true;
info.has_gclk = true;
if constexpr (have_cell)
info.sig_d = cell->getPort(ID::D);
info.sig_d = cell->getPort(TW::D);
} else if (type_str.substr(0, 5) == "$_SR_") {
info.is_fine = true;
info.has_sr = true;
info.pol_set = type_str[5] == 'P';
info.pol_clr = type_str[6] == 'P';
if constexpr (have_cell) {
info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
info.sig_set = cell->getPort(TW::S);
info.sig_clr = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 8) {
info.is_fine = true;
info.has_clk = true;
info.pol_clk = type_str[6] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
}
} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 10) {
info.is_fine = true;
@ -151,9 +151,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[8] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 6) == "$_DFF_" && type_str.size() == 10) {
info.is_fine = true;
@ -163,9 +163,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_arst = type_str[7] == 'P';
info.val_arst = type_str[8] == '1' ? State::S1 : State::S0;
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_arst = cell->getPort(ID::R);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_arst = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 7) == "$_DFFE_" && type_str.size() == 12) {
info.is_fine = true;
@ -177,10 +177,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[10] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_arst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_arst = cell->getPort(TW::R);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 8) == "$_ALDFF_" && type_str.size() == 11) {
info.is_fine = true;
@ -189,10 +189,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_aload = true;
info.pol_aload = type_str[9] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_aload = cell->getPort(ID::L);
info.sig_ad = cell->getPort(ID::AD);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_aload = cell->getPort(TW::L);
info.sig_ad = cell->getPort(TW::AD);
}
} else if (type_str.substr(0, 9) == "$_ALDFFE_" && type_str.size() == 13) {
info.is_fine = true;
@ -203,11 +203,11 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[11] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_aload = cell->getPort(ID::L);
info.sig_ad = cell->getPort(ID::AD);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_aload = cell->getPort(TW::L);
info.sig_ad = cell->getPort(TW::AD);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 8) == "$_DFFSR_" && type_str.size() == 12) {
info.is_fine = true;
@ -217,10 +217,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_set = type_str[9] == 'P';
info.pol_clr = type_str[10] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_set = cell->getPort(TW::S);
info.sig_clr = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 9) == "$_DFFSRE_" && type_str.size() == 14) {
info.is_fine = true;
@ -232,11 +232,11 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[12] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_set = cell->getPort(TW::S);
info.sig_clr = cell->getPort(TW::R);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 7) == "$_SDFF_" && type_str.size() == 11) {
info.is_fine = true;
@ -246,9 +246,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_srst = type_str[8] == 'P';
info.val_srst = type_str[9] == '1' ? State::S1 : State::S0;
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_srst = cell->getPort(ID::R);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_srst = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 8) == "$_SDFFE_" && type_str.size() == 13) {
info.is_fine = true;
@ -260,10 +260,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_ce = true;
info.pol_ce = type_str[11] == 'P';
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_srst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_srst = cell->getPort(TW::R);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 9) == "$_SDFFCE_" && type_str.size() == 14) {
info.is_fine = true;
@ -276,10 +276,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_ce = type_str[12] == 'P';
info.ce_over_srst = true;
if constexpr (have_cell) {
info.sig_d = cell->getPort(ID::D);
info.sig_clk = cell->getPort(ID::C);
info.sig_srst = cell->getPort(ID::R);
info.sig_ce = cell->getPort(ID::E);
info.sig_d = cell->getPort(TW::D);
info.sig_clk = cell->getPort(TW::C);
info.sig_srst = cell->getPort(TW::R);
info.sig_ce = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 11) {
info.is_fine = true;
@ -287,8 +287,8 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.has_aload = true;
info.pol_aload = type_str[9] == 'P';
if constexpr (have_cell) {
info.sig_ad = cell->getPort(ID::D);
info.sig_aload = cell->getPort(ID::E);
info.sig_ad = cell->getPort(TW::D);
info.sig_aload = cell->getPort(TW::E);
}
} else if (type_str.substr(0, 9) == "$_DLATCH_" && type_str.size() == 13) {
info.is_fine = true;
@ -299,9 +299,9 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_arst = type_str[10] == 'P';
info.val_arst = type_str[11] == '1' ? State::S1 : State::S0;
if constexpr (have_cell) {
info.sig_ad = cell->getPort(ID::D);
info.sig_aload = cell->getPort(ID::E);
info.sig_arst = cell->getPort(ID::R);
info.sig_ad = cell->getPort(TW::D);
info.sig_aload = cell->getPort(TW::E);
info.sig_arst = cell->getPort(TW::R);
}
} else if (type_str.substr(0, 11) == "$_DLATCHSR_" && type_str.size() == 15) {
info.is_fine = true;
@ -312,10 +312,10 @@ void manufacture_info(InputType flop, OutputType& info, FfInitVals *initvals) {
info.pol_set = type_str[12] == 'P';
info.pol_clr = type_str[13] == 'P';
if constexpr (have_cell) {
info.sig_ad = cell->getPort(ID::D);
info.sig_aload = cell->getPort(ID::E);
info.sig_set = cell->getPort(ID::S);
info.sig_clr = cell->getPort(ID::R);
info.sig_ad = cell->getPort(TW::D);
info.sig_aload = cell->getPort(TW::E);
info.sig_set = cell->getPort(TW::S);
info.sig_clr = cell->getPort(TW::R);
}
} else {
log_assert(0);
@ -780,7 +780,7 @@ Cell *FfData::emit() {
}
}
if (initvals && !is_anyinit)
initvals->set_init(cell->getPort(ID::Q), val_init);
initvals->set_init(cell->getPort(TW::Q), val_init);
return cell;
}
@ -823,7 +823,7 @@ void FfData::flip_bits(const pool<int> &bits) {
flip_rst_bits(bits);
Wire *new_q = module->addWire(NEW_ID, width);
Wire *new_q = module->addWire(NEW_TWINE, width);
if (has_sr && cell) {
log_warning("Flipping D/Q/init and inserting priority fixup to legalize %s.%s [%s].\n", module->name.unescape(), cell->name.unescape(), cell->type.unescape());

12
kernel/ffmerge.cc
View file

@ -298,12 +298,12 @@ void FfMergeHelper::remove_output_ff(const pool<std::pair<Cell *, int>> &bits) {
for (auto &it : bits) {
Cell *cell = it.first;
int idx = it.second;
SigSpec q = cell->getPort(ID::Q);
SigSpec q = cell->getPort(TW::Q);
initvals->remove_init(q[idx]);
dff_driver.erase((*sigmap)(q[idx]));
q[idx] = module->addWire(stringf("$ffmerge_disconnected$%d", autoidx++));
cell->setPort(ID::Q, q);
initvals->set_init(cell->getPort(ID::Q), (*initvals)(q));
cell->setPort(TW::Q, q);
initvals->set_init(cell->getPort(TW::Q), (*initvals)(q));
}
}
@ -312,7 +312,7 @@ void FfMergeHelper::mark_input_ff(const pool<std::pair<Cell *, int>> &bits) {
Cell *cell = it.first;
int idx = it.second;
if (cell->hasPort(ID::D)) {
SigSpec d = cell->getPort(ID::D);
SigSpec d = cell->getPort(TW::D);
// The user count was already at least 1
// (for the D port). Bump it as it is now connected
// to the merged-to cell as well. This suffices for
@ -338,11 +338,11 @@ void FfMergeHelper::set(FfInitVals *initvals_, RTLIL::Module *module_)
for (auto cell : module->cells()) {
if (cell->is_builtin_ff()) {
if (cell->hasPort(ID::D)) {
SigSpec d = (*sigmap)(cell->getPort(ID::D));
SigSpec d = (*sigmap)(cell->getPort(TW::D));
for (int i = 0; i < GetSize(d); i++)
dff_sink[d[i]].insert(std::make_pair(cell, i));
}
SigSpec q = (*sigmap)(cell->getPort(ID::Q));
SigSpec q = (*sigmap)(cell->getPort(TW::Q));
for (int i = 0; i < GetSize(q); i++)
dff_driver[q[i]] = std::make_pair(cell, i);
}

16
kernel/macc.h
View file

@ -84,7 +84,7 @@ struct Macc
void from_cell_v1(RTLIL::Cell *cell)
{
RTLIL::SigSpec port_a = cell->getPort(ID::A);
RTLIL::SigSpec port_a = cell->getPort(TW::A);
terms.clear();
@ -129,7 +129,7 @@ struct Macc
terms.push_back(this_port);
}
for (auto bit : cell->getPort(ID::B))
for (auto bit : cell->getPort(TW::B))
terms.push_back(term_t{{bit}, {}, false, false});
log_assert(config_cursor == config_width);
@ -144,9 +144,9 @@ struct Macc
}
log_assert(cell->type == ID($macc_v2));
RTLIL::SigSpec port_a = cell->getPort(ID::A);
RTLIL::SigSpec port_b = cell->getPort(ID::B);
RTLIL::SigSpec port_c = cell->getPort(ID::C);
RTLIL::SigSpec port_a = cell->getPort(TW::A);
RTLIL::SigSpec port_b = cell->getPort(TW::B);
RTLIL::SigSpec port_c = cell->getPort(TW::C);
terms.clear();
@ -255,9 +255,9 @@ struct Macc
cell->setParam(ID::A_WIDTHS, a_widths);
cell->setParam(ID::B_WIDTHS, b_widths);
cell->setParam(ID::C_WIDTHS, c_widths);
cell->setPort(ID::A, a);
cell->setPort(ID::B, b);
cell->setPort(ID::C, c);
cell->setPort(TW::A, a);
cell->setPort(TW::B, b);
cell->setPort(TW::C, c);
}
bool eval(RTLIL::Const &result) const

130
kernel/mem.cc
View file

@ -221,12 +221,12 @@ void Mem::emit() {
cell->parameters[ID::RD_SRST_VALUE] = rd_srst_value;
cell->parameters[ID::RD_INIT_VALUE] = rd_init_value;
cell->parameters.erase(ID::RD_TRANSPARENT);
cell->setPort(ID::RD_CLK, rd_clk);
cell->setPort(ID::RD_EN, rd_en);
cell->setPort(ID::RD_ARST, rd_arst);
cell->setPort(ID::RD_SRST, rd_srst);
cell->setPort(ID::RD_ADDR, rd_addr);
cell->setPort(ID::RD_DATA, rd_data);
cell->setPort(TW::RD_CLK, rd_clk);
cell->setPort(TW::RD_EN, rd_en);
cell->setPort(TW::RD_ARST, rd_arst);
cell->setPort(TW::RD_SRST, rd_srst);
cell->setPort(TW::RD_ADDR, rd_addr);
cell->setPort(TW::RD_DATA, rd_data);
Const::Builder wr_wide_continuation_builder;
Const::Builder wr_clk_enable_builder;
Const::Builder wr_clk_polarity_builder;
@ -270,10 +270,10 @@ void Mem::emit() {
cell->parameters[ID::WR_CLK_POLARITY] = wr_clk_polarity;
cell->parameters[ID::WR_PRIORITY_MASK] = wr_priority_mask;
cell->parameters[ID::WR_WIDE_CONTINUATION] = wr_wide_continuation;
cell->setPort(ID::WR_CLK, wr_clk);
cell->setPort(ID::WR_EN, wr_en);
cell->setPort(ID::WR_ADDR, wr_addr);
cell->setPort(ID::WR_DATA, wr_data);
cell->setPort(TW::WR_CLK, wr_clk);
cell->setPort(TW::WR_EN, wr_en);
cell->setPort(TW::WR_ADDR, wr_addr);
cell->setPort(TW::WR_DATA, wr_data);
for (auto &init : inits) {
for (auto attr: init.attributes)
if (!cell->has_attribute(attr.first))
@ -303,7 +303,7 @@ void Mem::emit() {
mem->attributes = attributes;
for (auto &port : rd_ports) {
if (!port.cell)
port.cell = module->addCell(NEW_ID, ID($memrd_v2));
port.cell = module->addCell(NEW_TWINE, ID($memrd_v2));
port.cell->type = ID($memrd_v2);
port.cell->attributes = port.attributes;
port.cell->parameters[ID::MEMID] = memid.str();
@ -318,17 +318,17 @@ void Mem::emit() {
port.cell->parameters[ID::TRANSPARENCY_MASK] = port.transparency_mask;
port.cell->parameters[ID::COLLISION_X_MASK] = port.collision_x_mask;
port.cell->parameters.erase(ID::TRANSPARENT);
port.cell->setPort(ID::CLK, port.clk);
port.cell->setPort(ID::EN, port.en);
port.cell->setPort(ID::ARST, port.arst);
port.cell->setPort(ID::SRST, port.srst);
port.cell->setPort(ID::ADDR, port.addr);
port.cell->setPort(ID::DATA, port.data);
port.cell->setPort(TW::CLK, port.clk);
port.cell->setPort(TW::EN, port.en);
port.cell->setPort(TW::ARST, port.arst);
port.cell->setPort(TW::SRST, port.srst);
port.cell->setPort(TW::ADDR, port.addr);
port.cell->setPort(TW::DATA, port.data);
}
int idx = 0;
for (auto &port : wr_ports) {
if (!port.cell)
port.cell = module->addCell(NEW_ID, ID($memwr_v2));
port.cell = module->addCell(NEW_TWINE, ID($memwr_v2));
port.cell->type = ID($memwr_v2);
port.cell->attributes = port.attributes;
if (port.cell->parameters.count(ID::PRIORITY))
@ -340,19 +340,19 @@ void Mem::emit() {
port.cell->parameters[ID::CLK_POLARITY] = port.clk_polarity;
port.cell->parameters[ID::PORTID] = idx++;
port.cell->parameters[ID::PRIORITY_MASK] = port.priority_mask;
port.cell->setPort(ID::CLK, port.clk);
port.cell->setPort(ID::EN, port.en);
port.cell->setPort(ID::ADDR, port.addr);
port.cell->setPort(ID::DATA, port.data);
port.cell->setPort(TW::CLK, port.clk);
port.cell->setPort(TW::EN, port.en);
port.cell->setPort(TW::ADDR, port.addr);
port.cell->setPort(TW::DATA, port.data);
}
idx = 0;
for (auto &init : inits) {
bool v2 = !init.en.is_fully_ones();
if (!init.cell)
init.cell = module->addCell(NEW_ID, v2 ? ID($meminit_v2) : ID($meminit));
init.cell = module->addCell(NEW_TWINE, v2 ? ID($meminit_v2) : ID($meminit));
else {
if (!v2)
init.cell->unsetPort(ID::EN);
init.cell->unsetPort(TW::EN);
init.cell->type = v2 ? ID($meminit_v2) : ID($meminit);
}
init.cell->attributes = init.attributes;
@ -361,10 +361,10 @@ void Mem::emit() {
init.cell->parameters[ID::WIDTH] = width;
init.cell->parameters[ID::WORDS] = GetSize(init.data) / width;
init.cell->parameters[ID::PRIORITY] = idx++;
init.cell->setPort(ID::ADDR, init.addr);
init.cell->setPort(ID::DATA, init.data);
init.cell->setPort(TW::ADDR, init.addr);
init.cell->setPort(TW::DATA, init.data);
if (v2)
init.cell->setPort(ID::EN, init.en);
init.cell->setPort(TW::EN, init.en);
}
}
}
@ -576,10 +576,10 @@ namespace {
mrd.attributes = cell->attributes;
mrd.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
mrd.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
mrd.clk = cell->getPort(ID::CLK);
mrd.en = cell->getPort(ID::EN);
mrd.addr = cell->getPort(ID::ADDR);
mrd.data = cell->getPort(ID::DATA);
mrd.clk = cell->getPort(TW::CLK);
mrd.en = cell->getPort(TW::EN);
mrd.addr = cell->getPort(TW::ADDR);
mrd.data = cell->getPort(TW::DATA);
mrd.wide_log2 = ceil_log2(GetSize(mrd.data) / mem->width);
bool transparent = false;
if (is_compat) {
@ -604,8 +604,8 @@ namespace {
mrd.arst_value = cell->parameters.at(ID::ARST_VALUE);
mrd.srst_value = cell->parameters.at(ID::SRST_VALUE);
mrd.init_value = cell->parameters.at(ID::INIT_VALUE);
mrd.arst = cell->getPort(ID::ARST);
mrd.srst = cell->getPort(ID::SRST);
mrd.arst = cell->getPort(TW::ARST);
mrd.srst = cell->getPort(TW::SRST);
}
res.rd_ports.push_back(mrd);
rd_transparent.push_back(transparent);
@ -620,10 +620,10 @@ namespace {
mwr.attributes = cell->attributes;
mwr.clk_enable = cell->parameters.at(ID::CLK_ENABLE).as_bool();
mwr.clk_polarity = cell->parameters.at(ID::CLK_POLARITY).as_bool();
mwr.clk = cell->getPort(ID::CLK);
mwr.en = cell->getPort(ID::EN);
mwr.addr = cell->getPort(ID::ADDR);
mwr.data = cell->getPort(ID::DATA);
mwr.clk = cell->getPort(TW::CLK);
mwr.en = cell->getPort(TW::EN);
mwr.addr = cell->getPort(TW::ADDR);
mwr.data = cell->getPort(TW::DATA);
mwr.wide_log2 = ceil_log2(GetSize(mwr.data) / mem->width);
ports.push_back(std::make_pair(cell->parameters.at(is_compat ? ID::PRIORITY : ID::PORTID).as_int(), mwr));
}
@ -662,8 +662,8 @@ namespace {
MemInit init;
init.cell = cell;
init.attributes = cell->attributes;
auto addr = cell->getPort(ID::ADDR);
auto data = cell->getPort(ID::DATA);
auto addr = cell->getPort(TW::ADDR);
auto data = cell->getPort(TW::DATA);
if (!addr.is_fully_const())
log_error("Non-constant address %s in memory initialization %s.\n", log_signal(addr), cell);
if (!data.is_fully_const())
@ -671,7 +671,7 @@ namespace {
init.addr = addr.as_const();
init.data = data.as_const();
if (cell->type == ID($meminit_v2)) {
auto en = cell->getPort(ID::EN);
auto en = cell->getPort(TW::EN);
if (!en.is_fully_const())
log_error("Non-constant enable %s in memory initialization %s.\n", log_signal(en), cell);
init.en = en.as_const();
@ -764,10 +764,10 @@ namespace {
log_assert(ni - i == (1 << mrd.wide_log2));
mrd.clk_enable = cell->parameters.at(ID::RD_CLK_ENABLE).extract(i, 1).as_bool();
mrd.clk_polarity = cell->parameters.at(ID::RD_CLK_POLARITY).extract(i, 1).as_bool();
mrd.clk = cell->getPort(ID::RD_CLK).extract(i, 1);
mrd.en = cell->getPort(ID::RD_EN).extract(i, 1);
mrd.addr = cell->getPort(ID::RD_ADDR).extract(i * abits, abits);
mrd.data = cell->getPort(ID::RD_DATA).extract(i * res.width, (ni - i) * res.width);
mrd.clk = cell->getPort(TW::RD_CLK).extract(i, 1);
mrd.en = cell->getPort(TW::RD_EN).extract(i, 1);
mrd.addr = cell->getPort(TW::RD_ADDR).extract(i * abits, abits);
mrd.data = cell->getPort(TW::RD_DATA).extract(i * res.width, (ni - i) * res.width);
if (is_compat) {
mrd.ce_over_srst = false;
mrd.arst_value = Const(State::Sx, res.width << mrd.wide_log2);
@ -780,8 +780,8 @@ namespace {
mrd.arst_value = cell->parameters.at(ID::RD_ARST_VALUE).extract(i * res.width, (ni - i) * res.width);
mrd.srst_value = cell->parameters.at(ID::RD_SRST_VALUE).extract(i * res.width, (ni - i) * res.width);
mrd.init_value = cell->parameters.at(ID::RD_INIT_VALUE).extract(i * res.width, (ni - i) * res.width);
mrd.arst = cell->getPort(ID::RD_ARST).extract(i, 1);
mrd.srst = cell->getPort(ID::RD_SRST).extract(i, 1);
mrd.arst = cell->getPort(TW::RD_ARST).extract(i, 1);
mrd.srst = cell->getPort(TW::RD_SRST).extract(i, 1);
}
if (!is_compat) {
Const transparency_mask = cell->parameters.at(ID::RD_TRANSPARENCY_MASK).extract(i * n_wr_ports, n_wr_ports);
@ -803,10 +803,10 @@ namespace {
log_assert(ni - i == (1 << mwr.wide_log2));
mwr.clk_enable = cell->parameters.at(ID::WR_CLK_ENABLE).extract(i, 1).as_bool();
mwr.clk_polarity = cell->parameters.at(ID::WR_CLK_POLARITY).extract(i, 1).as_bool();
mwr.clk = cell->getPort(ID::WR_CLK).extract(i, 1);
mwr.en = cell->getPort(ID::WR_EN).extract(i * res.width, (ni - i) * res.width);
mwr.addr = cell->getPort(ID::WR_ADDR).extract(i * abits, abits);
mwr.data = cell->getPort(ID::WR_DATA).extract(i * res.width, (ni - i) * res.width);
mwr.clk = cell->getPort(TW::WR_CLK).extract(i, 1);
mwr.en = cell->getPort(TW::WR_EN).extract(i * res.width, (ni - i) * res.width);
mwr.addr = cell->getPort(TW::WR_ADDR).extract(i * abits, abits);
mwr.data = cell->getPort(TW::WR_DATA).extract(i * res.width, (ni - i) * res.width);
if (!is_compat) {
Const priority_mask = cell->parameters.at(ID::WR_PRIORITY_MASK).extract(i * n_wr_ports, n_wr_ports);
for (int j = 0; j < n_wr_ports; j++)
@ -1178,7 +1178,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
// The write data FF doesn't need full reset/init behavior, as it'll be masked by
// the mux whenever this would be relevant. It does, however, need to have the same
// clock enable signal as the read port.
SigSpec wdata_q = module->addWire(NEW_ID, GetSize(wport.data));
SigSpec wdata_q = module->addWire(NEW_TWINE, GetSize(wport.data));
module->addDffe(NEW_ID, rport.clk, rport.en, wport.data, wdata_q, rport.clk_polarity, true);
for (int sub = 0; sub < (1 << max_wide_log2); sub += (1 << min_wide_log2)) {
SigSpec raddr = rport.addr;
@ -1195,7 +1195,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
int ewidth = width << min_wide_log2;
int wsub = wide_write ? sub : 0;
int rsub = wide_write ? 0 : sub;
SigSpec rdata_a = module->addWire(NEW_ID, ewidth);
SigSpec rdata_a = module->addWire(NEW_TWINE, ewidth);
while (pos < ewidth) {
int epos = pos;
while (epos < ewidth && wport.en[epos + wsub * width] == wport.en[pos + wsub * width])
@ -1205,7 +1205,7 @@ void Mem::emulate_transparency(int widx, int ridx, FfInitVals *initvals) {
cond = module->And(NEW_ID, wport.en[pos + wsub * width], addr_eq);
else
cond = wport.en[pos + wsub * width];
SigSpec cond_q = module->addWire(NEW_ID);
SigSpec cond_q = module->addWire(NEW_TWINE);
// The FF for storing the bypass enable signal must be carefully
// constructed to preserve the overall init/reset/enable behavior
// of the whole port.
@ -1405,9 +1405,9 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) {
auto &port = rd_ports[idx];
log_assert(port.clk_enable);
emulate_rd_ce_over_srst(idx);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *prev_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *sel = module->addWire(NEW_ID);
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
Wire *prev_data = module->addWire(NEW_TWINE, GetSize(port.data));
Wire *sel = module->addWire(NEW_TWINE);
FfData ff_sel(module, initvals, NEW_ID);
FfData ff_data(module, initvals, NEW_ID);
ff_sel.width = 1;
@ -1465,9 +1465,9 @@ void Mem::emulate_rden(int idx, FfInitVals *initvals) {
void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, FfInitVals *initvals) {
auto &port = rd_ports[idx];
if (emu_init && !port.init_value.is_fully_undef()) {
Wire *sel = module->addWire(NEW_ID);
Wire *sel = module->addWire(NEW_TWINE);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1511,9 +1511,9 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff
port.init_value = Const(State::Sx, GetSize(port.data));
}
if (emu_arst && port.arst != State::S0) {
Wire *sel = module->addWire(NEW_ID);
Wire *sel = module->addWire(NEW_TWINE);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1551,9 +1551,9 @@ void Mem::emulate_reset(int idx, bool emu_init, bool emu_arst, bool emu_srst, Ff
port.arst = State::S0;
}
if (emu_srst && port.srst != State::S0) {
Wire *sel = module->addWire(NEW_ID);
Wire *sel = module->addWire(NEW_TWINE);
FfData ff_sel(module, initvals, NEW_ID);
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
ff_sel.width = 1;
ff_sel.has_clk = true;
ff_sel.sig_clk = port.clk;
@ -1652,10 +1652,10 @@ void Mem::emulate_read_first(FfInitVals *initvals) {
rd_ports[i].transparency_mask[j] = true;
}
for (auto &port: wr_ports) {
Wire *new_data = module->addWire(NEW_ID, GetSize(port.data));
Wire *new_addr = module->addWire(NEW_ID, GetSize(port.addr));
Wire *new_data = module->addWire(NEW_TWINE, GetSize(port.data));
Wire *new_addr = module->addWire(NEW_TWINE, GetSize(port.addr));
auto compressed = port.compress_en();
Wire *new_en = module->addWire(NEW_ID, GetSize(compressed.first));
Wire *new_en = module->addWire(NEW_TWINE, GetSize(compressed.first));
FfData ff_data(module, initvals, NEW_ID);
FfData ff_addr(module, initvals, NEW_ID);
FfData ff_en(module, initvals, NEW_ID);

18
kernel/modtools.h
View file

@ -47,11 +47,11 @@ struct ModIndex : public RTLIL::Monitor
};
struct PortInfo {
RTLIL::Cell* cell;
RTLIL::IdString port;
TwineRef port;
int offset;
PortInfo() : cell(), port(), offset() { }
PortInfo(RTLIL::Cell* _c, RTLIL::IdString _p, int _o) : cell(_c), port(_p), offset(_o) { }
PortInfo(RTLIL::Cell* _c, TwineRef _p, int _o) : cell(_c), port(_p), offset(_o) { }
bool operator<(const PortInfo &other) const {
if (cell != other.cell)
@ -98,7 +98,7 @@ struct ModIndex : public RTLIL::Monitor
int auto_reload_counter;
bool auto_reload_module;
void port_add(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
void port_add(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &sig)
{
for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
@ -107,7 +107,7 @@ struct ModIndex : public RTLIL::Monitor
}
}
void port_del(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &sig)
void port_del(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &sig)
{
for (int i = 0; i < GetSize(sig); i++) {
RTLIL::SigBit bit = sigmap(sig[i]);
@ -187,7 +187,7 @@ struct ModIndex : public RTLIL::Monitor
log_assert(ok());
}
void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
void notify_connect(RTLIL::Cell *cell, TwineRef port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
{
log_assert(module == cell->module);
@ -321,7 +321,7 @@ struct ModIndex : public RTLIL::Monitor
log(" PRIMARY OUTPUT\n");
for (auto &port : it.second.ports)
log(" PORT: %s.%s[%d] (%s)\n", port.cell,
port.port.unescape(), port.offset, port.cell->type.unescape());
module->design->twines.str(port.port), port.offset, port.cell->type.unescape());
}
}
};
@ -331,9 +331,9 @@ struct ModWalker
struct PortBit
{
RTLIL::Cell *cell;
RTLIL::IdString port;
TwineRef port;
int offset;
PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}
PortBit(Cell* c, TwineRef p, int o) : cell(c), port(p), offset(o) {}
bool operator<(const PortBit &other) const {
if (cell != other.cell)
@ -384,7 +384,7 @@ struct ModWalker
}
}
void add_cell_port(RTLIL::Cell *cell, RTLIL::IdString port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)
void add_cell_port(RTLIL::Cell *cell, TwineRef port, std::vector<RTLIL::SigBit> bits, bool is_output, bool is_input)
{
for (int i = 0; i < int(bits.size()); i++)
if (bits[i].wire != NULL) {

4
kernel/newcelltypes.h
View file

@ -586,9 +586,9 @@ struct NewCellTypes {
for (auto wire_name : module->ports) {
RTLIL::Wire *wire = module->wire(wire_name);
if (wire->port_input)
inputs.insert(wire->meta_->name_id);
inputs.insert(wire->meta_->name);
if (wire->port_output)
outputs.insert(wire->meta_->name_id);
outputs.insert(wire->meta_->name);
}
setup_type(module->name, inputs, outputs);
}

2
kernel/pmux.h
View file

@ -14,7 +14,7 @@ struct PmuxBPortIterator {
PmuxBPortIterator(Cell* mux) : cell(mux) {
log_assert(mux->type == ID($mux) || mux->type == ID($pmux));
port_idx = 0;
b = mux->getPort(ID::B).to_sigbit_vector();
b = mux->getPort(TW::B).to_sigbit_vector();
port_count = GetSize(sig_b) / s_width;
}

1934
kernel/rtlil.cc
View file

File diff suppressed because it is too large Load diff

475
kernel/rtlil.h
View file

@ -129,7 +129,6 @@ namespace RTLIL
struct OwningIdString;
struct StaticIdString;
struct SigNormIndex;
struct SrcAttr;
struct ObjMeta;
struct ModuleNameMasq;
struct WireNameMasq;
@ -139,7 +138,6 @@ namespace RTLIL
struct PortBit;
};
using SrcAttr = TwineRef;
// TODO clean up?
extern int64_t signorm_ns;
@ -806,7 +804,7 @@ namespace RTLIL {
return log_id(str);
}
template <typename T> struct sort_by_name_id {
template <typename T> struct sort_by_name {
bool operator()(T *a, T *b) const {
return a->name < b->name;
}
@ -1285,7 +1283,7 @@ struct RTLIL::ObjMeta
{
TwineRef src = Twine::Null;
// RTLIL::IdString name; // used by Module names
TwineRef name_id = Twine::Null; // used by Wire/Cell names (per-Design twines)
TwineRef name = Twine::Null; // used by Wire/Cell names (per-Design twines)
};
struct RTLIL::AttrObject
@ -1942,8 +1940,8 @@ struct RTLIL::Selection
// add whole module to this selection
template<typename T1> void select(T1 *module) {
if (!selects_all() && selected_modules.count(module->meta_->name_id) == 0) {
TwineRef name = module->meta_->name_id;
if (!selects_all() && selected_modules.count(module->meta_->name) == 0) {
TwineRef name = module->meta_->name;
selected_modules.insert(name);
selected_members.erase(name);
if (module->get_blackbox_attribute())
@ -1992,7 +1990,7 @@ struct RTLIL::Monitor
virtual ~Monitor() { }
virtual void notify_module_add(RTLIL::Module*) { }
virtual void notify_module_del(RTLIL::Module*) { }
virtual void notify_connect(RTLIL::Cell*, RTLIL::IdString, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
virtual void notify_connect(RTLIL::Cell*, TwineRef, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }
virtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }
virtual void notify_blackout(RTLIL::Module*) { }
@ -2015,7 +2013,7 @@ struct RTLIL::Design
void sigNormalize(bool enable=true);
int refcount_modules_;
dict<IdString, RTLIL::Module*> modules_;
dict<TwineRef, RTLIL::Module*> modules_;
std::vector<RTLIL::Binding*> bindings_;
TwinePool twines;
@ -2035,22 +2033,22 @@ struct RTLIL::Design
void obj_release_src(RTLIL::AttrObject *obj);
std::string obj_name(const RTLIL::AttrObject *obj) const {
return (obj->meta_ ? twines.flat_string(obj->meta_->name_id) : std::string());
return (obj->meta_ ? twines.flat_string(obj->meta_->name) : std::string());
}
void obj_set_name(RTLIL::AttrObject *obj, RTLIL::IdString name);
void obj_release_name(RTLIL::AttrObject *obj);
// void obj_set_name(RTLIL::AttrObject *obj, RTLIL::IdString name);
// void obj_release_name(RTLIL::AttrObject *obj);
// Wire/Cell names: stored as TwineRef in twines.
TwineRef obj_name_id(const RTLIL::AttrObject *obj) const {
return (obj->meta_ ? obj->meta_->name_id : Twine::Null);
}
void obj_set_name_id(RTLIL::AttrObject *obj, TwineRef id);
void obj_release_name_id(RTLIL::AttrObject *obj);
// TwineRef obj_name(const RTLIL::AttrObject *obj) const {
// return (obj->meta_ ? obj->meta_->name : Twine::Null);
// }
// void obj_set_name(RTLIL::AttrObject *obj, TwineRef id);
// void obj_release_name(RTLIL::AttrObject *obj);
// Replacements for the methods that used to live on AttrObject and
// took an explicit TwinePool*. Same semantics; the pool resolves
// to this->twines internally.
void set_src_attribute(RTLIL::AttrObject *obj, const RTLIL::SrcAttr &src);
void set_src_attribute(RTLIL::AttrObject *obj, TwineRef src);
std::string get_src_attribute(const RTLIL::AttrObject *obj) const;
void adopt_src_from(RTLIL::AttrObject *obj, const RTLIL::AttrObject *source);
void adopt_src_from(RTLIL::AttrObject *obj, const RTLIL::AttrObject *source,
@ -2097,11 +2095,12 @@ struct RTLIL::Design
RTLIL::ObjRange<RTLIL::Module*, TwineRef> modules();
RTLIL::Module *module(IdString name);
// RTLIL::Module *module(TwineRef name);
// const RTLIL::Module *module(TwineRef name) const;
const RTLIL::Module *module(IdString name) const;
RTLIL::Module *module(TwineRef name);
const RTLIL::Module *module(TwineRef name) const;
RTLIL::Module *top_module() const;
bool has(IdString id) const {
bool has(TwineRef id) const {
return modules_.count(id) != 0;
}
@ -2188,7 +2187,7 @@ struct RTLIL::Design
// is the given member of the given module in the current selection
template<typename T1, typename T2> bool selected(T1 *module, T2 *member) const {
return selected_member(module->meta_->name_id, member->meta_->name_id);
return selected_member(module->meta_->name, member->meta_->name);
}
// add whole module to the current selection
@ -2250,7 +2249,7 @@ namespace RTLIL_BACKEND {
void dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src);
}
struct RTLIL::Wire : public RTLIL::NamedObject
struct RTLIL::Wire : public RTLIL::AttrObject
{
private:
struct ConstructToken { explicit ConstructToken() = default; };
@ -2271,7 +2270,7 @@ public:
friend void RTLIL_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire, const RTLIL::Design *design, bool resolve_src);
RTLIL::Cell *driverCell_ = nullptr;
RTLIL::IdString driverPort_;
TwineRef driverPort_;
// do not simply copy wires
Wire(ConstructToken, RTLIL::Wire &other);
@ -2286,7 +2285,7 @@ public:
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
// Transfer src from `source` verbatim (same pool). Asserts attached
// to a design.
@ -2296,7 +2295,7 @@ public:
bool known_driver() const { return driverCell_ != nullptr; }
RTLIL::Cell *driverCell() const { log_assert(driverCell_); return driverCell_; };
RTLIL::IdString driverPort() const { log_assert(driverCell_); return driverPort_; };
TwineRef driverPort() const { log_assert(driverCell_); return driverPort_; };
int from_hdl_index(int hdl_index) {
int zero_index = hdl_index - start_offset;
@ -2322,7 +2321,7 @@ inline int GetSize(RTLIL::Wire *wire) {
return wire->width;
}
struct RTLIL::Memory : public RTLIL::NamedObject
struct RTLIL::Memory : public RTLIL::AttrObject
{
Hasher::hash_t hashidx_;
[[nodiscard]] Hasher hash_into(Hasher h) const { h.eat(hashidx_); return h; }
@ -2341,7 +2340,7 @@ struct RTLIL::Memory : public RTLIL::NamedObject
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2354,7 +2353,7 @@ struct RTLIL::Memory : public RTLIL::NamedObject
std::string to_rtlil_str() const;
};
struct RTLIL::Cell : public RTLIL::NamedObject
struct RTLIL::Cell : public RTLIL::AttrObject
{
private:
struct ConstructToken { explicit ConstructToken() = default; };
@ -2366,9 +2365,9 @@ private:
void initIndex();
// Signorm index helpers (used by setPort/unsetPort/initIndex)
void signorm_index_remove(RTLIL::IdString portname, const RTLIL::SigSpec &old_signal, bool is_input);
void signorm_index_add(RTLIL::IdString portname, const RTLIL::SigSpec &new_signal, bool is_input);
bool bufnorm_handle_setPort(RTLIL::IdString portname, RTLIL::SigSpec &signal, dict<RTLIL::IdString, RTLIL::SigSpec>::iterator conn_it);
void signorm_index_remove(TwineRef portname, const RTLIL::SigSpec &old_signal, bool is_input);
void signorm_index_add(TwineRef portname, const RTLIL::SigSpec &new_signal, bool is_input);
bool bufnorm_handle_setPort(TwineRef portname, RTLIL::SigSpec &signal, dict<TwineRef, RTLIL::SigSpec>::iterator conn_it);
public:
// Shadows NamedObject::name. Reads materialise via twines; writes
// are a compile error — use Module::rename(cell, new_name) instead.
@ -2387,7 +2386,7 @@ public:
RTLIL::Module *module;
IdString type;
dict<RTLIL::IdString, RTLIL::SigSpec> connections_;
dict<TwineRef, RTLIL::SigSpec> connections_;
dict<RTLIL::IdString, RTLIL::Const> parameters;
// Context-aware src helpers. Resolve Design via module->design and
@ -2395,7 +2394,7 @@ public:
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2467,7 +2466,7 @@ struct RTLIL::CaseRule : public RTLIL::AttrObject
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2495,7 +2494,7 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2520,7 +2519,7 @@ struct RTLIL::MemWriteAction : RTLIL::AttrObject
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2538,7 +2537,7 @@ struct RTLIL::SyncRule
RTLIL::SyncRule *clone() const;
};
struct RTLIL::Process : public RTLIL::NamedObject
struct RTLIL::Process : public RTLIL::AttrObject
{
friend struct RTLIL::SigNormIndex;
friend struct RTLIL::Cell;
@ -2563,7 +2562,7 @@ public:
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2578,9 +2577,9 @@ public:
struct RTLIL::PortBit
{
RTLIL::Cell *cell;
RTLIL::IdString port;
TwineRef port;
int offset;
PortBit(Cell* c, IdString p, int o) : cell(c), port(p), offset(o) {}
PortBit(Cell* c, TwineRef p, int o) : cell(c), port(p), offset(o) {}
bool operator<(const PortBit &other) const {
if (cell != other.cell)
@ -2640,9 +2639,9 @@ inline Hasher RTLIL::SigBit::hash_into(Hasher h) const {
inline Hasher RTLIL::SigBit::hash_top() const {
Hasher h;
if (wire) {
// Use the wire's name_id (TwineRef) directly — avoids IdString materialisation.
TwineRef name_id = wire->meta_ ? wire->meta_->name_id : Twine::Null;
h.eat(name_id);
// Use the wire's name (TwineRef) directly — avoids IdString materialisation.
TwineRef name = wire->meta_ ? wire->meta_->name : Twine::Null;
h.eat(name);
h.eat(offset);
return h;
}
@ -2670,212 +2669,212 @@ class CellAdderMixin {
public:
// The add* methods create a cell and return the created cell. All signals must exist in advance.
RTLIL::Cell* addNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addPos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addBuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNeg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNot (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addPos (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addBuf (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNeg (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addXor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addXnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceXor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceXnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addReduceBool (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSshl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSshr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShift (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addShiftx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addEq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addEqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addGe (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addGt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addEq (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addEqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addNex (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addGe (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addGt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addAdd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addMul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addAdd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addSub (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addMul (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
// truncating division
RTLIL::Cell* addDiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addDiv (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
// truncating modulo
RTLIL::Cell* addMod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addDivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addPow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addMod (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addDivFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addModFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addPow (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addFa (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addFa (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_x, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicNot (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addLogicOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::Cell* addMux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addPmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addDemux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addMux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addPmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addDemux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBweqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBwmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addSlice (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, TwineRef src = Twine::Null);
RTLIL::Cell* addConcat (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addLut (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, TwineRef src = Twine::Null);
RTLIL::Cell* addTribuf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAssert (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addAssume (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addLive (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addFair (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addCover (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addEquiv (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addSlice (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const offset, TwineRef src = Twine::Null);
RTLIL::Cell* addConcat (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addLut (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, RTLIL::Const lut, TwineRef src = Twine::Null);
RTLIL::Cell* addTribuf (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAssert (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addAssume (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addLive (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addFair (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addCover (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_en, TwineRef src = Twine::Null);
RTLIL::Cell* addEquiv (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addSr (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addFf (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addDff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsre (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdff (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffe (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffce (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdlatch (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatchsr (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSr (Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addFf (Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addDff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsr (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsre (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdff (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffe (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffce (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const srst_value, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatch (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdlatch (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, RTLIL::Const arst_value, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatchsr (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr, RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addBufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addXorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addXnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addMuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addBufGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAndGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNandGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOrGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addXorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addXnorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAndnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOrnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addMuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addNmuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAoi3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOai3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addAoi4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addOai4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, const RTLIL::SigBit &sig_y, TwineRef src = Twine::Null);
RTLIL::Cell* addSrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell* addSrGate (Twine &&name, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
const RTLIL::SigSpec &sig_q, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addFfGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addDffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell* addFfGate (Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addDffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsrGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDffsreGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell* addDffsreGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity = true, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addAdffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool arst_value = false, bool clk_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addAdffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool arst_value = false, bool clk_polarity = true, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addAldffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAldffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addAldffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_aload, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
const RTLIL::SigSpec &sig_ad, bool clk_polarity = true, bool en_polarity = true, bool aload_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addSdffGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool srst_value = false, bool clk_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffeGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addSdffeGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addSdffceGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addSdffceGate (Twine &&name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_srst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool srst_value = false, bool clk_polarity = true, bool en_polarity = true, bool srst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatchGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdlatchGate(RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
RTLIL::Cell* addDlatchGate (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAdlatchGate(Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_arst, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q,
bool arst_value = false, bool en_polarity = true, bool arst_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addDlatchsrGate (RTLIL::IdString name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell* addDlatchsrGate (Twine &&name, const RTLIL::SigSpec &sig_en, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool en_polarity = true, bool set_polarity = true, bool clr_polarity = true, TwineRef src = Twine::Null);
RTLIL::Cell* addAnyinit(RTLIL::IdString name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
RTLIL::Cell* addAnyinit(Twine &&name, const RTLIL::SigSpec &sig_d, const RTLIL::SigSpec &sig_q, TwineRef src = Twine::Null);
// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.
RTLIL::SigSpec Not (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Pos (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Buf (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Neg (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Not (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Pos (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Buf (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Neg (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec And (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Or (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Xor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Xnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec And (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Or (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Xor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Xnor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceXor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceXnor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceBool (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceAnd (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceOr (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceXor (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceXnor (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ReduceBool (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sshl (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sshr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shift (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shiftx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sshl (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sshr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shift (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Shiftx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Lt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Le (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Eq (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Ne (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Eqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Nex (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Ge (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Gt (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Lt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Le (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Eq (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Ne (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Eqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Nex (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Ge (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Gt (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Add (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sub (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Mul (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Add (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Sub (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Mul (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
// truncating division
RTLIL::SigSpec Div (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Div (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
// truncating modulo
RTLIL::SigSpec Mod (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec DivFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ModFloor (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Pow (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Mod (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec DivFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec ModFloor (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Pow (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool a_signed = false, bool b_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicNot (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicAnd (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicOr (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicNot (Twine &&name, const RTLIL::SigSpec &sig_a, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicAnd (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec LogicOr (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed = false, TwineRef src = Twine::Null);
RTLIL::SigSpec Mux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Pmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Bmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Demux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Mux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Pmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Bmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Demux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Bweqx (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, TwineRef src = Twine::Null);
RTLIL::SigSpec Bwmux (RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigSpec Bweqx (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, TwineRef src = Twine::Null);
RTLIL::SigSpec Bwmux (Twine &&name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit BufGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
RTLIL::SigBit NotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
RTLIL::SigBit AndGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit NandGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit OrGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit NorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit XorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit XnorGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit AndnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit OrnotGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit MuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit NmuxGate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit Aoi3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
RTLIL::SigBit Oai3Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
RTLIL::SigBit Aoi4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
RTLIL::SigBit Oai4Gate (RTLIL::IdString name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
RTLIL::SigBit BufGate (Twine &&name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
RTLIL::SigBit NotGate (Twine &&name, const RTLIL::SigBit &sig_a, TwineRef src = Twine::Null);
RTLIL::SigBit AndGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit NandGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit OrGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit NorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit XorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit XnorGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit AndnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit OrnotGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, TwineRef src = Twine::Null);
RTLIL::SigBit MuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit NmuxGate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_s, TwineRef src = Twine::Null);
RTLIL::SigBit Aoi3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
RTLIL::SigBit Oai3Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, TwineRef src = Twine::Null);
RTLIL::SigBit Aoi4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
RTLIL::SigBit Oai4Gate (Twine &&name, const RTLIL::SigBit &sig_a, const RTLIL::SigBit &sig_b, const RTLIL::SigBit &sig_c, const RTLIL::SigBit &sig_d, TwineRef src = Twine::Null);
};
// Zero-size masquerade for Module::name. Reads/writes route through
@ -2961,7 +2960,7 @@ public:
TwineRef src_id() const;
TwineRef src_ref() const { return src_id(); }
void set_src_id(TwineRef id);
void set_src_attribute(const RTLIL::SrcAttr &src);
void set_src_attribute(TwineRef src);
std::string get_src_attribute() const;
void adopt_src_from(const RTLIL::AttrObject *source);
void absorb_attrs(dict<RTLIL::IdString, RTLIL::Const> &&buf);
@ -2970,7 +2969,7 @@ public:
virtual ~Module();
virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);
virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
virtual size_t count_id(Twine* id);
virtual size_t count_id(TwineRef id);
virtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);
virtual bool reprocess_if_necessary(RTLIL::Design *design);
@ -2992,7 +2991,7 @@ public:
void fixup_ports();
pool<RTLIL::Cell *> buf_norm_cell_queue;
pool<pair<RTLIL::Cell *, RTLIL::IdString>> buf_norm_cell_port_queue;
pool<pair<RTLIL::Cell *, TwineRef>> buf_norm_cell_port_queue;
pool<RTLIL::Wire *> buf_norm_wire_queue;
pool<RTLIL::Cell *> pending_deleted_cells;
dict<RTLIL::Wire *, pool<RTLIL::Cell *>> buf_norm_connect_index;
@ -3057,7 +3056,7 @@ public:
std::vector<RTLIL::NamedObject*> selected_members() const;
template<typename T> bool selected(T *member) const {
return design->selected_member(name, member->name);
return design->selected_member(meta_->name, member->meta_->name);
}
// Primary (fast) overloads — key directly into the dict.
@ -3093,29 +3092,35 @@ public:
void remove(RTLIL::Memory *memory);
void remove(RTLIL::Process *process);
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);
void rename(RTLIL::IdString old_name, RTLIL::IdString new_name);
void rename(RTLIL::Wire *wire, TwineRef new_name);
void rename(RTLIL::Cell *cell, TwineRef new_name);
void rename(TwineRef old_name, TwineRef new_name);
void swap_names(RTLIL::Wire *w1, RTLIL::Wire *w2);
void swap_names(RTLIL::Cell *c1, RTLIL::Cell *c2);
RTLIL::IdString uniquify(RTLIL::IdString name);
RTLIL::IdString uniquify(RTLIL::IdString name, int &index);
TwineRef uniquify(TwineRef name);
TwineRef uniquify(TwineRef name, int &index);
// Primary overloads: name already interned in design->twines.
RTLIL::Wire *addWire(TwineRef name, int width = 1);
RTLIL::Wire *addWire(TwineRef name, const RTLIL::Wire *other);
// IdString compatibility: interns name into twines, then dispatches.
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
// Convenience: adds name into twines, then dispatches.
RTLIL::Wire *addWire(Twine &&name, int width = 1);
RTLIL::Wire *addWire(Twine &&name, const RTLIL::Wire *other);
// Primary overloads.
RTLIL::Cell *addCell(TwineRef name, RTLIL::IdString type);
RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other);
// IdString compatibility.
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
// Convenience.
RTLIL::Cell *addCell(Twine &&name, RTLIL::IdString type);
RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
TwineRef new_name(const std::string *prefix) {
TwineRef pref = design->twines.add(Twine{*prefix});
return design->twines.add(Twine{Twine::Suffix{pref, std::to_string(autoidx++)}});
}
RTLIL::Memory *addMemory(RTLIL::IdString name);
RTLIL::Memory *addMemory(RTLIL::IdString name, const RTLIL::Memory *other);
@ -3129,18 +3134,18 @@ public:
// The methods without the add* prefix create a cell and an output signal. They return the newly created output signal.
RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Initstate (RTLIL::IdString name, TwineRef src = Twine::Null);
RTLIL::SigSpec Anyconst (TwineRef name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Anyseq (TwineRef name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Allconst (TwineRef name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Allseq (TwineRef name, int width = 1, TwineRef src = Twine::Null);
RTLIL::SigSpec Initstate (TwineRef name, TwineRef src = Twine::Null);
RTLIL::SigSpec SetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
RTLIL::Cell* addSetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::SigSpec GetTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
RTLIL::Cell* addOverwriteTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
RTLIL::SigSpec OriginalTag (RTLIL::IdString name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
RTLIL::SigSpec FutureFF (RTLIL::IdString name, const RTLIL::SigSpec &sig_e, TwineRef src = Twine::Null);
RTLIL::SigSpec SetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
RTLIL::Cell* addSetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, const RTLIL::SigSpec &sig_y, TwineRef src = Twine::Null);
RTLIL::SigSpec GetTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
RTLIL::Cell* addOverwriteTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_c, TwineRef src = Twine::Null);
RTLIL::SigSpec OriginalTag (TwineRef name, const std::string &tag, const RTLIL::SigSpec &sig_a, TwineRef src = Twine::Null);
RTLIL::SigSpec FutureFF (TwineRef name, const RTLIL::SigSpec &sig_e, TwineRef src = Twine::Null);
std::string to_rtlil_str() const;
#ifdef YOSYS_ENABLE_PYTHON
@ -3276,7 +3281,7 @@ inline RTLIL::WireNameMasq::operator RTLIL::IdString() const {
reinterpret_cast<const char *>(this) - offsetof(RTLIL::Wire, name));
if (!w->module || !w->module->design || !w->meta_)
return RTLIL::IdString{};
TwineRef id = w->meta_->name_id;
TwineRef id = w->meta_->name;
if (id == Twine::Null)
return RTLIL::IdString{};
return RTLIL::IdString(w->module->design->twines.flat_string(id));
@ -3287,7 +3292,7 @@ inline RTLIL::CellNameMasq::operator RTLIL::IdString() const {
reinterpret_cast<const char *>(this) - offsetof(RTLIL::Cell, name));
if (!c->module || !c->module->design || !c->meta_)
return RTLIL::IdString{};
TwineRef id = c->meta_->name_id;
TwineRef id = c->meta_->name;
if (id == Twine::Null)
return RTLIL::IdString{};
return RTLIL::IdString(c->module->design->twines.flat_string(id));

97
kernel/rtlil_bufnorm.cc
View file

@ -20,6 +20,7 @@
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
#include "kernel/modtools.h"
#include "kernel/yosys_common.h"
#include <string.h>
#include <algorithm>
@ -28,7 +29,7 @@
YOSYS_NAMESPACE_BEGIN
typedef std::pair<Cell*, IdString> cell_port_t;
typedef std::pair<Cell*, TwineRef> cell_port_t;
// Since this is kernel code, we only log with yosys_xtrace set to not get
// in the way when using `debug` to debug specific passes.q
@ -83,7 +84,7 @@ struct RTLIL::SigNormIndex
if (cell->type != ID($input_port))
continue;
auto const &sig_y = cell->getPort(ID::Y);
auto const &sig_y = cell->getPort(TW::Y);
Wire *wire;
if (sig_y.is_wire() && (wire = sig_y.as_wire())->port_input && !wire->port_output && !input_port_cells.count(wire))
input_port_cells.emplace(wire, cell);
@ -97,16 +98,16 @@ struct RTLIL::SigNormIndex
for (auto portname : module->ports) {
Wire *wire = module->wire(portname);
if (wire->port_input && !wire->port_output && !input_port_cells.count(wire)) {
Cell *cell = module->addCell(NEW_ID, ID($input_port));
Cell *cell = module->addCell(NEW_TWINE, ID($input_port));
cell->setParam(ID::WIDTH, GetSize(wire));
cell->setPort(ID::Y, wire);
cell->setPort(TW::Y, wire);
input_port_cells.emplace(wire, cell);
}
}
for (auto [wire, cell] : input_port_cells) {
wire->driverCell_ = cell;
wire->driverPort_ = ID::Y;
wire->driverPort_ = TW::Y;
}
}
@ -130,7 +131,7 @@ struct RTLIL::SigNormIndex
}
}
Wire *wire = module->addWire(NEW_ID, GetSize(sig));
Wire *wire = module->addWire(NEW_TWINE, GetSize(sig));
wire->driverCell_ = cell;
wire->driverPort_ = port;
@ -194,11 +195,11 @@ struct RTLIL::SigNormIndex
}
if (!connect_lhs.empty()) {
Cell *cell = module->addCell(NEW_ID, ID($connect));
Cell *cell = module->addCell(NEW_TWINE, ID($connect));
xlog("add connect (1) %s\n", cell->name);
cell->setParam(ID::WIDTH, GetSize(connect_lhs));
cell->setPort(ID::A, std::move(connect_lhs));
cell->setPort(ID::B, std::move(connect_rhs));
cell->setPort(TW::A, std::move(connect_lhs));
cell->setPort(TW::B, std::move(connect_rhs));
}
}
@ -287,7 +288,7 @@ void RTLIL::Design::bufNormalize(bool enable)
module->buf_norm_cell_port_queue.clear();
for (auto wire : module->wires()) {
wire->driverCell_ = nullptr;
wire->driverPort_ = IdString();
wire->driverPort_ = Twine::Null;
}
module->buf_norm_connect_index.clear();
}
@ -348,7 +349,7 @@ void RTLIL::Design::sigNormalize(bool enable)
for (auto wire : module->wires()) {
wire->driverCell_ = nullptr;
wire->driverPort_ = IdString();
wire->driverPort_ = Twine::Null;
}
// TODO inefficient?
@ -520,14 +521,14 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
while (!cell->connections_.empty())
cell->unsetPort(cell->connections_.begin()->first);
log_assert(cell->meta_ && cell->meta_->name_id != Twine::Null);
TwineRef cell_id = cell->meta_->name_id;
log_assert(cell->meta_ && cell->meta_->name != Twine::Null);
TwineRef cell_id = cell->meta_->name;
log_assert(cells_.count(cell_id) != 0);
log_assert(refcount_cells_ == 0);
cells_.erase(cell_id);
if (design && design->flagBufferedNormalized && buf_norm_cell_queue.count(cell)) {
cell->type.clear();
design->obj_release_name_id(cell);
// design->obj_release_name(cell);
pending_deleted_cells.insert(cell);
} else {
if (sig_norm_index != nullptr) {
@ -561,12 +562,12 @@ void RTLIL::Module::bufNormalize()
if (wire->port_input && !wire->port_output) {
if (wire->driverCell_ != nullptr && wire->driverCell_->type != ID($input_port)) {
wire->driverCell_ = nullptr;
wire->driverPort_.clear();
wire->driverPort_ = Twine::Null;
}
if (wire->driverCell_ == nullptr) {
Cell *input_port_cell = addCell(NEW_ID, ID($input_port));
Cell *input_port_cell = addCell(NEW_TWINE, ID($input_port));
input_port_cell->setParam(ID::WIDTH, GetSize(wire));
input_port_cell->setPort(ID::Y, wire); // this hits the fast path that doesn't mutate the queues
input_port_cell->setPort(TW::Y, wire); // this hits the fast path that doesn't mutate the queues
}
}
}
@ -593,19 +594,19 @@ void RTLIL::Module::bufNormalize()
// because it's not driving an input port or because there already is
// another $input_port driver for the same port, we also delete that
// $input_port cell.
dict<Wire *, std::pair<Cell *, IdString>> direct_driven_wires;
dict<Wire *, std::pair<Cell *, TwineRef>> direct_driven_wires;
// Set of cell ports that need a fresh intermediate wire. These are all
// cell ports that drive non-full-wire sigspecs, cell ports driving
// module input ports, and cell ports driving wires that are already
// driven.
pool<std::pair<Cell *, IdString>> pending_ports;
pool<std::pair<Cell *, TwineRef>> pending_ports;
// This helper will be called for every output/inout cell port that is
// already enqueued or becomes reachable when denormalizing $buf or
// $connect cells.
auto enqueue_cell_port = [&](Cell *cell, IdString port) {
xlog("processing cell port %s.%s\n", cell, port.unescape());
auto enqueue_cell_port = [&](Cell *cell, TwineRef port) {
xlog("processing cell port %s.%s\n", cell, design->twines.str(port));
// An empty cell type means the cell got removed
if (cell->type.empty())
@ -632,8 +633,8 @@ void RTLIL::Module::bufNormalize()
// TODO: We could defer removing the $buf cells here, and
// re-use them in case we would create a new identical cell
// later.
log_assert(port == ID::Y);
SigSpec sig_a = cell->getPort(ID::A);
log_assert(port == TW::Y);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_y = sig;
for (auto const &s : {sig_a, sig})
@ -662,7 +663,7 @@ void RTLIL::Module::bufNormalize()
buf_norm_wire_queue.clear();
return;
} else if (cell->type == ID($input_port)) {
log_assert(port == ID::Y);
log_assert(port == TW::Y);
if (sig.is_wire()) {
Wire *w = sig.as_wire();
if (w->port_input && !w->port_output) {
@ -733,7 +734,7 @@ void RTLIL::Module::bufNormalize()
if (wire->driverCell_) {
Cell *cell = wire->driverCell_;
IdString port = wire->driverPort_;
TwineRef port = wire->driverPort_;
enqueue_cell_port(cell, port);
}
@ -744,8 +745,8 @@ void RTLIL::Module::bufNormalize()
while (!found->second.empty()) {
Cell *connect_cell = *found->second.begin();
log_assert(connect_cell->type == ID($connect));
SigSpec const &sig_a = connect_cell->getPort(ID::A);
SigSpec const &sig_b = connect_cell->getPort(ID::B);
SigSpec const &sig_a = connect_cell->getPort(TW::A);
SigSpec const &sig_b = connect_cell->getPort(TW::B);
xlog("found $connect cell %s: %s <-> %s\n", connect_cell, log_signal(sig_a), log_signal(sig_b));
for (auto &side : {sig_a, sig_b})
for (auto chunk : side.chunks())
@ -772,7 +773,7 @@ void RTLIL::Module::bufNormalize()
log_assert(!cell->type.empty());
log_assert(!pending_deleted_cells.count(cell));
SigSpec const &sig = cell->getPort(port);
Wire *w = addWire(NEW_ID, GetSize(sig));
Wire *w = addWire(NEW_TWINE, GetSize(sig));
// We update the module level connections, `direct_driven_wires`
// and `direct_driven_wires_conflicts` in such a way that they
@ -792,7 +793,7 @@ void RTLIL::Module::bufNormalize()
// to keep track of the wires that we still have to update.
for (auto wire : wire_queue_entries) {
wire->driverCell_ = nullptr;
wire->driverPort_.clear();
wire->driverPort_ = Twine::Null;
}
// For the unique driving cell ports fully connected to a full wire, we
@ -912,7 +913,7 @@ void RTLIL::Module::bufNormalize()
if (wire->driverCell_ == nullptr) {
xlog("wire %s drivers %s\n", wire, log_signal(wire_drivers));
addBuf(NEW_ID, wire_drivers, wire);
addBuf(NEW_TWINE, wire_drivers, wire);
}
}
@ -946,10 +947,10 @@ void RTLIL::Module::bufNormalize()
if (sig_a.empty())
return;
xlog("connect %s <-> %s\n", log_signal(sig_a), log_signal(sig_b));
Cell *connect_cell = addCell(NEW_ID, ID($connect));
Cell *connect_cell = addCell(NEW_TWINE, ID($connect));
connect_cell->setParam(ID::WIDTH, GetSize(sig_a));
connect_cell->setPort(ID::A, sig_a);
connect_cell->setPort(ID::B, sig_b);
connect_cell->setPort(TW::A, sig_a);
connect_cell->setPort(TW::B, sig_b);
sig_a = SigSpec();
sig_b = SigSpec();
};
@ -985,7 +986,7 @@ void RTLIL::Module::bufNormalize()
pending_deleted_cells.clear();
}
void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
void RTLIL::Cell::unsetPort(TwineRef portname)
{
RTLIL::SigSpec signal;
auto conn_it = connections_.find(portname);
@ -1000,7 +1001,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
mon->notify_connect(this, conn_it->first, conn_it->second, signal);
if (yosys_xtrace) {
log("#X# Unconnect %s.%s.%s\n", this->module, this, portname.unescape());
log("#X# Unconnect %s.%s.%s\n", module, this, module->design->twines.str(portname));
log_backtrace("-X- ", yosys_xtrace-1);
}
@ -1026,14 +1027,14 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
log_assert(w->driverCell_ == this);
log_assert(w->driverPort_ == portname);
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
w->driverPort_ = Twine::Null;
}
// bool clear_fanout = true;
// if (conn_it->second.is_wire()) {
// Wire *w = conn_it->second.as_wire();
// if (w->driverCell_ == this && w->driverPort_ == portname) {
// w->driverCell_ = nullptr;
// w->driverPort_ = IdString();
// w->driverPort_ = Twine::Null;
// clear_fanout = false;
// }
// }
@ -1058,7 +1059,7 @@ void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
Wire *w = conn_it->second.as_wire();
if (w->driverCell_ == this && w->driverPort_ == portname) {
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
w->driverPort_ = Twine::Null;
module->buf_norm_wire_queue.insert(w);
} else if (w->driverCell_) {
log_assert(w->driverCell_->getPort(w->driverPort_) == w);
@ -1099,7 +1100,7 @@ static bool ignored_cell(const RTLIL::IdString& type)
return type == ID($specify2) || type == ID($specify3) || type == ID($specrule);
}
void RTLIL::Cell::signorm_index_remove(IdString portname, const SigSpec &old_signal, bool is_input)
void RTLIL::Cell::signorm_index_remove(TwineRef portname, const SigSpec &old_signal, bool is_input)
{
auto &index = *module->sig_norm_index;
index.dirty.insert(this);
@ -1121,11 +1122,11 @@ void RTLIL::Cell::signorm_index_remove(IdString portname, const SigSpec &old_sig
log_assert(w->driverCell_ == this);
log_assert(w->driverPort_ == portname);
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
w->driverPort_ = Twine::Null;
}
}
void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal, bool is_input)
void RTLIL::Cell::signorm_index_add(TwineRef portname, const SigSpec &new_signal, bool is_input)
{
auto &index = *module->sig_norm_index;
index.dirty.insert(this);
@ -1140,7 +1141,7 @@ void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal
} else if (GetSize(new_signal)) {
Wire *w = new_signal.as_wire();
log_assert(w->driverCell_ == nullptr);
log_assert(w->driverPort_.empty());
log_assert(w->driverPort_ == Twine::Null);
w->driverCell_ = this;
w->driverPort_ = portname;
}
@ -1148,14 +1149,14 @@ void RTLIL::Cell::signorm_index_add(IdString portname, const SigSpec &new_signal
// Handles the bufnorm part of setPort. Updates conn_it->second and returns true if the
// connection was stored (fast path or $connect cell). If false, caller must store signal.
bool RTLIL::Cell::bufnorm_handle_setPort(IdString portname, SigSpec &signal, dict<IdString, SigSpec>::iterator conn_it)
bool RTLIL::Cell::bufnorm_handle_setPort(TwineRef portname, SigSpec &signal, dict<TwineRef, SigSpec>::iterator conn_it)
{
// Eagerly clear a driver that got disconnected by changing this port connection
if (conn_it->second.is_wire()) {
Wire *w = conn_it->second.as_wire();
if (w->driverCell_ == this && w->driverPort_ == portname) {
w->driverCell_ = nullptr;
w->driverPort_ = IdString();
w->driverPort_ = Twine::Null;
module->buf_norm_wire_queue.insert(w);
}
}
@ -1260,7 +1261,7 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal)
if (signal.is_wire() && (wire = signal.as_wire())->driverCell_ != nullptr)
wire = nullptr;
if (wire == nullptr) {
wire = module->addWire(NEW_ID, GetSize(signal));
wire = module->addWire(NEW_TWINE, GetSize(signal));
module->connect(signal, wire);
signal = wire;
}
@ -1282,7 +1283,7 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal)
}
if (yosys_xtrace) {
log("#X# Connect %s.%s.%s = %s (%d)\n", this->module ? this->module->name.unescape() : "PATCH", this, portname.unescape(), log_signal(signal), GetSize(signal));
log("#X# Connect %s.%s.%s = %s (%d)\n", module ? module->name.unescape() : "PATCH", this, module->design->twines.str(portname), log_signal(signal), GetSize(signal));
log_backtrace("-X- ", yosys_xtrace-1);
}
@ -1302,9 +1303,9 @@ void RTLIL::Cell::setPort(TwineRef portname, RTLIL::SigSpec signal)
void RTLIL::Design::add(RTLIL::Module *module)
{
log_assert(modules_.count(module->name) == 0);
log_assert(modules_.count(module->meta_->name) == 0);
log_assert(refcount_modules_ == 0);
modules_[module->name] = module;
modules_[module->meta_->name] = module;
module->design = this;
for (auto mon : monitors)

356
kernel/satgen.cc
View file

@ -30,9 +30,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef && (cell->type.in(ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($divfloor), ID($modfloor)) || is_arith_compare))
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
if (is_arith_compare)
extendSignalWidth(undef_a, undef_b, cell, true);
else
@ -43,7 +43,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
int undef_y_bit = ez->OR(undef_any_a, undef_any_b);
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor))) {
std::vector<int> b = importSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> b = importSigSpec(cell->getPort(TW::B), timestep);
undef_y_bit = ez->OR(undef_y_bit, ez->NOT(ez->expression(ezSAT::OpOr, b)));
}
@ -62,9 +62,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_),
ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($sub)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -92,9 +92,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef && !arith_undef_handled)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell, false);
if (cell->type.in(ID($and), ID($_AND_), ID($_NAND_))) {
@ -133,7 +133,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
}
else if (model_undef)
{
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -144,11 +144,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
bool aoi_mode = cell->type.in(ID($_AOI3_), ID($_AOI4_));
bool three_mode = cell->type.in(ID($_AOI3_), ID($_OAI3_));
int a = importDefSigSpec(cell->getPort(ID::A), timestep).at(0);
int b = importDefSigSpec(cell->getPort(ID::B), timestep).at(0);
int c = importDefSigSpec(cell->getPort(ID::C), timestep).at(0);
int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(ID::D), timestep).at(0);
int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
int a = importDefSigSpec(cell->getPort(TW::A), timestep).at(0);
int b = importDefSigSpec(cell->getPort(TW::B), timestep).at(0);
int c = importDefSigSpec(cell->getPort(TW::C), timestep).at(0);
int d = three_mode ? (aoi_mode ? ez->CONST_TRUE : ez->CONST_FALSE) : importDefSigSpec(cell->getPort(TW::D), timestep).at(0);
int y = importDefSigSpec(cell->getPort(TW::Y), timestep).at(0);
int yy = model_undef ? ez->literal() : y;
if (cell->type.in(ID($_AOI3_), ID($_AOI4_)))
@ -158,11 +158,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
int undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep).at(0);
int undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep).at(0);
int undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep).at(0);
int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(ID::D), timestep).at(0);
int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
int undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep).at(0);
int undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep).at(0);
int undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep).at(0);
int undef_d = three_mode ? ez->CONST_FALSE : importUndefSigSpec(cell->getPort(TW::D), timestep).at(0);
int undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep).at(0);
if (aoi_mode)
{
@ -207,16 +207,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($_NOT_), ID($not)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
ez->assume(ez->vec_eq(ez->vec_not(a), yy));
if (model_undef) {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, false);
ez->assume(ez->vec_eq(undef_a, undef_y));
undefGating(y, yy, undef_y);
@ -226,17 +226,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($bweqx))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> bweqx = ez->vec_not(ez->vec_xor(a, b));
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> both_undef = ez->vec_and(undef_a, undef_b);
std::vector<int> both_def = ez->vec_and(ez->vec_not(undef_a), ez->vec_not(undef_b));
@ -252,10 +252,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($_MUX_), ID($mux), ID($_NMUX_), ID($bwmux)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (cell->type == ID($_NMUX_))
@ -267,10 +267,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> unequal_ab = ez->vec_not(ez->vec_iff(a, b));
std::vector<int> undef_ab = ez->vec_or(unequal_ab, ez->vec_or(undef_a, undef_b));
@ -287,16 +287,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($bmux))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> undef_a, undef_s, undef_y;
if (model_undef)
{
undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep);
undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
}
if (GetSize(s) == 0) {
@ -335,17 +335,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($demux))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> undef_a, undef_s, undef_y;
if (model_undef)
{
undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep);
undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
}
if (GetSize(s) == 0) {
@ -387,10 +387,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($pmux))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> s = importDefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -403,10 +403,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(ID::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_s = importUndefSigSpec(cell->getPort(TW::S), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
int all_undef = ez->CONST_FALSE;
int found_active = ez->CONST_FALSE;
@ -433,8 +433,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($pos), ID($buf), ID($neg)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -448,8 +448,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell);
if (cell->type.in(ID($pos), ID($buf))) {
@ -467,8 +467,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($connect)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
extendSignalWidthUnary(a, b, cell);
std::vector<int> bb = model_undef ? ez->vec_var(b.size()) : b;
@ -476,8 +476,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
extendSignalWidthUnary(undef_a, undef_b, cell);
ez->assume(ez->vec_eq(undef_a, undef_b));
undefGating(b, bb, undef_b);
@ -487,8 +487,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($logic_not)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -507,8 +507,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
int aX = ez->expression(ezSAT::OpOr, undef_a);
if (cell->type == ID($reduce_and)) {
@ -534,12 +534,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($logic_and), ID($logic_or)))
{
std::vector<int> vec_a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> vec_b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> vec_a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> vec_b = importDefSigSpec(cell->getPort(TW::B), timestep);
int a = ez->expression(ez->OpOr, vec_a);
int b = ez->expression(ez->OpOr, vec_b);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -552,9 +552,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
int a0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_a), ez->expression(ezSAT::OpOr, undef_a)));
int b0 = ez->NOT(ez->OR(ez->expression(ezSAT::OpOr, vec_b), ez->expression(ezSAT::OpOr, undef_b)));
@ -581,16 +581,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)))
{
bool is_signed = cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool();
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(a, b, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
if (model_undef && cell->type.in(ID($eqx), ID($nex))) {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
a = ez->vec_or(a, undef_a);
b = ez->vec_or(b, undef_b);
@ -613,9 +613,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef && cell->type.in(ID($eqx), ID($nex)))
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
if (cell->type == ID($eqx))
@ -630,9 +630,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
}
else if (model_undef && cell->type.in(ID($eq), ID($ne)))
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(undef_a, undef_b, cell, true);
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
@ -654,7 +654,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
else
{
if (model_undef) {
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
undefGating(y, yy, undef_y);
}
log_assert(!model_undef || arith_undef_handled);
@ -664,9 +664,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
int extend_bit = ez->CONST_FALSE;
@ -697,9 +697,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> undef_a_shifted;
extend_bit = cell->type == ID($shiftx) ? ez->CONST_TRUE : ez->CONST_FALSE;
@ -736,9 +736,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($mul))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -755,7 +755,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef) {
log_assert(arith_undef_handled);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -763,8 +763,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($macc), ID($macc_v2)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
Macc macc;
macc.from_cell(cell);
@ -807,19 +807,19 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_c;
if (cell->type == ID($macc_v2))
undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep);
undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep);
int undef_any_a = ez->expression(ezSAT::OpOr, undef_a);
int undef_any_b = ez->expression(ezSAT::OpOr, undef_b);
int undef_any_c = ez->expression(ezSAT::OpOr, undef_c);
int undef_any = ez->OR(undef_any_a, ez->OR(undef_any_b, undef_any_c));
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
ez->assume(ez->vec_eq(undef_y, std::vector<int>(GetSize(y), undef_any)));
undefGating(y, tmp, undef_y);
@ -832,9 +832,9 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($div), ID($mod), ID($divfloor), ID($modfloor)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidth(a, b, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
@ -913,12 +913,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
only_first_one.at(0) = ez->CONST_TRUE;
div_zero_result = ez->vec_ite(a.back(), only_first_one, all_ones);
} else {
div_zero_result.insert(div_zero_result.end(), cell->getPort(ID::A).size(), ez->CONST_TRUE);
div_zero_result.insert(div_zero_result.end(), cell->getPort(TW::A).size(), ez->CONST_TRUE);
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), ez->CONST_FALSE);
}
} else if (cell->type.in(ID($mod), ID($modfloor))) {
// a mod 0 = a
int copy_a_bits = min(cell->getPort(ID::A).size(), cell->getPort(ID::B).size());
int copy_a_bits = min(cell->getPort(TW::A).size(), cell->getPort(TW::B).size());
div_zero_result.insert(div_zero_result.end(), a.begin(), a.begin() + copy_a_bits);
if (cell->parameters[ID::A_SIGNED].as_bool() && cell->parameters[ID::B_SIGNED].as_bool())
div_zero_result.insert(div_zero_result.end(), y.size() - div_zero_result.size(), div_zero_result.back());
@ -930,7 +930,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef) {
log_assert(arith_undef_handled);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
undefGating(y, yy, undef_y);
}
return true;
@ -938,8 +938,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($lut))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> lut;
for (auto bit : cell->getParam(ID::LUT))
@ -950,7 +950,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> t(lut), u(GetSize(t), ez->CONST_FALSE);
for (int i = GetSize(a)-1; i >= 0; i--)
@ -968,7 +968,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
log_assert(GetSize(t) == 1);
log_assert(GetSize(u) == 1);
undefGating(y, t, u);
ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(ID::Y), timestep), u));
ez->assume(ez->vec_eq(importUndefSigSpec(cell->getPort(TW::Y), timestep), u));
}
else
{
@ -988,8 +988,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($sop))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
int y = importDefSigSpec(cell->getPort(ID::Y), timestep).at(0);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
int y = importDefSigSpec(cell->getPort(TW::Y), timestep).at(0);
int width = cell->getParam(ID::WIDTH).as_int();
int depth = cell->getParam(ID::DEPTH).as_int();
@ -1017,8 +1017,8 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> products, undef_products;
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
int undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep).at(0);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
int undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep).at(0);
for (int i = 0; i < depth; i++)
{
@ -1070,11 +1070,11 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($fa))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> c = importDefSigSpec(cell->getPort(ID::C), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> c = importDefSigSpec(cell->getPort(TW::C), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(TW::X), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
std::vector<int> xx = model_undef ? ez->vec_var(x.size()) : x;
@ -1088,12 +1088,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_c = importUndefSigSpec(cell->getPort(ID::C), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_c = importUndefSigSpec(cell->getPort(TW::C), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(TW::X), timestep);
ez->assume(ez->vec_eq(undef_y, ez->vec_or(ez->vec_or(undef_a, undef_b), undef_c)));
ez->assume(ez->vec_eq(undef_x, undef_y));
@ -1106,10 +1106,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($lcu))
{
std::vector<int> p = importDefSigSpec(cell->getPort(ID::P), timestep);
std::vector<int> g = importDefSigSpec(cell->getPort(ID::G), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> p = importDefSigSpec(cell->getPort(TW::P), timestep);
std::vector<int> g = importDefSigSpec(cell->getPort(TW::G), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(TW::CI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(TW::CO), timestep);
std::vector<int> yy = model_undef ? ez->vec_var(co.size()) : co;
@ -1118,10 +1118,10 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_p = importUndefSigSpec(cell->getPort(ID::P), timestep);
std::vector<int> undef_g = importUndefSigSpec(cell->getPort(ID::G), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> undef_p = importUndefSigSpec(cell->getPort(TW::P), timestep);
std::vector<int> undef_g = importUndefSigSpec(cell->getPort(TW::G), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(TW::CI), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(TW::CO), timestep);
int undef_any_p = ez->expression(ezSAT::OpOr, undef_p);
int undef_any_g = ez->expression(ezSAT::OpOr, undef_g);
@ -1138,13 +1138,13 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($alu))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> bi = importDefSigSpec(cell->getPort(ID::BI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> b = importDefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> x = importDefSigSpec(cell->getPort(TW::X), timestep);
std::vector<int> ci = importDefSigSpec(cell->getPort(TW::CI), timestep);
std::vector<int> bi = importDefSigSpec(cell->getPort(TW::BI), timestep);
std::vector<int> co = importDefSigSpec(cell->getPort(TW::CO), timestep);
extendSignalWidth(a, b, y, cell);
extendSignalWidth(a, b, x, cell);
@ -1169,14 +1169,14 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (model_undef)
{
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(ID::B), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(ID::CI), timestep);
std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(ID::BI), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_b = importUndefSigSpec(cell->getPort(TW::B), timestep);
std::vector<int> undef_ci = importUndefSigSpec(cell->getPort(TW::CI), timestep);
std::vector<int> undef_bi = importUndefSigSpec(cell->getPort(TW::BI), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(ID::X), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(ID::CO), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> undef_x = importUndefSigSpec(cell->getPort(TW::X), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort(TW::CO), timestep);
extendSignalWidth(undef_a, undef_b, undef_y, cell);
extendSignalWidth(undef_a, undef_b, undef_x, cell);
@ -1204,17 +1204,17 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($slice))
{
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec y = cell->getPort(TW::Y);
ez->assume(signals_eq(a.extract(cell->parameters.at(ID::OFFSET).as_int(), y.size()), y, timestep));
return true;
}
if (cell->type == ID($concat))
{
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec b = cell->getPort(ID::B);
RTLIL::SigSpec y = cell->getPort(ID::Y);
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec b = cell->getPort(TW::B);
RTLIL::SigSpec y = cell->getPort(TW::Y);
RTLIL::SigSpec ab = a;
ab.append(b);
@ -1233,18 +1233,18 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (timestep == 1)
{
initial_state.add((*sigmap)(cell->getPort(ID::Q)));
initial_state.add((*sigmap)(cell->getPort(TW::Q)));
if (model_undef && def_formal) {
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Q), timestep);
ez->assume(ez->NOT(ez->vec_reduce_or(undef_q)));
}
}
else
{
std::vector<int> d = importDefSigSpec(cell->getPort(ID::D), timestep-1);
std::vector<int> d = importDefSigSpec(cell->getPort(TW::D), timestep-1);
std::vector<int> undef_d;
if (model_undef)
undef_d = importUndefSigSpec(cell->getPort(ID::D), timestep-1);
undef_d = importUndefSigSpec(cell->getPort(TW::D), timestep-1);
if (ff.has_srst && ff.has_ce && ff.ce_over_srst) {
int srst = importDefSigSpec(ff.sig_srst, timestep-1).at(0);
std::vector<int> rval = importDefSigSpec(ff.val_srst, timestep-1);
@ -1287,14 +1287,14 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
else
std::tie(d, undef_d) = mux(srst, undef_srst, rval, undef_rval, d, undef_d);
}
std::vector<int> q = importDefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> q = importDefSigSpec(cell->getPort(TW::Q), timestep);
std::vector<int> qq = model_undef ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq));
if (model_undef)
{
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Q), timestep);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Q), timestep);
ez->assume(ez->vec_eq(undef_d, undef_q));
undefGating(q, qq, undef_q);
@ -1307,22 +1307,22 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
{
if (timestep < 2) {
if (model_undef && def_formal) {
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
ez->assume(ez->NOT(ez->vec_reduce_or(undef_y)));
}
return true;
}
std::vector<int> d = importDefSigSpec(cell->getPort(ID::Y), timestep-1);
std::vector<int> q = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> d = importDefSigSpec(cell->getPort(TW::Y), timestep-1);
std::vector<int> q = importDefSigSpec(cell->getPort(TW::Y), timestep);
std::vector<int> qq = (model_undef && !def_formal) ? ez->vec_var(q.size()) : q;
ez->assume(ez->vec_eq(d, qq));
if (model_undef)
{
std::vector<int> undef_d = importUndefSigSpec(cell->getPort(ID::Y), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_d = importUndefSigSpec(cell->getPort(TW::Y), timestep-1);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Y), timestep);
if (def_formal) {
for (auto &undef_q_bit : undef_q)
@ -1338,7 +1338,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($anyseq))
{
if (model_undef && def_formal) {
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_q = importUndefSigSpec(cell->getPort(TW::Y), timestep);
for (auto &undef_q_bit : undef_q)
ez->SET(ez->CONST_FALSE, undef_q_bit);
}
@ -1347,16 +1347,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type.in(ID($_BUF_), ID($equiv)))
{
std::vector<int> a = importDefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> a = importDefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(a, y, cell);
std::vector<int> yy = model_undef ? ez->vec_var(y.size()) : y;
ez->assume(ez->vec_eq(a, yy));
if (model_undef) {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(ID::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_a = importUndefSigSpec(cell->getPort(TW::A), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
extendSignalWidthUnary(undef_a, undef_y, cell, false);
ez->assume(ez->vec_eq(undef_a, undef_y));
undefGating(y, yy, undef_y);
@ -1370,12 +1370,12 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (initstates.count(key) == 0)
initstates[key] = false;
std::vector<int> y = importDefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> y = importDefSigSpec(cell->getPort(TW::Y), timestep);
log_assert(GetSize(y) == 1);
ez->SET(y[0], initstates[key] ? ez->CONST_TRUE : ez->CONST_FALSE);
if (model_undef) {
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(ID::Y), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort(TW::Y), timestep);
log_assert(GetSize(undef_y) == 1);
ez->SET(undef_y[0], ez->CONST_FALSE);
}
@ -1386,16 +1386,16 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep)
if (cell->type == ID($assert))
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
asserts_a[pf].append((*sigmap)(cell->getPort(ID::A)));
asserts_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
asserts_a[pf].append((*sigmap)(cell->getPort(TW::A)));
asserts_en[pf].append((*sigmap)(cell->getPort(TW::EN)));
return true;
}
if (cell->type == ID($assume))
{
std::string pf = prefix + (timestep == -1 ? "" : stringf("@%d:", timestep));
assumes_a[pf].append((*sigmap)(cell->getPort(ID::A)));
assumes_en[pf].append((*sigmap)(cell->getPort(ID::EN)));
assumes_a[pf].append((*sigmap)(cell->getPort(TW::A)));
assumes_en[pf].append((*sigmap)(cell->getPort(TW::EN)));
return true;
}

4
kernel/sigtools.h
View file

@ -233,9 +233,9 @@ struct SigSet
template<typename T>
class SigSet<T, typename std::enable_if<!std::is_pointer<T>::value>::type> : public SigSet<T, std::less<T>> {};
template<typename T>
using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;
using sort_by_name_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell*>::value>::type;
template<typename T>
class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
class SigSet<T, sort_by_name_guard<T>> : public SigSet<T, RTLIL::sort_by_name<typename std::remove_pointer<T>::type>> {};
struct SigMapView
{

14
kernel/timinginfo.h
View file

@ -98,11 +98,11 @@ struct TimingInfo
for (auto cell : module->cells()) {
if (cell->type == ID($specify2)) {
auto en = cell->getPort(ID::EN);
auto en = cell->getPort(TW::EN);
if (en.is_fully_const() && !en.as_bool())
continue;
auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID::DST);
auto src = cell->getPort(TW::SRC);
auto dst = cell->getPort(TW::DST);
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
@ -136,8 +136,8 @@ struct TimingInfo
}
}
else if (cell->type == ID($specify3)) {
auto src = cell->getPort(ID::SRC).as_bit();
auto dst = cell->getPort(ID::DST);
auto src = cell->getPort(TW::SRC).as_bit();
auto dst = cell->getPort(TW::DST);
if (!src.wire || !src.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));
for (const auto &c : dst.chunks())
@ -163,8 +163,8 @@ struct TimingInfo
IdString type = cell->getParam(ID::TYPE).decode_string();
if (type != ID($setup) && type != ID($setuphold))
continue;
auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID::DST).as_bit();
auto src = cell->getPort(TW::SRC);
auto dst = cell->getPort(TW::DST).as_bit();
for (const auto &c : src.chunks())
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", module, cell, log_signal(src));

126
kernel/twine.h
View file

@ -23,6 +23,9 @@ struct TwinePool;
using TwineRef = size_t;
// Tags TwineChildPool-local refs; never set on refs handed out by TwinePool.
constexpr TwineRef TWINE_LOCAL_BIT = TwineRef(1) << 63;
enum : short {
STATIC_TWINE_BEGIN = 0,
#define X(N) IDX_##N,
@ -195,6 +198,68 @@ struct TwinePool {
return ref;
}
size_t size() const { return backing.size(); }
TwineRef concat(std::span<const TwineRef> ids) {
if (ids.size() == 1)
return ids[0];
return add(Twine{std::vector<TwineRef>(ids.begin(), ids.end())});
}
TwineRef copy_from(const TwinePool& src, TwineRef ref) {
if (ref == Twine::Null || ref < STATIC_TWINE_END)
return ref;
const Twine& t = src[ref];
if (t.is_leaf())
return add(Twine{t.leaf()});
if (t.is_concat()) {
std::vector<TwineRef> children;
children.reserve(t.children().size());
for (TwineRef c : t.children())
children.push_back(copy_from(src, c));
return add(Twine{std::move(children)});
}
if (t.is_suffix())
return add(Twine{Twine::Suffix{copy_from(src, t.suffix().prefix), t.suffix().tail}});
return Twine::Null;
}
// linear deep scan; only for rare by-string lookups
TwineRef lookup(std::string_view sv) const;
// Erases every backing node not reachable from `roots`; refs to
// surviving nodes stay valid. Returns the number of erased nodes.
template<typename Pool>
size_t gc(const Pool& roots) {
std::unordered_set<TwineRef> live;
for (TwineRef ref : roots)
mark_live(ref, live);
size_t erased = 0;
for (auto it = backing.begin(); it != backing.end();) {
TwineRef ref = STATIC_TWINE_END + backing.get_index(it);
if (live.count(ref)) {
++it;
} else {
index.erase(ref);
it = backing.erase(it);
erased++;
}
}
return erased;
}
void mark_live(TwineRef ref, std::unordered_set<TwineRef>& live) const {
if (ref == Twine::Null || ref < STATIC_TWINE_END || !live.insert(ref).second)
return;
const Twine& t = (*this)[ref];
if (t.is_concat()) {
for (TwineRef c : t.children())
mark_live(c, live);
} else if (t.is_suffix()) {
mark_live(t.suffix().prefix, live);
}
}
void dump(std::ostream& os = std::cout) const {
os << "--- TwinePool Dump (" << backing.size() << " nodes) ---\n";
for (auto it = backing.begin(); it != backing.end(); ++it) {
@ -368,6 +433,67 @@ struct DeepTwineEq {
}
};
// Parallel-safe staging while the parent stays read-only; nodes may reference parent refs and earlier local refs
struct TwineChildPool {
const TwinePool* parent;
std::vector<Twine> local_;
std::vector<TwineRef> remap_;
TwineChildPool(const TwinePool* parent) : parent(parent) {}
static bool is_local(TwineRef ref) {
return ref != Twine::Null && (ref & TWINE_LOCAL_BIT);
}
const Twine& operator[] (TwineRef ref) const {
if (is_local(ref))
return local_[ref & ~TWINE_LOCAL_BIT];
return (*parent)[ref];
}
TwineRef add(Twine t) {
local_.push_back(std::move(t));
return (local_.size() - 1) | TWINE_LOCAL_BIT;
}
bool empty() const { return local_.empty(); }
// serial phase only; dest must be *parent; resolve() covers refs added since the previous commit
void commit_into(TwinePool& dest) {
remap_.clear();
remap_.reserve(local_.size());
for (Twine& t : local_) {
if (t.is_concat()) {
for (TwineRef& c : std::get<std::vector<TwineRef>>(t.data))
c = resolve(c);
} else if (t.is_suffix()) {
std::get<Twine::Suffix>(t.data).prefix = resolve(std::get<Twine::Suffix>(t.data).prefix);
}
remap_.push_back(dest.add(std::move(t)));
}
local_.clear();
}
TwineRef resolve(TwineRef ref) const {
if (!is_local(ref))
return ref;
return remap_[ref & ~TWINE_LOCAL_BIT];
}
};
inline TwineRef TwinePool::lookup(std::string_view sv) const {
DeepTwineEq eq{this};
for (TwineRef ref = 0; ref < globals_.size(); ref++)
if (eq(ref, sv))
return ref;
for (auto it = backing.begin(); it != backing.end(); ++it) {
TwineRef ref = STATIC_TWINE_END + backing.get_index(it);
if (eq(ref, sv))
return ref;
}
return Twine::Null;
}
struct TwineSearch {
TwinePool* pool;
std::unordered_set<TwineRef, DeepTwineHash, DeepTwineEq> index;

87
kernel/unstable/patch.cc
View file

@ -10,7 +10,7 @@ using namespace RTLIL;
template class CellAdderMixin<Patch>;
Cell* Patch::addCell(IdString name, IdString type) {
Cell* Patch::addCell(TwineRef name, IdString type) {
cells_.push_back(std::make_unique<Cell>(Cell::ConstructToken{}));
Cell* cell = cells_.back().get();
@ -20,7 +20,11 @@ Cell* Patch::addCell(IdString name, IdString type) {
return cell;
}
Wire* Patch::addWire(IdString name, int width) {
Cell* Patch::addCell(Twine &&name, IdString type) {
return addCell(twine_staging.add(std::move(name)), type);
}
Wire* Patch::addWire(TwineRef name, int width) {
wires_.push_back(std::make_unique<Wire>(Wire::ConstructToken{}));
Wire* wire = wires_.back().get();
@ -30,11 +34,15 @@ Wire* Patch::addWire(IdString name, int width) {
return wire;
}
Wire* Patch::addWire(Twine &&name, int width) {
return addWire(twine_staging.add(std::move(name)), width);
}
// TODO code golf
RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *other)
RTLIL::Wire *RTLIL::Patch::addWire(TwineRef name, const RTLIL::Wire *other)
{
RTLIL::Wire *wire = addWire(std::move(name));
RTLIL::Wire *wire = addWire(name);
wire->width = other->width;
wire->start_offset = other->start_offset;
wire->port_id = other->port_id;
@ -46,32 +54,44 @@ RTLIL::Wire *RTLIL::Patch::addWire(RTLIL::IdString name, const RTLIL::Wire *othe
return wire;
}
RTLIL::Wire *RTLIL::Patch::addWire(Twine &&name, const RTLIL::Wire *other)
{
return addWire(twine_staging.add(std::move(name)), other);
}
TwineRef Patch::new_name(const std::string *prefix) {
TwineRef pref;
if (auto it = staged_prefix_cache_.find(prefix); it != staged_prefix_cache_.end())
pref = it->second;
else
pref = staged_prefix_cache_[prefix] = twine_staging.add(Twine{*prefix});
return twine_staging.add(Twine{Twine::Suffix{pref, std::to_string(autoidx++)}});
}
Wire* Patch::commit_wire(std::unique_ptr<Wire> wire) {
Wire* raw = wire.release();
IdString name = staged_wire_names_.at(raw);
TwineRef id = twine_staging.resolve(staged_wire_names_.at(raw));
staged_wire_names_.erase(raw);
TwineRef id = mod->design->twines.intern(name.str());
mod->design->obj_set_name_id(raw, id);
mod->design->twines.release(id);
mod->wires_[raw->meta_->name_id] = raw;
raw->meta_->name = id;
mod->wires_[raw->meta_->name] = raw;
raw->module = mod;
return raw;
}
Cell* Patch::commit_cell(std::unique_ptr<Cell> cell) {
Cell* raw = cell.release();
IdString name = staged_cell_names_.at(raw);
TwineRef id = twine_staging.resolve(staged_cell_names_.at(raw));
staged_cell_names_.erase(raw);
TwineRef id = mod->design->twines.intern(name.str());
mod->design->obj_set_name_id(raw, id);
mod->design->twines.release(id);
raw->meta_->name = id;
raw->module = mod;
mod->cells_[raw->meta_->name_id] = raw;
mod->cells_[raw->meta_->name] = raw;
raw->initIndex();
return raw;
}
std::vector<Cell*> Patch::commit_staged() {
twine_staging.commit_into(mod->design->twines);
staged_prefix_cache_.clear();
std::vector<Cell*> committed;
committed.reserve(cells_.size());
for (auto& cell : cells_) {
@ -86,6 +106,12 @@ std::vector<Cell*> Patch::commit_staged() {
}
namespace {
std::string port_name(Cell* cell, TwineRef port) {
if (cell->module && cell->module->design)
return cell->module->design->twines.str(port);
return "<port#" + std::to_string(port) + ">";
}
void apply_src(Module* mod, Cell* root, const std::vector<Cell*>& extras,
const std::vector<Cell*>& targets, Cell* merge_src_into)
{
@ -107,25 +133,24 @@ namespace {
push(merge_src_into);
if (ids.empty())
return;
TwineRef merged = pool.concat(std::span<const TwineRef>{ids});
TwineRef merged = ids.size() == 1 ? ids[0] : pool.add(Twine{std::move(ids)});
if (ys_debug()) {
log_debug("twine: merge yields %s (pool size %zu)\n",
pool.format_ref(merged).c_str(), pool.size());
pool.str(merged).c_str(), pool.backing.size());
if (ys_debug(2))
pool.dump("twine pool state");
pool.dump();
}
for (Cell* c : targets)
c->set_src_id(merged);
if (merge_src_into)
merge_src_into->set_src_id(merged);
pool.release(merged);
}
// Verifies via newcelltypes that root_cell has exactly one output port
// and that it matches `expected_port`.
void assert_single_output(Cell* root_cell, IdString expected_port) {
void assert_single_output(Cell* root_cell, TwineRef expected_port) {
int count = 0;
IdString found;
TwineRef found = Twine::Null;
for (auto &[port, sig] : root_cell->connections()) {
if (root_cell->output(port)) {
found = port;
@ -138,11 +163,11 @@ namespace {
if (found != expected_port)
log_error("Patch: cell %s of type %s sole output port %s does not match patched port %s\n",
log_id(root_cell->name), log_id(root_cell->type),
log_id(found), log_id(expected_port));
port_name(root_cell, found).c_str(), port_name(root_cell, expected_port).c_str());
}
}
void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
void Patch::patch(Cell* root_cell, TwineRef old_port, SigSpec new_sig,
const std::vector<Cell*>& extras, Cell* merge_src_into)
{
assert_single_output(root_cell, old_port);
@ -150,11 +175,11 @@ void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
SigSpec old_sig = root_cell->getPort(old_port);
if (old_sig.size() != new_sig.size())
log_error("patch size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
log_id(root_cell->name), log_id(old_port),
log_id(root_cell->name), port_name(root_cell, old_port).c_str(),
old_sig.size(), log_signal(old_sig),
new_sig.size(), log_signal(new_sig));
log_debug("patching %s %s which is %s with %s\n",
log_id(root_cell->name), log_id(old_port),
log_id(root_cell->name), port_name(root_cell, old_port).c_str(),
log_signal(old_sig), log_signal(new_sig));
std::vector<Cell*> committed = commit_staged();
@ -174,22 +199,22 @@ void Patch::patch(Cell* root_cell, IdString old_port, SigSpec new_sig,
}
void Patch::patch_ports(Cell* root_cell,
const std::vector<std::pair<IdString, SigSpec>>& port_replacements,
const std::vector<std::pair<TwineRef, SigSpec>>& port_replacements,
const std::vector<Cell*>& extras, Cell* merge_src_into)
{
// Verify each listed port is an output of root_cell and that the
// replacements cover every output port of root_cell.
pool<IdString> listed;
pool<TwineRef> listed;
std::vector<SigSpec> old_sigs;
old_sigs.reserve(port_replacements.size());
for (auto &[port, new_sig] : port_replacements) {
if (!root_cell->output(port))
log_error("patch_ports: cell %s of type %s port %s is not an output\n",
log_id(root_cell->name), log_id(root_cell->type), log_id(port));
log_id(root_cell->name), log_id(root_cell->type), port_name(root_cell, port).c_str());
SigSpec old_sig = root_cell->getPort(port);
if (old_sig.size() != new_sig.size())
log_error("patch_ports size mismatch on cell %s port %s: old %d (%s) vs new %d (%s)\n",
log_id(root_cell->name), log_id(port),
log_id(root_cell->name), port_name(root_cell, port).c_str(),
old_sig.size(), log_signal(old_sig),
new_sig.size(), log_signal(new_sig));
listed.insert(port);
@ -198,7 +223,7 @@ void Patch::patch_ports(Cell* root_cell,
for (auto &[port, sig] : root_cell->connections())
if (root_cell->output(port) && !listed.count(port))
log_error("patch_ports: cell %s of type %s has output port %s not in port_replacements\n",
log_id(root_cell->name), log_id(root_cell->type), log_id(port));
log_id(root_cell->name), log_id(root_cell->type), port_name(root_cell, port).c_str());
std::vector<Cell*> committed = commit_staged();
apply_src(mod, root_cell, extras, committed, merge_src_into);
@ -207,7 +232,7 @@ void Patch::patch_ports(Cell* root_cell,
// shell before we wire old_sigs to new_sigs. Doing this first ensures
// the old port signals are not briefly double-driven by root_cell and
// the new connection.
std::vector<IdString> all_ports;
std::vector<TwineRef> all_ports;
all_ports.reserve(root_cell->connections().size());
for (auto &[port, sig] : root_cell->connections())
all_ports.push_back(port);
@ -226,6 +251,8 @@ void Patch::patch_ports(Cell* root_cell,
}
void Patch::commit_inheriting_src(Cell* src_source) {
twine_staging.commit_into(mod->design->twines);
staged_prefix_cache_.clear();
for (auto& cell : cells_) {
cell->fixup_parameters();
Cell *committed = commit_cell(std::move(cell));

31
kernel/unstable/patch.h
View file

@ -26,8 +26,10 @@ public:
SigMap* map;
vector<std::unique_ptr<Wire>> wires_ = {};
vector<std::unique_ptr<Cell>> cells_ = {};
dict<RTLIL::Cell*, Twine> staged_cell_names_;
dict<RTLIL::Wire*, Twine> staged_wire_names_;
TwineChildPool twine_staging;
dict<RTLIL::Cell*, TwineRef> staged_cell_names_;
dict<RTLIL::Wire*, TwineRef> staged_wire_names_;
dict<const std::string*, TwineRef> staged_prefix_cache_;
void connect(const RTLIL::SigSig &conn);
void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs);
@ -64,16 +66,29 @@ public:
// tracking carries through transparently). Pass nullptr for src_source
// if the staged helpers have no natural ancestor.
void commit_inheriting_src(Cell* src_source);
RTLIL::Wire *addWire(RTLIL::IdString name, int width = 1);
RTLIL::Wire *addWire(RTLIL::IdString name, const RTLIL::Wire *other);
RTLIL::Cell *addCell(RTLIL::IdString name, RTLIL::IdString type);
RTLIL::Cell *addCell(RTLIL::IdString name, const RTLIL::Cell *other);
// Primary overloads: name is a design ref or a twine_staging-local ref.
RTLIL::Wire *addWire(TwineRef name, int width = 1);
RTLIL::Wire *addWire(TwineRef name, const RTLIL::Wire *other);
// Convenience: stages name into twine_staging, then dispatches.
RTLIL::Wire *addWire(Twine &&name, int width = 1);
RTLIL::Wire *addWire(Twine &&name, const RTLIL::Wire *other);
RTLIL::Cell* addDffsr(RTLIL::IdString name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::Cell *addCell(TwineRef name, RTLIL::IdString type);
RTLIL::Cell *addCell(TwineRef name, const RTLIL::Cell *other);
RTLIL::Cell *addCell(Twine &&name, RTLIL::IdString type);
RTLIL::Cell *addCell(Twine &&name, const RTLIL::Cell *other);
// NEW_ID analog for twine names; see NEW_TWINE in yosys_common.h.
// Returned refs are twine_staging-local and die at the next commit.
TwineRef new_name(const std::string *prefix);
RTLIL::Cell* addDffsr(TwineRef name, const RTLIL::SigSpec &sig_clk, const RTLIL::SigSpec &sig_set, const RTLIL::SigSpec &sig_clr,
RTLIL::SigSpec sig_d, const RTLIL::SigSpec &sig_q, bool clk_polarity, bool set_polarity, bool clr_polarity, const std::string &src);
Patch(Module* mod, SigMap* map = nullptr) : mod(mod), map(map) {}
Patch(Module* mod, SigMap* map = nullptr) :
mod(mod), map(map),
twine_staging(mod && mod->design ? &mod->design->twines : nullptr) {}
};
YOSYS_NAMESPACE_END

4
kernel/wallace_tree.h
View file

@ -21,8 +21,8 @@ YOSYS_NAMESPACE_BEGIN
inline std::pair<SigSpec, SigSpec> emit_fa(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
{
SigSpec sum = module->addWire(NEW_ID, width);
SigSpec cout = module->addWire(NEW_ID, width);
SigSpec sum = module->addWire(NEW_TWINE, width);
SigSpec cout = module->addWire(NEW_TWINE, width);
module->addFa(NEW_ID, a, b, c, cout, sum);

10
kernel/yosys_common.h
View file

@ -304,6 +304,16 @@ RTLIL::IdString new_id_suffix(std::string_view file, int line, std::string_view
}(__FUNCTION__))
#define NEW_ID_SUFFIX(suffix) \
YOSYS_NAMESPACE_PREFIX new_id_suffix(__FILE__, __LINE__, __FUNCTION__, suffix)
#define NEW_TWINE \
YOSYS_NAMESPACE_PREFIX Twine{*[](std::string_view func) -> const std::string * { \
static std::unique_ptr<const std::string> prefix(YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func)); \
return prefix.get(); \
}(__FUNCTION__) + std::to_string(YOSYS_NAMESPACE_PREFIX autoidx++)}
#define NEW_TWINE_SUFFIX(suffix) \
YOSYS_NAMESPACE_PREFIX Twine{*[](std::string_view func) -> const std::string * { \
static std::unique_ptr<const std::string> prefix(YOSYS_NAMESPACE_PREFIX create_id_prefix(__FILE__, __LINE__, func)); \
return prefix.get(); \
}(__FUNCTION__) + std::string(suffix) + "$" + std::to_string(YOSYS_NAMESPACE_PREFIX autoidx++)}
namespace ID = RTLIL::ID;