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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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126
frontends/liberty/liberty.cc
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@ -185,12 +185,12 @@ static RTLIL::SigSpec create_tristate(RTLIL::Module *module, RTLIL::SigSpec func
{
RTLIL::SigSpec three_state = parse_func_expr(module, three_state_expr);
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($tribuf));
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($tribuf));
cell->setParam(ID::WIDTH, GetSize(func));
cell->setPort(ID::A, func);
cell->setPort(ID::EN, module->NotGate(NEW_ID, three_state));
cell->setPort(ID::Y, module->addWire(NEW_ID));
return cell->getPort(ID::Y);
cell->setPort(TW::A, func);
cell->setPort(TW::EN, module->NotGate(NEW_ID, three_state));
cell->setPort(TW::Y, module->addWire(NEW_TWINE));
return cell->getPort(TW::Y);
}
static void create_latch_ff_wires(RTLIL::Module *module, const LibertyAst *node)
@ -243,18 +243,18 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) {
clk_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clk_sig) {
clk_sig = it.second->getPort(TW::A);
clk_polarity = !clk_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
clear_sig = it.second->getPort(TW::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
preset_sig = it.second->getPort(TW::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
@ -264,14 +264,14 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
for (auto& [out_sig, cp_var, neg] : {tuple{iq_sig, clear_preset_var1, false}, {iqn_sig, clear_preset_var2, true}}) {
SigSpec q_sig = out_sig;
if (neg) {
q_sig = module->addWire(NEW_ID, out_sig.as_wire());
q_sig = module->addWire(NEW_TWINE, out_sig.as_wire());
module->addNotGate(NEW_ID, q_sig, out_sig);
}
RTLIL::Cell* cell = module->addCell(NEW_ID, "");
cell->setPort(ID::D, data_sig);
cell->setPort(ID::Q, q_sig);
cell->setPort(ID::C, clk_sig);
RTLIL::Cell* cell = module->addCell(NEW_TWINE, "");
cell->setPort(TW::D, data_sig);
cell->setPort(TW::Q, q_sig);
cell->setPort(TW::C, clk_sig);
if (clear_sig.size() == 0 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N');
@ -279,12 +279,12 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
if (clear_sig.size() == 1 && preset_sig.size() == 0) {
cell->type = stringf("$_DFF_%c%c0_", clk_polarity ? 'P' : 'N', clear_polarity ? 'P' : 'N');
cell->setPort(ID::R, clear_sig);
cell->setPort(TW::R, clear_sig);
}
if (clear_sig.size() == 0 && preset_sig.size() == 1) {
cell->type = stringf("$_DFF_%c%c1_", clk_polarity ? 'P' : 'N', preset_polarity ? 'P' : 'N');
cell->setPort(ID::R, preset_sig);
cell->setPort(TW::R, preset_sig);
}
if (clear_sig.size() == 1 && preset_sig.size() == 1) {
@ -313,8 +313,8 @@ static void create_ff(RTLIL::Module *module, const LibertyAst *node)
log_debug("cell %s variable %d undef c&p behavior\n", name, (int)neg + 1);
}
cell->setPort(ID::S, s_sig);
cell->setPort(ID::R, r_sig);
cell->setPort(TW::S, s_sig);
cell->setPort(TW::R, r_sig);
}
log_assert(!cell->type.empty());
@ -352,27 +352,27 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
rerun_invert_rollback = false;
for (auto &it : module->cells_) {
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == enable_sig) {
enable_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == enable_sig) {
enable_sig = it.second->getPort(TW::A);
enable_polarity = !enable_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clear_sig) {
clear_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == clear_sig) {
clear_sig = it.second->getPort(TW::A);
clear_polarity = !clear_polarity;
rerun_invert_rollback = true;
}
if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == preset_sig) {
preset_sig = it.second->getPort(ID::A);
if (it.second->type == ID($_NOT_) && it.second->getPort(TW::Y) == preset_sig) {
preset_sig = it.second->getPort(TW::A);
preset_polarity = !preset_polarity;
rerun_invert_rollback = true;
}
}
}
RTLIL::Cell *cell = module->addCell(NEW_ID, ID($_NOT_));
cell->setPort(ID::A, iq_sig);
cell->setPort(ID::Y, iqn_sig);
RTLIL::Cell *cell = module->addCell(NEW_TWINE, ID($_NOT_));
cell->setPort(TW::A, iq_sig);
cell->setPort(TW::Y, iqn_sig);
if (clear_sig.size() == 1)
{
@ -381,25 +381,25 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (clear_polarity == true || clear_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
inv->setPort(ID::A, clear_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
inv->setPort(TW::A, clear_sig);
inv->setPort(TW::Y, module->addWire(NEW_TWINE));
if (clear_polarity == true)
clear_negative = inv->getPort(ID::Y);
clear_negative = inv->getPort(TW::Y);
if (clear_polarity != enable_polarity)
clear_enable = inv->getPort(ID::Y);
clear_enable = inv->getPort(TW::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_AND_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, clear_negative);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_AND_));
data_gate->setPort(TW::A, data_sig);
data_gate->setPort(TW::B, clear_negative);
data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, clear_enable);
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(TW::A, enable_sig);
enable_gate->setPort(TW::B, clear_enable);
enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
}
if (preset_sig.size() == 1)
@ -409,31 +409,31 @@ static bool create_latch(RTLIL::Module *module, const LibertyAst *node, bool fla
if (preset_polarity == false || preset_polarity != enable_polarity)
{
RTLIL::Cell *inv = module->addCell(NEW_ID, ID($_NOT_));
inv->setPort(ID::A, preset_sig);
inv->setPort(ID::Y, module->addWire(NEW_ID));
RTLIL::Cell *inv = module->addCell(NEW_TWINE, ID($_NOT_));
inv->setPort(TW::A, preset_sig);
inv->setPort(TW::Y, module->addWire(NEW_TWINE));
if (preset_polarity == false)
preset_positive = inv->getPort(ID::Y);
preset_positive = inv->getPort(TW::Y);
if (preset_polarity != enable_polarity)
preset_enable = inv->getPort(ID::Y);
preset_enable = inv->getPort(TW::Y);
}
RTLIL::Cell *data_gate = module->addCell(NEW_ID, ID($_OR_));
data_gate->setPort(ID::A, data_sig);
data_gate->setPort(ID::B, preset_positive);
data_gate->setPort(ID::Y, data_sig = module->addWire(NEW_ID));
RTLIL::Cell *data_gate = module->addCell(NEW_TWINE, ID($_OR_));
data_gate->setPort(TW::A, data_sig);
data_gate->setPort(TW::B, preset_positive);
data_gate->setPort(TW::Y, data_sig = module->addWire(NEW_TWINE));
RTLIL::Cell *enable_gate = module->addCell(NEW_ID, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(ID::A, enable_sig);
enable_gate->setPort(ID::B, preset_enable);
enable_gate->setPort(ID::Y, enable_sig = module->addWire(NEW_ID));
RTLIL::Cell *enable_gate = module->addCell(NEW_TWINE, enable_polarity ? ID($_OR_) : ID($_AND_));
enable_gate->setPort(TW::A, enable_sig);
enable_gate->setPort(TW::B, preset_enable);
enable_gate->setPort(TW::Y, enable_sig = module->addWire(NEW_TWINE));
}
cell = module->addCell(NEW_ID, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->setPort(ID::D, data_sig);
cell->setPort(ID::Q, iq_sig);
cell->setPort(ID::E, enable_sig);
cell = module->addCell(NEW_TWINE, stringf("$_DLATCH_%c_", enable_polarity ? 'P' : 'N'));
cell->setPort(TW::D, data_sig);
cell->setPort(TW::Q, iq_sig);
cell->setPort(TW::E, enable_sig);
return true;
}
@ -793,7 +793,7 @@ struct LibertyFrontend : public Frontend {
if (wi->port_input) {
for (auto wo : module->wires())
if (wo->port_output) {
RTLIL::Cell *spec = module->addCell(NEW_ID, ID($specify2));
RTLIL::Cell *spec = module->addCell(NEW_TWINE, ID($specify2));
spec->setParam(ID::SRC_WIDTH, wi->width);
spec->setParam(ID::DST_WIDTH, wo->width);
spec->setParam(ID::T_FALL_MAX, 1000);
@ -805,9 +805,9 @@ struct LibertyFrontend : public Frontend {
spec->setParam(ID::SRC_DST_POL, false);
spec->setParam(ID::SRC_DST_PEN, false);
spec->setParam(ID::FULL, true);
spec->setPort(ID::EN, Const(1, 1));
spec->setPort(ID::SRC, wi);
spec->setPort(ID::DST, wo);
spec->setPort(TW::EN, Const(1, 1));
spec->setPort(TW::SRC, wi);
spec->setPort(TW::DST, wo);
}
}
}