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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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12
frontends/aiger/aigerparse.cc
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@ -130,7 +130,7 @@ struct ConstEvalAig
sig2deps[output].insert(output);
RTLIL::Cell *cell = sig2driver.at(output);
RTLIL::SigBit sig_a = cell->getPort(ID::A);
RTLIL::SigBit sig_a = cell->getPort(TW::A);
sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
@ -139,7 +139,7 @@ struct ConstEvalAig
compute_deps(sig_a, inputs);
if (cell->type == ID($_AND_)) {
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
// that may occur does so here, and
// not mid insertion (below)
@ -155,11 +155,11 @@ struct ConstEvalAig
bool eval(RTLIL::Cell *cell)
{
RTLIL::SigBit sig_y = cell->getPort(ID::Y);
RTLIL::SigBit sig_y = cell->getPort(TW::Y);
if (values_map.count(sig_y))
return true;
RTLIL::SigBit sig_a = cell->getPort(ID::A);
RTLIL::SigBit sig_a = cell->getPort(TW::A);
if (!eval(sig_a))
return false;
@ -175,7 +175,7 @@ struct ConstEvalAig
}
{
RTLIL::SigBit sig_b = cell->getPort(ID::B);
RTLIL::SigBit sig_b = cell->getPort(TW::B);
if (!eval(sig_b))
return false;
if (sig_b == State::S0) {
@ -978,7 +978,7 @@ void AigerReader::post_process()
for (auto cell : module->cells().to_vector()) {
if (cell->type != ID($lut)) continue;
auto y_port = cell->getPort(ID::Y).as_bit();
auto y_port = cell->getPort(TW::Y).as_bit();
if (y_port.wire->width == 1)
module->rename(cell, stringf("$lut%s", y_port.wire->name));
else