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This commit is contained in:
Emil J. Tywoniak 2026-06-10 19:22:53 +02:00
parent 015ab4e45b
commit f592f2f3af
203 changed files with 4575 additions and 4481 deletions
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44
backends/aiger/aiger.cc
View file

@ -223,8 +223,8 @@ struct AigerWriter
{
if (cell->type == ID($_NOT_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
unused_bits.erase(A);
undriven_bits.erase(Y);
not_map[Y] = A;
@ -233,14 +233,14 @@ struct AigerWriter
if (cell->type.in(ID($_FF_), ID($_DFF_N_), ID($_DFF_P_)))
{
SigBit D = sigmap(cell->getPort(ID::D).as_bit());
SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
ff_map[Q] = D;
if (cell->type != ID($_FF_)) {
auto sig_clk = sigmap(cell->getPort(ID::C).as_bit());
auto sig_clk = sigmap(cell->getPort(TW::C).as_bit());
ywmap_clocks[sig_clk] |= cell->type == ID($_DFF_N_) ? 2 : 1;
}
continue;
@ -248,8 +248,8 @@ struct AigerWriter
if (cell->type == ID($anyinit))
{
auto sig_d = sigmap(cell->getPort(ID::D));
auto sig_q = sigmap(cell->getPort(ID::Q));
auto sig_d = sigmap(cell->getPort(TW::D));
auto sig_q = sigmap(cell->getPort(TW::Q));
for (int i = 0; i < sig_d.size(); i++) {
undriven_bits.erase(sig_q[i]);
ff_map[sig_q[i]] = sig_d[i];
@ -259,9 +259,9 @@ struct AigerWriter
if (cell->type == ID($_AND_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit B = sigmap(cell->getPort(ID::B).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
unused_bits.erase(A);
unused_bits.erase(B);
undriven_bits.erase(Y);
@ -271,7 +271,7 @@ struct AigerWriter
if (cell->type == ID($initstate))
{
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
undriven_bits.erase(Y);
initstate_bits.insert(Y);
continue;
@ -279,8 +279,8 @@ struct AigerWriter
if (cell->type == ID($assert))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
asserts.push_back(make_pair(A, EN));
@ -290,8 +290,8 @@ struct AigerWriter
if (cell->type == ID($assume))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
assumes.push_back(make_pair(A, EN));
@ -301,8 +301,8 @@ struct AigerWriter
if (cell->type == ID($live))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
liveness.push_back(make_pair(A, EN));
@ -311,8 +311,8 @@ struct AigerWriter
if (cell->type == ID($fair))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit EN = sigmap(cell->getPort(ID::EN).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit EN = sigmap(cell->getPort(TW::EN).as_bit());
unused_bits.erase(A);
unused_bits.erase(EN);
fairness.push_back(make_pair(A, EN));
@ -321,7 +321,7 @@ struct AigerWriter
if (cell->type == ID($anyconst))
{
for (auto bit : sigmap(cell->getPort(ID::Y))) {
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
ff_map[bit] = bit;
}
@ -330,7 +330,7 @@ struct AigerWriter
if (cell->type == ID($anyseq))
{
for (auto bit : sigmap(cell->getPort(ID::Y))) {
for (auto bit : sigmap(cell->getPort(TW::Y))) {
undriven_bits.erase(bit);
input_bits.insert(bit);
}
@ -780,7 +780,7 @@ struct AigerWriter
SigSpec sig = sigmap(sig_qy);
if (cell->get_bool_attribute(ID(clk2fflogic)))
sig_qy = cell->getPort(ID::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output
sig_qy = cell->getPort(TW::D); // For a clk2fflogic $_FF_ the named signal is the D input not the Q output
for (int i = 0; i < GetSize(sig_qy); i++) {
if (sig_qy[i].wire == nullptr || sig[i].wire == nullptr)

24
backends/aiger/xaiger.cc
View file

@ -193,8 +193,8 @@ struct XAigerWriter
if (!cell->has_keep_attr()) {
if (cell->type == ID($_NOT_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
unused_bits.erase(A);
undriven_bits.erase(Y);
not_map[Y] = A;
@ -203,9 +203,9 @@ struct XAigerWriter
if (cell->type == ID($_AND_))
{
SigBit A = sigmap(cell->getPort(ID::A).as_bit());
SigBit B = sigmap(cell->getPort(ID::B).as_bit());
SigBit Y = sigmap(cell->getPort(ID::Y).as_bit());
SigBit A = sigmap(cell->getPort(TW::A).as_bit());
SigBit B = sigmap(cell->getPort(TW::B).as_bit());
SigBit Y = sigmap(cell->getPort(TW::Y).as_bit());
unused_bits.erase(A);
unused_bits.erase(B);
undriven_bits.erase(Y);
@ -215,8 +215,8 @@ struct XAigerWriter
if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
{
SigBit D = sigmap(cell->getPort(ID::D).as_bit());
SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());
SigBit D = sigmap(cell->getPort(TW::D).as_bit());
SigBit Q = sigmap(cell->getPort(TW::Q).as_bit());
unused_bits.erase(D);
undriven_bits.erase(Q);
alias_map[Q] = D;
@ -413,7 +413,7 @@ struct XAigerWriter
}
for (auto cell : ff_list) {
const SigBit &q = sigmap(cell->getPort(ID::Q));
const SigBit &q = sigmap(cell->getPort(TW::Q));
aig_m++, aig_i++;
log_assert(!aig_map.count(q));
aig_map[q] = 2*aig_m;
@ -461,7 +461,7 @@ struct XAigerWriter
}
for (auto cell : ff_list) {
const SigBit &d = sigmap(cell->getPort(ID::D));
const SigBit &d = sigmap(cell->getPort(TW::D));
aig_o++;
aig_outputs.push_back(aig_map.at(d));
}
@ -605,10 +605,10 @@ struct XAigerWriter
dict<SigSpec, int> clk_to_mergeability;
for (const auto cell : ff_list) {
const SigBit &d = sigmap(cell->getPort(ID::D));
const SigBit &q = sigmap(cell->getPort(ID::Q));
const SigBit &d = sigmap(cell->getPort(TW::D));
const SigBit &q = sigmap(cell->getPort(TW::Q));
SigSpec clk_and_pol{sigmap(cell->getPort(ID::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
SigSpec clk_and_pol{sigmap(cell->getPort(TW::C)), cell->type[6] == 'P' ? State::S1 : State::S0};
auto r = clk_to_mergeability.insert(std::make_pair(clk_and_pol, clk_to_mergeability.size()+1));
int mergeability = r.first->second;
log_assert(mergeability > 0);

46
backends/aiger2/aiger.cc
View file

@ -283,9 +283,9 @@ struct Index {
if (cell->type.in(REDUCE_OPS, LOGIC_OPS, CMP_OPS) && obit != 0) {
return CFALSE;
} else if (cell->type.in(CMP_OPS)) {
SigSpec aport = cell->getPort(ID::A);
SigSpec aport = cell->getPort(TW::A);
bool asigned = cell->getParam(ID::A_SIGNED).as_bool();
SigSpec bport = cell->getPort(ID::B);
SigSpec bport = cell->getPort(TW::B);
bool bsigned = cell->getParam(ID::B_SIGNED).as_bool();
int width = std::max(aport.size(), bport.size()) + 1;
@ -318,7 +318,7 @@ struct Index {
log_abort();
}
} else if (cell->type.in(REDUCE_OPS, ID($logic_not))) {
SigSpec inport = cell->getPort(ID::A);
SigSpec inport = cell->getPort(TW::A);
std::vector<Lit> lits;
for (int i = 0; i < inport.size(); i++) {
@ -339,8 +339,8 @@ struct Index {
else
return NOT(acc);
} else if (cell->type.in(ID($logic_and), ID($logic_or))) {
SigSpec aport = cell->getPort(ID::A);
SigSpec bport = cell->getPort(ID::B);
SigSpec aport = cell->getPort(TW::A);
SigSpec bport = cell->getPort(TW::B);
log_assert(aport.size() > 0 && bport.size() > 0); // TODO
@ -363,7 +363,7 @@ struct Index {
else
log_abort();
} else if (cell->type.in(BITWISE_OPS, GATE_OPS, ID($pos))) {
SigSpec aport = cell->getPort(ID::A);
SigSpec aport = cell->getPort(TW::A);
Lit a;
if (obit < aport.size()) {
a = visit(cursor, aport[obit]);
@ -379,7 +379,7 @@ struct Index {
} else if (cell->type.in(ID($not), ID($_NOT_))) {
return NOT(a);
} else {
SigSpec bport = cell->getPort(ID::B);
SigSpec bport = cell->getPort(TW::B);
Lit b;
if (obit < bport.size()) {
b = visit(cursor, bport[obit]);
@ -407,16 +407,16 @@ struct Index {
} else if (cell->type.in(ID($_ORNOT_))) {
return OR(a, NOT(b));
} else if (cell->type.in(ID($mux), ID($_MUX_))) {
Lit s = visit(cursor, cell->getPort(ID::S));
Lit s = visit(cursor, cell->getPort(TW::S));
return MUX(a, b, s);
} else if (cell->type.in(ID($bwmux))) {
Lit s = visit(cursor, cell->getPort(ID::S)[obit]);
Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
return MUX(a, b, s);
} else if (cell->type.in(ID($_NMUX_))) {
Lit s = visit(cursor, cell->getPort(ID::S)[obit]);
Lit s = visit(cursor, cell->getPort(TW::S)[obit]);
return NOT(MUX(a, b, s));
} else if (cell->type.in(ID($fa))) {
Lit c = visit(cursor, cell->getPort(ID::C)[obit]);
Lit c = visit(cursor, cell->getPort(TW::C)[obit]);
Lit ab = XOR(a, b);
if (oport == ID::Y) {
return XOR(ab, c);
@ -428,9 +428,9 @@ struct Index {
} else if (cell->type.in(ID($_AOI3_), ID($_OAI3_), ID($_AOI4_), ID($_OAI4_))) {
Lit c, d;
c = visit(cursor, cell->getPort(ID::C)[obit]);
c = visit(cursor, cell->getPort(TW::C)[obit]);
if (/* 4 input types */ cell->type.in(ID($_AOI4_), ID($_OAI4_)))
d = visit(cursor, cell->getPort(ID::D)[obit]);
d = visit(cursor, cell->getPort(TW::D)[obit]);
else
d = cell->type == ID($_AOI3_) ? CTRUE : CFALSE;
@ -448,9 +448,9 @@ struct Index {
}
}
} else if (cell->type == ID($pmux)) {
SigSpec aport = cell->getPort(ID::A);
SigSpec bport = cell->getPort(ID::B);
SigSpec sport = cell->getPort(ID::S);
SigSpec aport = cell->getPort(TW::A);
SigSpec bport = cell->getPort(TW::B);
SigSpec sport = cell->getPort(TW::S);
int width = aport.size();
Lit a = visit(cursor, aport[obit]);
@ -469,8 +469,8 @@ struct Index {
return OR(reduce_sels_and_a, reduce_bar);
} else if (cell->type == ID($bmux)) {
SigSpec aport = cell->getPort(ID::A);
SigSpec sport = cell->getPort(ID::S);
SigSpec aport = cell->getPort(TW::A);
SigSpec sport = cell->getPort(TW::S);
int width = cell->getParam(ID::WIDTH).as_int();
std::vector<Lit> data;
@ -632,7 +632,7 @@ struct Index {
} else {
Module *def = cursor.enter(*this, driver);
{
IdString portname = bit.wire->driverPort();
TwineRef portname = bit.wire->driverPort();
Wire *w = def->wire(portname);
if (!w)
log_error("Output port %s on instance %s of %s doesn't exist\n",
@ -652,7 +652,7 @@ struct Index {
// step into the upper module
Cell *instance = cursor.exit(*this);
{
IdString portname = bit.wire->name;
TwineRef portname = bit.wire->name;
if (!instance->hasPort(portname))
log_error("Input port %s on instance %s of %s unconnected\n",
portname.unescape(), instance, instance->type);
@ -1134,7 +1134,7 @@ struct XAigerWriter : AigerWriter {
for (auto [cursor, box, def] : nonopaque_boxes) {
// use `def->name` not `box->type` as we want the derived type
Cell *holes_wb = holes_module->addCell(NEW_ID, def->name);
Cell *holes_wb = holes_module->addCell(NEW_TWINE, def->name);
int holes_pi_idx = 0;
if (map_file.is_open()) {
@ -1175,7 +1175,7 @@ struct XAigerWriter : AigerWriter {
SigSpec in_conn;
for (int i = 0; i < port->width; i++) {
while (holes_pi_idx >= (int) holes_pis.size()) {
Wire *w = holes_module->addWire(NEW_ID, 1);
Wire *w = holes_module->addWire(NEW_TWINE, 1);
w->port_input = true;
holes_module->ports.push_back(w->name);
holes_pis.push_back(w);
@ -1204,7 +1204,7 @@ struct XAigerWriter : AigerWriter {
boxes_ci_num += port->width;
// holes
Wire *w = holes_module->addWire(NEW_ID, port->width);
Wire *w = holes_module->addWire(NEW_TWINE, port->width);
w->port_output = true;
holes_module->ports.push_back(w->name);
holes_wb->setPort(port_id, w);

66
backends/blif/blif.cc
View file

@ -244,136 +244,136 @@ struct BlifDumper
if (!config->icells_mode && cell->type == ID($_NOT_)) {
f << stringf(".names %s %s\n0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AND_)) {
f << stringf(".names %s %s %s\n11 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OR_)) {
f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_XOR_)) {
f << stringf(".names %s %s %s\n10 1\n01 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NAND_)) {
f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NOR_)) {
f << stringf(".names %s %s %s\n00 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_XNOR_)) {
f << stringf(".names %s %s %s\n11 1\n00 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_ANDNOT_)) {
f << stringf(".names %s %s %s\n10 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_ORNOT_)) {
f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AOI3_)) {
f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OAI3_)) {
f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(), str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_AOI4_)) {
f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_OAI4_)) {
f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::C)).c_str(), str(cell->getPort(TW::D)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_MUX_)) {
f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_NMUX_)) {
f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str());
str(cell->getPort(TW::A)).c_str(), str(cell->getPort(TW::B)).c_str(),
str(cell->getPort(TW::S)).c_str(), str(cell->getPort(TW::Y)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_FF_)) {
f << stringf(".latch %s %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DFF_N_)) {
f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DFF_P_)) {
f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::C)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) {
f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) {
f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(ID::D)), str(cell->getPort(ID::Q)),
str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(TW::D)), str(cell->getPort(TW::Q)),
str(cell->getPort(TW::E)).c_str(), str_init(cell->getPort(TW::Q)).c_str());
goto internal_cell;
}
if (!config->icells_mode && cell->type == ID($lut)) {
f << stringf(".names");
auto &inputs = cell->getPort(ID::A);
auto &inputs = cell->getPort(TW::A);
auto width = cell->parameters.at(ID::WIDTH).as_int();
log_assert(inputs.size() == width);
for (int i = width-1; i >= 0; i--)
f << stringf(" %s", str(inputs.extract(i, 1)));
auto &output = cell->getPort(ID::Y);
auto &output = cell->getPort(TW::Y);
log_assert(output.size() == 1);
f << stringf(" %s", str(output));
f << stringf("\n");
@ -390,7 +390,7 @@ struct BlifDumper
if (!config->icells_mode && cell->type == ID($sop)) {
f << stringf(".names");
auto &inputs = cell->getPort(ID::A);
auto &inputs = cell->getPort(TW::A);
auto width = cell->parameters.at(ID::WIDTH).as_int();
auto depth = cell->parameters.at(ID::DEPTH).as_int();
vector<State> table = cell->parameters.at(ID::TABLE).to_bits();
@ -399,7 +399,7 @@ struct BlifDumper
log_assert(inputs.size() == width);
for (int i = 0; i < width; i++)
f << stringf(" %s", str(inputs.extract(i, 1)));
auto &output = cell->getPort(ID::Y);
auto &output = cell->getPort(TW::Y);
log_assert(output.size() == 1);
f << stringf(" %s", str(output));
f << stringf("\n");

118
backends/btor/btor.cc
View file

@ -271,8 +271,8 @@ struct BtorWorker
if (cell->type.in(ID($xnor), ID($_XNOR_))) btor_op = "xnor";
log_assert(!btor_op.empty());
int width_ay = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
int width = std::max(width_ay, GetSize(cell->getPort(ID::B)));
int width_ay = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
int width = std::max(width_ay, GetSize(cell->getPort(TW::B)));
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
@ -292,17 +292,17 @@ struct BtorWorker
int nid_a;
if (cell->type.in(ID($shl), ID($shr), ID($shift), ID($shiftx)) && a_signed && width_ay < width) {
// sign-extend A up to the width of Y
int nid_a_padded = get_sig_nid(cell->getPort(ID::A), width_ay, a_signed);
int nid_a_padded = get_sig_nid(cell->getPort(TW::A), width_ay, a_signed);
// zero-extend the rest
int zeroes = get_sig_nid(Const(0, width-width_ay));
nid_a = next_nid++;
btorf("%d concat %d %d %d\n", nid_a, sid, zeroes, nid_a_padded);
} else {
nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed);
}
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
if (btor_op == "shift")
{
@ -329,7 +329,7 @@ struct BtorWorker
btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) < width) {
int sid = get_bv_sid(GetSize(sig));
@ -358,18 +358,18 @@ struct BtorWorker
}
log_assert(!btor_op.empty());
int width = GetSize(cell->getPort(ID::Y));
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
int width = GetSize(cell->getPort(TW::Y));
width = std::max(width, GetSize(cell->getPort(TW::A)));
width = std::max(width, GetSize(cell->getPort(TW::B)));
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
int sid = get_bv_sid(width);
int nid = next_nid++;
btorf("%d %c%s %d %d %d%s\n", nid, a_signed || b_signed ? 's' : 'u', btor_op, sid, nid_a, nid_b, getinfo(cell));
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) < width) {
int sid = get_bv_sid(GetSize(sig));
@ -385,8 +385,8 @@ struct BtorWorker
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_b = get_sig_nid(cell->getPort(TW::B));
int nid1 = next_nid++;
int nid2 = next_nid++;
@ -401,7 +401,7 @@ struct BtorWorker
btorf("%d or %d %d %d%s\n", nid2, sid, nid_a, nid1, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
add_nid_sig(nid2, sig);
goto okay;
}
@ -409,9 +409,9 @@ struct BtorWorker
if (cell->type.in(ID($_OAI3_), ID($_AOI3_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_b = get_sig_nid(cell->getPort(TW::B));
int nid_c = get_sig_nid(cell->getPort(TW::C));
int nid1 = next_nid++;
int nid2 = next_nid++;
@ -429,7 +429,7 @@ struct BtorWorker
btorf("%d not %d %d%s\n", nid3, sid, nid2, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
add_nid_sig(nid3, sig);
goto okay;
}
@ -437,10 +437,10 @@ struct BtorWorker
if (cell->type.in(ID($_OAI4_), ID($_AOI4_)))
{
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = get_sig_nid(cell->getPort(ID::B));
int nid_c = get_sig_nid(cell->getPort(ID::C));
int nid_d = get_sig_nid(cell->getPort(ID::D));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_b = get_sig_nid(cell->getPort(TW::B));
int nid_c = get_sig_nid(cell->getPort(TW::C));
int nid_d = get_sig_nid(cell->getPort(TW::D));
int nid1 = next_nid++;
int nid2 = next_nid++;
@ -461,7 +461,7 @@ struct BtorWorker
btorf("%d not %d %d%s\n", nid4, sid, nid3, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
add_nid_sig(nid4, sig);
goto okay;
}
@ -478,15 +478,15 @@ struct BtorWorker
log_assert(!btor_op.empty());
int width = 1;
width = std::max(width, GetSize(cell->getPort(ID::A)));
width = std::max(width, GetSize(cell->getPort(ID::B)));
width = std::max(width, GetSize(cell->getPort(TW::A)));
width = std::max(width, GetSize(cell->getPort(TW::B)));
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
bool b_signed = cell->hasParam(ID::B_SIGNED) ? cell->getParam(ID::B_SIGNED).as_bool() : false;
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(ID::B), width, b_signed);
int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed);
int nid_b = get_sig_nid(cell->getPort(TW::B), width, b_signed);
int nid = next_nid++;
if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt))) {
@ -495,7 +495,7 @@ struct BtorWorker
btorf("%d %s %d %d %d%s\n", nid, btor_op, sid, nid_a, nid_b, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
@ -514,11 +514,11 @@ struct BtorWorker
if (cell->type.in(ID($not), ID($_NOT_))) btor_op = "not";
if (cell->type == ID($neg)) btor_op = "neg";
int width = std::max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::Y)));
int width = std::max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::Y)));
bool a_signed = cell->hasParam(ID::A_SIGNED) ? cell->getParam(ID::A_SIGNED).as_bool() : false;
int nid_a = get_sig_nid(cell->getPort(ID::A), width, a_signed);
SigSpec sig = sigmap(cell->getPort(ID::Y));
int nid_a = get_sig_nid(cell->getPort(TW::A), width, a_signed);
SigSpec sig = sigmap(cell->getPort(TW::Y));
// the $pos/$buf cells just pass through, all other cells need an actual operation applied
int nid = nid_a;
@ -550,16 +550,16 @@ struct BtorWorker
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(ID::B)) : 0;
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_b = btor_op != "not" ? get_sig_nid(cell->getPort(TW::B)) : 0;
if (GetSize(cell->getPort(ID::A)) > 1) {
if (GetSize(cell->getPort(TW::A)) > 1) {
int nid_red_a = next_nid++;
btorf("%d redor %d %d\n", nid_red_a, sid, nid_a);
nid_a = nid_red_a;
}
if (btor_op != "not" && GetSize(cell->getPort(ID::B)) > 1) {
if (btor_op != "not" && GetSize(cell->getPort(TW::B)) > 1) {
int nid_red_b = next_nid++;
btorf("%d redor %d %d\n", nid_red_b, sid, nid_b);
nid_b = nid_red_b;
@ -571,7 +571,7 @@ struct BtorWorker
else
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
@ -594,7 +594,7 @@ struct BtorWorker
log_assert(!btor_op.empty());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid = next_nid++;
@ -607,7 +607,7 @@ struct BtorWorker
btorf("%d %s %d %d%s\n", nid, btor_op, sid, nid_a, getinfo(cell));
}
SigSpec sig = sigmap(cell->getPort(ID::Y));
SigSpec sig = sigmap(cell->getPort(TW::Y));
if (GetSize(sig) > 1) {
int sid = get_bv_sid(GetSize(sig));
@ -623,10 +623,10 @@ struct BtorWorker
if (cell->type.in(ID($mux), ID($_MUX_), ID($_NMUX_)))
{
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_s = sigmap(cell->getPort(ID::S));
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_s = sigmap(cell->getPort(TW::S));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
int nid_a = get_sig_nid(sig_a);
int nid_b = get_sig_nid(sig_b);
@ -650,10 +650,10 @@ struct BtorWorker
if (cell->type == ID($pmux))
{
SigSpec sig_a = sigmap(cell->getPort(ID::A));
SigSpec sig_b = sigmap(cell->getPort(ID::B));
SigSpec sig_s = sigmap(cell->getPort(ID::S));
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_a = sigmap(cell->getPort(TW::A));
SigSpec sig_b = sigmap(cell->getPort(TW::B));
SigSpec sig_s = sigmap(cell->getPort(TW::S));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
int width = GetSize(sig_a);
int sid = get_bv_sid(width);
@ -676,8 +676,8 @@ struct BtorWorker
if (cell->type.in(ID($dff), ID($ff), ID($anyinit), ID($_DFF_P_), ID($_DFF_N), ID($_FF_)))
{
SigSpec sig_d = sigmap(cell->getPort(ID::D));
SigSpec sig_q = sigmap(cell->getPort(ID::Q));
SigSpec sig_d = sigmap(cell->getPort(TW::D));
SigSpec sig_q = sigmap(cell->getPort(TW::Q));
if ((!info_filename.empty() || ywmap_json.active()) && cell->type.in(ID($dff), ID($_DFF_P_), ID($_DFF_N_)))
{
@ -730,7 +730,7 @@ struct BtorWorker
btorf("%d state %d %s\n", nid, sid, symbol.unescape());
if (cell->get_bool_attribute(ID(clk2fflogic)))
ywmap_state(cell->getPort(ID::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
ywmap_state(cell->getPort(TW::D)); // For a clk2fflogic FF the named signal is the D input not the Q output
else
ywmap_state(sig_q);
@ -748,7 +748,7 @@ struct BtorWorker
if (cell->type.in(ID($anyconst), ID($anyseq)))
{
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
int sid = get_bv_sid(GetSize(sig_y));
int nid = next_nid++;
@ -768,7 +768,7 @@ struct BtorWorker
if (cell->type == ID($initstate))
{
SigSpec sig_y = sigmap(cell->getPort(ID::Y));
SigSpec sig_y = sigmap(cell->getPort(TW::Y));
if (initstate_nid < 0)
{
@ -1272,8 +1272,8 @@ struct BtorWorker
btorf_push(cell->name.unescape());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_en = get_sig_nid(cell->getPort(TW::EN));
int nid_not_en = next_nid++;
int nid_a_or_not_en = next_nid++;
int nid = next_nid++;
@ -1292,8 +1292,8 @@ struct BtorWorker
btorf_push(cell->name.unescape());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_en = get_sig_nid(cell->getPort(TW::EN));
int nid_not_a = next_nid++;
int nid_en_and_not_a = next_nid++;
@ -1321,8 +1321,8 @@ struct BtorWorker
btorf_push(cell->name.unescape());
int sid = get_bv_sid(1);
int nid_a = get_sig_nid(cell->getPort(ID::A));
int nid_en = get_sig_nid(cell->getPort(ID::EN));
int nid_a = get_sig_nid(cell->getPort(TW::A));
int nid_en = get_sig_nid(cell->getPort(TW::EN));
int nid_en_and_a = next_nid++;
btorf("%d and %d %d %d\n", nid_en_and_a, sid, nid_en, nid_a);
@ -1372,7 +1372,7 @@ struct BtorWorker
btorf_push(stringf("next %s", cell));
SigSpec sig = sigmap(cell->getPort(ID::D));
SigSpec sig = sigmap(cell->getPort(TW::D));
int nid_q = get_sig_nid(sig);
int sid = get_bv_sid(GetSize(sig));
btorf("%d next %d %d %d%s\n", next_nid++, sid, nid, nid_q, getinfo(cell));

116
backends/cxxrtl/cxxrtl_backend.cc
View file

@ -243,7 +243,7 @@ enum class CxxrtlPortType {
SYNC = 2,
};
CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, RTLIL::IdString port)
CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, TwineRef port)
{
RTLIL::Wire *output_wire = module->wire(port);
log_assert(output_wire != nullptr);
@ -259,7 +259,7 @@ CxxrtlPortType cxxrtl_port_type(RTLIL::Module *module, RTLIL::IdString port)
return CxxrtlPortType::UNKNOWN;
}
CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, TwineRef port)
{
RTLIL::Module *cell_module = cell->module->design->module(cell->type);
if (cell_module == nullptr || !cell_module->get_bool_attribute(ID(cxxrtl_blackbox)))
@ -267,12 +267,12 @@ CxxrtlPortType cxxrtl_port_type(const RTLIL::Cell *cell, RTLIL::IdString port)
return cxxrtl_port_type(cell_module, port);
}
bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, RTLIL::IdString port)
bool is_cxxrtl_comb_port(const RTLIL::Cell *cell, TwineRef port)
{
return cxxrtl_port_type(cell, port) == CxxrtlPortType::COMB;
}
bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, RTLIL::IdString port)
bool is_cxxrtl_sync_port(const RTLIL::Cell *cell, TwineRef port)
{
return cxxrtl_port_type(cell, port) == CxxrtlPortType::SYNC;
}
@ -1139,7 +1139,7 @@ struct CxxrtlWorker {
if (is_extending_cell(cell->type))
f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u');
f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ")";
// Binary cells
} else if (is_binary_cell(cell->type)) {
@ -1148,18 +1148,18 @@ struct CxxrtlWorker {
f << '_' << (cell->getParam(ID::A_SIGNED).as_bool() ? 's' : 'u') <<
(cell->getParam(ID::B_SIGNED).as_bool() ? 's' : 'u');
f << "<" << cell->getParam(ID::Y_WIDTH).as_int() << ">(";
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ", ";
dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << ")";
// Muxes
} else if (cell->type == ID($mux)) {
f << "(";
dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << " ? ";
dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << " : ";
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ")";
// Parallel (one-hot) muxes
} else if (cell->type == ID($pmux)) {
@ -1167,48 +1167,48 @@ struct CxxrtlWorker {
int s_width = cell->getParam(ID::S_WIDTH).as_int();
for (int part = 0; part < s_width; part++) {
f << "(";
dump_sigspec_rhs(cell->getPort(ID::S).extract(part), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S).extract(part), for_debug);
f << " ? ";
dump_sigspec_rhs(cell->getPort(ID::B).extract(part * width, width), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B).extract(part * width, width), for_debug);
f << " : ";
}
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
for (int part = 0; part < s_width; part++) {
f << ")";
}
// Big muxes
} else if (cell->type == ID($bmux)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".bmux<";
f << cell->getParam(ID::WIDTH).as_int();
f << ">(";
dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Bitwise muxes
} else if (cell->type == ID($bwmux)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".bwmux(";
dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << ",";
dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Demuxes
} else if (cell->type == ID($demux)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".demux<";
f << GetSize(cell->getPort(ID::Y));
f << GetSize(cell->getPort(TW::Y));
f << ">(";
dump_sigspec_rhs(cell->getPort(ID::S), for_debug);
dump_sigspec_rhs(cell->getPort(TW::S), for_debug);
f << ").val()";
// Concats
} else if (cell->type == ID($concat)) {
dump_sigspec_rhs(cell->getPort(ID::B), for_debug);
dump_sigspec_rhs(cell->getPort(TW::B), for_debug);
f << ".concat(";
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ").val()";
// Slices
} else if (cell->type == ID($slice)) {
dump_sigspec_rhs(cell->getPort(ID::A), for_debug);
dump_sigspec_rhs(cell->getPort(TW::A), for_debug);
f << ".slice<";
f << cell->getParam(ID::OFFSET).as_int() + cell->getParam(ID::Y_WIDTH).as_int() - 1;
f << ",";
@ -1225,7 +1225,7 @@ struct CxxrtlWorker {
fmt.parse_rtlil(cell);
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << " == value<1>{1u}) {\n";
inc_indent();
dict<std::string, RTLIL::SigSpec> fmt_args;
@ -1277,7 +1277,7 @@ struct CxxrtlWorker {
fmt.parse_rtlil(cell);
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << ") {\n";
inc_indent();
dict<std::string, RTLIL::SigSpec> fmt_args;
@ -1309,7 +1309,7 @@ struct CxxrtlWorker {
}
if (cell->hasPort(ID::A)) {
f << indent << "bool condition = (bool)";
dump_sigspec_rhs(cell->getPort(ID::A));
dump_sigspec_rhs(cell->getPort(TW::A));
f << ";\n";
}
f << indent << "if (performer) {\n";
@ -1366,7 +1366,7 @@ struct CxxrtlWorker {
// Elidable cells
if (is_inlinable_cell(cell->type)) {
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Y), for_debug);
dump_sigspec_lhs(cell->getPort(TW::Y), for_debug);
f << " = ";
dump_cell_expr(cell, for_debug);
f << ";\n";
@ -1379,12 +1379,12 @@ struct CxxrtlWorker {
if (!cell->getParam(ID::TRG_ENABLE).as_bool()) { // async effectful cell
f << indent << "auto " << mangle(cell) << "_next = ";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << ".concat(";
if (cell->type == ID($print))
dump_sigspec_rhs(cell->getPort(ID::ARGS));
dump_sigspec_rhs(cell->getPort(TW::ARGS));
else if (cell->type == ID($check))
dump_sigspec_rhs(cell->getPort(ID::A));
dump_sigspec_rhs(cell->getPort(TW::A));
else log_assert(false);
f << ").val();\n";
@ -1406,9 +1406,9 @@ struct CxxrtlWorker {
} else if (is_ff_cell(cell->type)) {
log_assert(!for_debug);
// Clocks might be slices of larger signals but should only ever be single bit
if (cell->hasPort(ID::CLK) && is_valid_clock(cell->getPort(ID::CLK))) {
if (cell->hasPort(ID::CLK) && is_valid_clock(cell->getPort(TW::CLK))) {
// Edge-sensitive logic
RTLIL::SigBit clk_bit = cell->getPort(ID::CLK)[0];
RTLIL::SigBit clk_bit = cell->getPort(TW::CLK)[0];
clk_bit = sigmaps[clk_bit.wire->module](clk_bit);
if (clk_bit.wire) {
f << indent << "if (" << (cell->getParam(ID::CLK_POLARITY).as_bool() ? "posedge_" : "negedge_")
@ -1419,14 +1419,14 @@ struct CxxrtlWorker {
inc_indent();
if (cell->hasPort(ID::EN)) {
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
inc_indent();
}
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::D));
dump_sigspec_rhs(cell->getPort(TW::D));
f << ";\n";
if (cell->hasPort(ID::EN) && cell->type != ID($sdffce)) {
dec_indent();
@ -1434,11 +1434,11 @@ struct CxxrtlWorker {
}
if (cell->hasPort(ID::SRST)) {
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::SRST));
dump_sigspec_rhs(cell->getPort(TW::SRST));
f << " == value<1> {" << cell->getParam(ID::SRST_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_const(cell->getParam(ID::SRST_VALUE));
f << ";\n";
@ -1454,13 +1454,13 @@ struct CxxrtlWorker {
} else if (cell->hasPort(ID::EN)) {
// Level-sensitive logic
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::EN));
dump_sigspec_rhs(cell->getPort(TW::EN));
f << " == value<1> {" << cell->getParam(ID::EN_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::D));
dump_sigspec_rhs(cell->getPort(TW::D));
f << ";\n";
dec_indent();
f << indent << "}\n";
@ -1468,11 +1468,11 @@ struct CxxrtlWorker {
if (cell->hasPort(ID::ARST)) {
// Asynchronous reset (entire coarse cell at once)
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::ARST));
dump_sigspec_rhs(cell->getPort(TW::ARST));
f << " == value<1> {" << cell->getParam(ID::ARST_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_const(cell->getParam(ID::ARST_VALUE));
f << ";\n";
@ -1482,13 +1482,13 @@ struct CxxrtlWorker {
if (cell->hasPort(ID::ALOAD)) {
// Asynchronous load
f << indent << "if (";
dump_sigspec_rhs(cell->getPort(ID::ALOAD));
dump_sigspec_rhs(cell->getPort(TW::ALOAD));
f << " == value<1> {" << cell->getParam(ID::ALOAD_POLARITY).as_bool() << "u}) {\n";
inc_indent();
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::AD));
dump_sigspec_rhs(cell->getPort(TW::AD));
f << ";\n";
dec_indent();
f << indent << "}\n";
@ -1496,25 +1496,25 @@ struct CxxrtlWorker {
if (cell->hasPort(ID::SET)) {
// Asynchronous set (for individual bits)
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::Q));
dump_sigspec_rhs(cell->getPort(TW::Q));
f << ".update(";
dump_const(RTLIL::Const(RTLIL::S1, cell->getParam(ID::WIDTH).as_int()));
f << ", ";
dump_sigspec_rhs(cell->getPort(ID::SET));
dump_sigspec_rhs(cell->getPort(TW::SET));
f << (cell->getParam(ID::SET_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
if (cell->hasPort(ID::CLR)) {
// Asynchronous clear (for individual bits; priority over set)
f << indent;
dump_sigspec_lhs(cell->getPort(ID::Q));
dump_sigspec_lhs(cell->getPort(TW::Q));
f << " = ";
dump_sigspec_rhs(cell->getPort(ID::Q));
dump_sigspec_rhs(cell->getPort(TW::Q));
f << ".update(";
dump_const(RTLIL::Const(RTLIL::S0, cell->getParam(ID::WIDTH).as_int()));
f << ", ";
dump_sigspec_rhs(cell->getPort(ID::CLR));
dump_sigspec_rhs(cell->getPort(TW::CLR));
f << (cell->getParam(ID::CLR_POLARITY).as_bool() ? "" : ".bit_not()") << ");\n";
}
// Internal cells
@ -1788,7 +1788,7 @@ struct CxxrtlWorker {
void dump_cell_effect_sync(std::vector<const RTLIL::Cell*> &cells)
{
log_assert(!cells.empty());
const auto &trg = cells[0]->getPort(ID::TRG);
const auto &trg = cells[0]->getPort(TW::TRG);
const auto &trg_polarity = cells[0]->getParam(ID::TRG_POLARITY);
f << indent << "if (";
@ -1813,7 +1813,7 @@ struct CxxrtlWorker {
});
for (auto cell : cells) {
log_assert(cell->getParam(ID::TRG_ENABLE).as_bool());
log_assert(cell->getPort(ID::TRG) == trg);
log_assert(cell->getPort(TW::TRG) == trg);
log_assert(cell->getParam(ID::TRG_POLARITY) == trg_polarity);
std::vector<const RTLIL::Cell*> inlined_cells;
@ -2999,15 +2999,15 @@ struct CxxrtlWorker {
// Various DFF cells are treated like posedge/negedge processes, see above for details.
if (cell->type.in(ID($dff), ID($dffe), ID($adff), ID($adffe), ID($aldff), ID($aldffe), ID($dffsr), ID($dffsre), ID($sdff), ID($sdffe), ID($sdffce))) {
if (is_valid_clock(cell->getPort(ID::CLK)))
register_edge_signal(sigmap, cell->getPort(ID::CLK),
if (is_valid_clock(cell->getPort(TW::CLK)))
register_edge_signal(sigmap, cell->getPort(TW::CLK),
cell->parameters[ID::CLK_POLARITY].as_bool() ? RTLIL::STp : RTLIL::STn);
}
// Effectful cells may be triggered on posedge/negedge events.
if (is_effectful_cell(cell->type) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
for (size_t i = 0; i < (size_t)cell->getParam(ID::TRG_WIDTH).as_int(); i++) {
RTLIL::SigBit trg = cell->getPort(ID::TRG).extract(i, 1);
RTLIL::SigBit trg = cell->getPort(TW::TRG).extract(i, 1);
if (is_valid_clock(trg))
register_edge_signal(sigmap, trg,
cell->parameters[ID::TRG_POLARITY][i] == RTLIL::S1 ? RTLIL::STp : RTLIL::STn);
@ -3216,7 +3216,7 @@ struct CxxrtlWorker {
is_effectful_cell(node->cell->type) &&
node->cell->getParam(ID::TRG_ENABLE).as_bool() &&
node->cell->getParam(ID::TRG_WIDTH).as_int() != 0)
effect_sync_cells[make_pair(node->cell->getPort(ID::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
effect_sync_cells[make_pair(node->cell->getPort(TW::TRG), node->cell->getParam(ID::TRG_POLARITY))].push_back(node->cell);
else
schedule[module].push_back(*node);
}

48
backends/firrtl/firrtl.cc
View file

@ -601,7 +601,7 @@ struct FirrtlWorker
if (cell->type.in(ID($not), ID($logic_not), ID($_NOT_), ID($neg), ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_bool), ID($reduce_xnor)))
{
string a_expr = make_expr(cell->getPort(ID::A));
string a_expr = make_expr(cell->getPort(TW::A));
wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo));
if (a_signed) {
@ -643,7 +643,7 @@ struct FirrtlWorker
expr = stringf("asUInt(%s)", expr);
cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
@ -651,8 +651,8 @@ struct FirrtlWorker
ID($gt), ID($ge), ID($lt), ID($le), ID($ne), ID($nex), ID($shr), ID($sshr), ID($sshl), ID($shl),
ID($logic_and), ID($logic_or), ID($pow)))
{
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string a_expr = make_expr(cell->getPort(TW::A));
string b_expr = make_expr(cell->getPort(TW::B));
std::string cellFileinfo = getFileinfo(cell);
wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, y_width, cellFileinfo));
@ -690,7 +690,7 @@ struct FirrtlWorker
}
// Assume the FIRRTL width is the width of "A"
firrtl_width = a_width;
auto a_sig = cell->getPort(ID::A);
auto a_sig = cell->getPort(TW::A);
if (cell->type == ID($add)) {
primop = "add";
@ -769,7 +769,7 @@ struct FirrtlWorker
// We'll need to offset this by extracting the un-widened portion as Verilog would do.
extract_y_bits = true;
// Is the shift amount constant?
auto b_sig = cell->getPort(ID::B);
auto b_sig = cell->getPort(TW::B);
if (b_sig.is_fully_const()) {
primop = "shl";
int shift_amount = b_sig.as_int();
@ -786,7 +786,7 @@ struct FirrtlWorker
// We don't need to extract a specific range of bits.
extract_y_bits = false;
// Is the shift amount constant?
auto b_sig = cell->getPort(ID::B);
auto b_sig = cell->getPort(TW::B);
if (b_sig.is_fully_const()) {
primop = "shr";
int shift_amount = b_sig.as_int();
@ -828,7 +828,7 @@ struct FirrtlWorker
a_expr = firrtl_is_signed ? "SInt(1)" : "UInt(1)";
extract_y_bits = true;
// Is the shift amount constant?
auto b_sig = cell->getPort(ID::B);
auto b_sig = cell->getPort(TW::B);
if (b_sig.is_fully_const()) {
primop = "shl";
int shiftAmount = b_sig.as_int();
@ -873,7 +873,7 @@ struct FirrtlWorker
expr = stringf("asUInt(%s)", expr);
cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
@ -882,15 +882,15 @@ struct FirrtlWorker
{
auto it = cell->parameters.find(ID::WIDTH);
int width = it == cell->parameters.end()? 1 : it->second.as_int();
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string s_expr = make_expr(cell->getPort(ID::S));
string a_expr = make_expr(cell->getPort(TW::A));
string b_expr = make_expr(cell->getPort(TW::B));
string s_expr = make_expr(cell->getPort(TW::S));
wire_decls.push_back(stringf("%swire %s: UInt<%d> %s\n", indent, y_id, width, cellFileinfo));
string expr = stringf("mux(%s, %s, %s)", s_expr, b_expr, a_expr);
cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
@ -908,13 +908,13 @@ struct FirrtlWorker
log_error("Negative edge clock on FF %s.%s.\n", module, cell);
int width = cell->parameters.at(ID::WIDTH).as_int();
string expr = make_expr(cell->getPort(ID::D));
string clk_expr = "asClock(" + make_expr(cell->getPort(ID::CLK)) + ")";
string expr = make_expr(cell->getPort(TW::D));
string clk_expr = "asClock(" + make_expr(cell->getPort(TW::CLK)) + ")";
wire_decls.push_back(stringf("%sreg %s: UInt<%d>, %s %s\n", indent, y_id, width, clk_expr, cellFileinfo));
cell_exprs.push_back(stringf("%s%s <= %s %s\n", indent, y_id, expr, cellFileinfo));
register_reverse_wire_map(y_id, cell->getPort(ID::Q));
register_reverse_wire_map(y_id, cell->getPort(TW::Q));
continue;
}
@ -923,9 +923,9 @@ struct FirrtlWorker
// assign y = a[b +: y_width];
// We'll extract the correct bits as part of the primop.
string a_expr = make_expr(cell->getPort(ID::A));
string a_expr = make_expr(cell->getPort(TW::A));
// Get the initial bit selector
string b_expr = make_expr(cell->getPort(ID::B));
string b_expr = make_expr(cell->getPort(TW::B));
wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width));
if (cell->getParam(ID::B_SIGNED).as_bool()) {
@ -937,15 +937,15 @@ struct FirrtlWorker
string expr = stringf("dshr(%s, %s)", a_expr, b_expr);
cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
if (cell->type == ID($shift)) {
// assign y = a >> b;
// where b may be negative
string a_expr = make_expr(cell->getPort(ID::A));
string b_expr = make_expr(cell->getPort(ID::B));
string a_expr = make_expr(cell->getPort(TW::A));
string b_expr = make_expr(cell->getPort(TW::B));
auto b_string = b_expr.c_str();
string expr;
wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width));
@ -963,13 +963,13 @@ struct FirrtlWorker
expr = stringf("dshr(%s, %s)", a_expr, b_string);
}
cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, expr));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}
if (cell->type == ID($pos)) {
// assign y = a;
// printCell(cell);
string a_expr = make_expr(cell->getPort(ID::A));
string a_expr = make_expr(cell->getPort(TW::A));
// Verilog appears to treat the result as signed, so if the result is wider than "A",
// we need to pad.
if (a_width < y_width) {
@ -977,7 +977,7 @@ struct FirrtlWorker
}
wire_decls.push_back(stringf("%swire %s: UInt<%d>\n", indent, y_id, y_width));
cell_exprs.push_back(stringf("%s%s <= %s\n", indent, y_id, a_expr));
register_reverse_wire_map(y_id, cell->getPort(ID::Y));
register_reverse_wire_map(y_id, cell->getPort(TW::Y));
continue;
}

36
backends/simplec/simplec.cc
View file

@ -380,8 +380,8 @@ struct SimplecWorker
{
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string expr;
@ -399,9 +399,9 @@ struct SimplecWorker
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
@ -426,10 +426,10 @@ struct SimplecWorker
if (cell->type.in(ID($_AOI3_), ID($_OAI3_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
SigBit c = sigmaps.at(work->module)(cell->getPort(TW::C));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
@ -449,11 +449,11 @@ struct SimplecWorker
if (cell->type.in(ID($_AOI4_), ID($_OAI4_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit c = sigmaps.at(work->module)(cell->getPort(ID::C));
SigBit d = sigmaps.at(work->module)(cell->getPort(ID::D));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
SigBit c = sigmaps.at(work->module)(cell->getPort(TW::C));
SigBit d = sigmaps.at(work->module)(cell->getPort(TW::D));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";
@ -474,10 +474,10 @@ struct SimplecWorker
if (cell->type.in(ID($_MUX_), ID($_NMUX_)))
{
SigBit a = sigmaps.at(work->module)(cell->getPort(ID::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(ID::B));
SigBit s = sigmaps.at(work->module)(cell->getPort(ID::S));
SigBit y = sigmaps.at(work->module)(cell->getPort(ID::Y));
SigBit a = sigmaps.at(work->module)(cell->getPort(TW::A));
SigBit b = sigmaps.at(work->module)(cell->getPort(TW::B));
SigBit s = sigmaps.at(work->module)(cell->getPort(TW::S));
SigBit y = sigmaps.at(work->module)(cell->getPort(TW::Y));
string a_expr = a.wire ? util_get_bit(work->prefix + cid(a.wire->name), a.wire->width, a.offset) : a.data ? "1" : "0";
string b_expr = b.wire ? util_get_bit(work->prefix + cid(b.wire->name), b.wire->width, b.offset) : b.data ? "1" : "0";

94
backends/smt2/smt2.cc
View file

@ -435,15 +435,15 @@ struct Smt2Worker
void export_gate(RTLIL::Cell *cell, std::string expr)
{
RTLIL::SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
RTLIL::SigBit bit = sigmap(cell->getPort(TW::Y).as_bit());
std::string processed_expr;
for (char ch : expr) {
if (ch == 'A') processed_expr += get_bool(cell->getPort(ID::A));
else if (ch == 'B') processed_expr += get_bool(cell->getPort(ID::B));
else if (ch == 'C') processed_expr += get_bool(cell->getPort(ID::C));
else if (ch == 'D') processed_expr += get_bool(cell->getPort(ID::D));
else if (ch == 'S') processed_expr += get_bool(cell->getPort(ID::S));
if (ch == 'A') processed_expr += get_bool(cell->getPort(TW::A));
else if (ch == 'B') processed_expr += get_bool(cell->getPort(TW::B));
else if (ch == 'C') processed_expr += get_bool(cell->getPort(TW::C));
else if (ch == 'D') processed_expr += get_bool(cell->getPort(TW::D));
else if (ch == 'S') processed_expr += get_bool(cell->getPort(TW::S));
else processed_expr += ch;
}
@ -459,26 +459,26 @@ struct Smt2Worker
void export_bvop(RTLIL::Cell *cell, std::string expr, char type = 0)
{
RTLIL::SigSpec sig_a, sig_b;
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
bool is_signed = type == 'U' ? false : cell->getParam(ID::A_SIGNED).as_bool();
int width = GetSize(sig_y);
if (type == 's' || type == 'S' || type == 'd' || type == 'b') {
if (type == 'b')
width = GetSize(cell->getPort(ID::A));
width = GetSize(cell->getPort(TW::A));
else
width = max(width, GetSize(cell->getPort(ID::A)));
width = max(width, GetSize(cell->getPort(TW::A)));
if (cell->hasPort(ID::B))
width = max(width, GetSize(cell->getPort(ID::B)));
width = max(width, GetSize(cell->getPort(TW::B)));
}
if (cell->hasPort(ID::A)) {
sig_a = cell->getPort(ID::A);
sig_a = cell->getPort(TW::A);
sig_a.extend_u0(width, is_signed);
}
if (cell->hasPort(ID::B)) {
sig_b = cell->getPort(ID::B);
sig_b = cell->getPort(TW::B);
sig_b.extend_u0(width, (type == 'S') || (is_signed && !(type == 's')));
}
@ -487,8 +487,8 @@ struct Smt2Worker
for (char ch : expr) {
if (ch == 'A') processed_expr += get_bv(sig_a);
else if (ch == 'B') processed_expr += get_bv(sig_b);
else if (ch == 'P') processed_expr += get_bv(cell->getPort(ID::B));
else if (ch == 'S') processed_expr += get_bv(cell->getPort(ID::S));
else if (ch == 'P') processed_expr += get_bv(cell->getPort(TW::B));
else if (ch == 'S') processed_expr += get_bv(cell->getPort(TW::S));
else if (ch == 'L') processed_expr += is_signed ? "a" : "l";
else if (ch == 'U') processed_expr += is_signed ? "s" : "u";
else processed_expr += ch;
@ -515,7 +515,7 @@ struct Smt2Worker
void export_reduce(RTLIL::Cell *cell, std::string expr, bool identity_val)
{
RTLIL::SigSpec sig_y = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig_y = sigmap(cell->getPort(TW::Y));
std::string processed_expr;
for (char ch : expr)
@ -554,7 +554,7 @@ struct Smt2Worker
if (cell->type == ID($initstate))
{
SigBit bit = sigmap(cell->getPort(ID::Y).as_bit());
SigBit bit = sigmap(cell->getPort(TW::Y).as_bit());
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) Bool (|%s_is| state)) ; %s\n",
get_id(module), idcounter, get_id(module), get_id(module), log_signal(bit)));
register_bool(bit, idcounter++);
@ -565,11 +565,11 @@ struct Smt2Worker
if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
{
registers.insert(cell);
SigBit q_bit = cell->getPort(ID::Q);
SigBit q_bit = cell->getPort(TW::Q);
if (q_bit.is_wire())
decls.push_back(witness_signal("reg", 1, 0, "", idcounter, q_bit.wire));
makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(ID::Q)));
register_bool(cell->getPort(ID::Q), idcounter++);
makebits(stringf("%s#%d", get_id(module), idcounter), 0, log_signal(cell->getPort(TW::Q)));
register_bool(cell->getPort(TW::Q), idcounter++);
recursive_cells.erase(cell);
return;
}
@ -599,13 +599,13 @@ struct Smt2Worker
{
registers.insert(cell);
int smtoffset = 0;
for (auto chunk : cell->getPort(ID::Q).chunks()) {
for (auto chunk : cell->getPort(TW::Q).chunks()) {
if (chunk.is_wire())
decls.push_back(witness_signal("reg", chunk.width, chunk.offset, "", idcounter, chunk.wire, smtoffset));
smtoffset += chunk.width;
}
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q)));
register_bv(cell->getPort(ID::Q), idcounter++);
makebits(stringf("%s#%d", get_id(module), idcounter), GetSize(cell->getPort(TW::Q)), log_signal(cell->getPort(TW::Q)));
register_bv(cell->getPort(TW::Q), idcounter++);
recursive_cells.erase(cell);
return;
}
@ -667,7 +667,7 @@ struct Smt2Worker
if (cell->getParam(ID::B_SIGNED).as_bool()) {
return export_bvop(cell, stringf("(ite (bvsge P #b%0*d) "
"(bvlshr A B) (bvshl A (bvneg B)))",
GetSize(cell->getPort(ID::B)), 0), 'S'); // type 'S' sign extends B
GetSize(cell->getPort(TW::B)), 0), 'S'); // type 'S' sign extends B
} else {
return export_bvop(cell, "(bvlshr A B)", 's');
}
@ -706,8 +706,8 @@ struct Smt2Worker
if (cell->type == ID($divfloor)) {
if (cell->getParam(ID::A_SIGNED).as_bool()) {
// bvsdiv is truncating division, so we can't use it here.
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
width = max(width, GetSize(cell->getPort(ID::Y)));
int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
width = max(width, GetSize(cell->getPort(TW::Y)));
auto expr = stringf("(let ("
"(a_neg (bvslt A #b%0*d)) "
"(b_neg (bvslt B #b%0*d))) "
@ -725,9 +725,9 @@ struct Smt2Worker
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)) &&
2*GetSize(cell->getPort(ID::A).chunks()) < GetSize(cell->getPort(ID::A))) {
2*GetSize(cell->getPort(TW::A).chunks()) < GetSize(cell->getPort(TW::A))) {
bool is_and = cell->type == ID($reduce_and);
string bits(GetSize(cell->getPort(ID::A)), is_and ? '1' : '0');
string bits(GetSize(cell->getPort(TW::A)), is_and ? '1' : '0');
return export_bvop(cell, stringf("(%s A #b%s)", is_and ? "=" : "distinct", bits), 'b');
}
@ -743,11 +743,11 @@ struct Smt2Worker
if (cell->type.in(ID($mux), ID($pmux)))
{
int width = GetSize(cell->getPort(ID::Y));
std::string processed_expr = get_bv(cell->getPort(ID::A));
int width = GetSize(cell->getPort(TW::Y));
std::string processed_expr = get_bv(cell->getPort(TW::A));
RTLIL::SigSpec sig_b = cell->getPort(ID::B);
RTLIL::SigSpec sig_s = cell->getPort(ID::S);
RTLIL::SigSpec sig_b = cell->getPort(TW::B);
RTLIL::SigSpec sig_s = cell->getPort(TW::S);
get_bv(sig_b);
get_bv(sig_s);
@ -758,7 +758,7 @@ struct Smt2Worker
if (verbose)
log("%*s-> import cell: %s\n", 2+2*GetSize(recursive_cells), "", cell);
RTLIL::SigSpec sig = sigmap(cell->getPort(ID::Y));
RTLIL::SigSpec sig = sigmap(cell->getPort(TW::Y));
decls.push_back(stringf("(define-fun |%s#%d| ((state |%s_s|)) (_ BitVec %d) %s) ; %s\n",
get_id(module), idcounter, get_id(module), width, processed_expr.c_str(), log_signal(sig)));
register_bv(sig, idcounter++);
@ -971,7 +971,7 @@ struct Smt2Worker
for (auto cell : module->cells())
if (cell->type.in(ID($ff), ID($dff), ID($_FF_), ID($_DFF_P_), ID($_DFF_N_), ID($anyinit))) {
// not using sigmap -- we want the net directly at the dff output
for (auto bit : cell->getPort(ID::Q))
for (auto bit : cell->getPort(TW::Q))
reg_bits.insert(bit);
}
@ -1123,8 +1123,8 @@ struct Smt2Worker
cell->type == ID($assume) ? 'u' :
cell->type == ID($cover) ? 'c' : 0;
string name_a = get_bool(cell->getPort(ID::A));
string name_en = get_bool(cell->getPort(ID::EN));
string name_a = get_bool(cell->getPort(TW::A));
string name_en = get_bool(cell->getPort(TW::EN));
bool private_name = cell->name[0] == '$';
if (!private_name && cell->has_attribute(ID::hdlname)) {
@ -1211,27 +1211,27 @@ struct Smt2Worker
{
if (cell->type.in(ID($_FF_), ID($_DFF_P_), ID($_DFF_N_)))
{
std::string expr_d = get_bool(cell->getPort(ID::D));
std::string expr_q = get_bool(cell->getPort(ID::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(ID::Q)), get_bool(cell->getPort(ID::Q), "other_state")));
std::string expr_d = get_bool(cell->getPort(TW::D));
std::string expr_q = get_bool(cell->getPort(TW::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bool(cell->getPort(TW::Q)), get_bool(cell->getPort(TW::Q), "other_state")));
}
if (cell->type.in(ID($ff), ID($dff), ID($anyinit)))
{
std::string expr_d = get_bv(cell->getPort(ID::D));
std::string expr_q = get_bv(cell->getPort(ID::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Q)), get_bv(cell->getPort(ID::Q), "other_state")));
std::string expr_d = get_bv(cell->getPort(TW::D));
std::string expr_q = get_bv(cell->getPort(TW::Q), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Q))));
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Q)), get_bv(cell->getPort(TW::Q), "other_state")));
}
if (cell->type.in(ID($anyconst), ID($allconst)))
{
std::string expr_d = get_bv(cell->getPort(ID::Y));
std::string expr_q = get_bv(cell->getPort(ID::Y), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(ID::Y))));
std::string expr_d = get_bv(cell->getPort(TW::Y));
std::string expr_q = get_bv(cell->getPort(TW::Y), "next_state");
trans.push_back(stringf(" (= %s %s) ; %s %s\n", expr_d, expr_q, get_id(cell), log_signal(cell->getPort(TW::Y))));
if (cell->type == ID($anyconst))
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(ID::Y)), get_bv(cell->getPort(ID::Y), "other_state")));
ex_state_eq.push_back(stringf("(= %s %s)", get_bv(cell->getPort(TW::Y)), get_bv(cell->getPort(TW::Y), "other_state")));
}
}

146
backends/smv/smv.cc
View file

@ -229,8 +229,8 @@ struct SmvWorker
if (cell->type.in(ID($assert)))
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_en = cell->getPort(ID::EN);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_en = cell->getPort(TW::EN);
invarspecs.push_back(stringf("!bool(%s) | bool(%s);", rvalue(sig_en), rvalue(sig_a)));
@ -239,10 +239,10 @@ struct SmvWorker
if (cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)))
{
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
int width_y = GetSize(cell->getPort(ID::Y));
int width_y = GetSize(cell->getPort(TW::Y));
int shift_b_width = GetSize(sig_b);
int width_ay = max(GetSize(sig_a), width_y);
int width = width_ay;
@ -303,14 +303,14 @@ struct SmvWorker
GetSize(sig_b)-shift_b_width, width_y, expr.c_str());
}
definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr));
definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(TW::Y)), expr));
continue;
}
if (cell->type.in(ID($not), ID($pos), ID($neg)))
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
string expr_a, op;
if (cell->type == ID($not)) op = "!";
@ -319,13 +319,13 @@ struct SmvWorker
if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(ID::Y)),
op.c_str(), rvalue_s(cell->getPort(ID::A), width)));
definitions.push_back(stringf("%s := unsigned(%s%s);", lvalue(cell->getPort(TW::Y)),
op.c_str(), rvalue_s(cell->getPort(TW::A), width)));
}
else
{
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)),
op.c_str(), rvalue_u(cell->getPort(ID::A), width)));
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(TW::Y)),
op.c_str(), rvalue_u(cell->getPort(TW::A), width)));
}
continue;
@ -333,7 +333,7 @@ struct SmvWorker
if (cell->type.in(ID($add), ID($sub), ID($mul), ID($and), ID($or), ID($xor), ID($xnor)))
{
int width = GetSize(cell->getPort(ID::Y));
int width = GetSize(cell->getPort(TW::Y));
string expr_a, expr_b, op;
if (cell->type == ID($add)) op = "+";
@ -346,13 +346,13 @@ struct SmvWorker
if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(ID::Y)),
rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width)));
definitions.push_back(stringf("%s := unsigned(%s %s %s);", lvalue(cell->getPort(TW::Y)),
rvalue_s(cell->getPort(TW::A), width), op.c_str(), rvalue_s(cell->getPort(TW::B), width)));
}
else
{
definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)),
rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width)));
definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(TW::Y)),
rvalue_u(cell->getPort(TW::A), width), op.c_str(), rvalue_u(cell->getPort(TW::B), width)));
}
continue;
@ -361,9 +361,9 @@ struct SmvWorker
// SMV has a "mod" operator, but its semantics don't seem to be well-defined - to be safe, don't generate it at all
if (cell->type.in(ID($div)/*, ID($mod), ID($modfloor)*/))
{
int width_y = GetSize(cell->getPort(ID::Y));
int width = max(width_y, GetSize(cell->getPort(ID::A)));
width = max(width, GetSize(cell->getPort(ID::B)));
int width_y = GetSize(cell->getPort(TW::Y));
int width = max(width_y, GetSize(cell->getPort(TW::A)));
width = max(width, GetSize(cell->getPort(TW::B)));
string expr_a, expr_b, op;
if (cell->type == ID($div)) op = "/";
@ -371,13 +371,13 @@ struct SmvWorker
if (cell->getParam(ID::A_SIGNED).as_bool())
{
definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)),
rvalue_s(cell->getPort(ID::A), width), op.c_str(), rvalue_s(cell->getPort(ID::B), width), width_y));
definitions.push_back(stringf("%s := resize(unsigned(%s %s %s), %d);", lvalue(cell->getPort(TW::Y)),
rvalue_s(cell->getPort(TW::A), width), op.c_str(), rvalue_s(cell->getPort(TW::B), width), width_y));
}
else
{
definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(ID::Y)),
rvalue_u(cell->getPort(ID::A), width), op.c_str(), rvalue_u(cell->getPort(ID::B), width), width_y));
definitions.push_back(stringf("%s := resize(%s %s %s, %d);", lvalue(cell->getPort(TW::Y)),
rvalue_u(cell->getPort(TW::A), width), op.c_str(), rvalue_u(cell->getPort(TW::B), width), width_y));
}
continue;
@ -385,7 +385,7 @@ struct SmvWorker
if (cell->type.in(ID($eq), ID($ne), ID($eqx), ID($nex), ID($lt), ID($le), ID($ge), ID($gt)))
{
int width = max(GetSize(cell->getPort(ID::A)), GetSize(cell->getPort(ID::B)));
int width = max(GetSize(cell->getPort(TW::A)), GetSize(cell->getPort(TW::B)));
string expr_a, expr_b, op;
if (cell->type == ID($eq)) op = "=";
@ -399,27 +399,27 @@ struct SmvWorker
if (cell->getParam(ID::A_SIGNED).as_bool())
{
expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::A)), width);
expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(ID::B)), width);
expr_a = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(TW::A)), width);
expr_b = stringf("resize(signed(%s), %d)", rvalue(cell->getPort(TW::B)), width);
}
else
{
expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::A)), width);
expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(ID::B)), width);
expr_a = stringf("resize(%s, %d)", rvalue(cell->getPort(TW::A)), width);
expr_b = stringf("resize(%s, %d)", rvalue(cell->getPort(TW::B)), width);
}
definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(ID::Y)),
expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(ID::Y))));
definitions.push_back(stringf("%s := resize(word1(%s %s %s), %d);", lvalue(cell->getPort(TW::Y)),
expr_a.c_str(), op.c_str(), expr_b.c_str(), GetSize(cell->getPort(TW::Y))));
continue;
}
if (cell->type.in(ID($reduce_and), ID($reduce_or), ID($reduce_bool)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_y = GetSize(cell->getPort(ID::Y));
const char *expr_a = rvalue(cell->getPort(ID::A));
const char *expr_y = lvalue(cell->getPort(ID::Y));
int width_a = GetSize(cell->getPort(TW::A));
int width_y = GetSize(cell->getPort(TW::Y));
const char *expr_a = rvalue(cell->getPort(TW::A));
const char *expr_y = lvalue(cell->getPort(TW::Y));
string expr;
if (cell->type == ID($reduce_and)) expr = stringf("%s = !0ub%d_0", expr_a, width_a);
@ -432,11 +432,11 @@ struct SmvWorker
if (cell->type.in(ID($reduce_xor), ID($reduce_xnor)))
{
int width_y = GetSize(cell->getPort(ID::Y));
const char *expr_y = lvalue(cell->getPort(ID::Y));
int width_y = GetSize(cell->getPort(TW::Y));
const char *expr_y = lvalue(cell->getPort(TW::Y));
string expr;
for (auto bit : cell->getPort(ID::A)) {
for (auto bit : cell->getPort(TW::A)) {
if (!expr.empty())
expr += " xor ";
expr += rvalue(bit);
@ -451,13 +451,13 @@ struct SmvWorker
if (cell->type.in(ID($logic_and), ID($logic_or)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_b = GetSize(cell->getPort(ID::B));
int width_y = GetSize(cell->getPort(ID::Y));
int width_a = GetSize(cell->getPort(TW::A));
int width_b = GetSize(cell->getPort(TW::B));
int width_y = GetSize(cell->getPort(TW::Y));
string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a);
string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(ID::B)), width_b);
const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr_a = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(TW::A)), width_a);
string expr_b = stringf("(%s != 0ub%d_0)", rvalue(cell->getPort(TW::B)), width_b);
const char *expr_y = lvalue(cell->getPort(TW::Y));
string expr;
if (cell->type == ID($logic_and)) expr = expr_a + " & " + expr_b;
@ -469,11 +469,11 @@ struct SmvWorker
if (cell->type.in(ID($logic_not)))
{
int width_a = GetSize(cell->getPort(ID::A));
int width_y = GetSize(cell->getPort(ID::Y));
int width_a = GetSize(cell->getPort(TW::A));
int width_y = GetSize(cell->getPort(TW::Y));
string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(ID::A)), width_a);
const char *expr_y = lvalue(cell->getPort(ID::Y));
string expr_a = stringf("(%s = 0ub%d_0)", rvalue(cell->getPort(TW::A)), width_a);
const char *expr_y = lvalue(cell->getPort(TW::Y));
definitions.push_back(stringf("%s := resize(word1(%s), %d);", expr_y, expr_a, width_y));
continue;
@ -481,31 +481,31 @@ struct SmvWorker
if (cell->type.in(ID($mux), ID($pmux)))
{
int width = GetSize(cell->getPort(ID::Y));
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_s = cell->getPort(ID::S);
int width = GetSize(cell->getPort(TW::Y));
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
SigSpec sig_s = cell->getPort(TW::S);
string expr;
for (int i = 0; i < GetSize(sig_s); i++)
expr += stringf("bool(%s) ? %s : ", rvalue(sig_s[i]), rvalue(sig_b.extract(i*width, width)));
expr += rvalue(sig_a);
definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(ID::Y)), expr));
definitions.push_back(stringf("%s := %s;", lvalue(cell->getPort(TW::Y)), expr));
continue;
}
if (cell->type == ID($dff))
{
vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(ID::Q)), GetSize(cell->getPort(ID::Q)), log_signal(cell->getPort(ID::Q))));
assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(ID::Q)), rvalue(cell->getPort(ID::D))));
vars.push_back(stringf("%s : unsigned word[%d]; -- %s", lvalue(cell->getPort(TW::Q)), GetSize(cell->getPort(TW::Q)), log_signal(cell->getPort(TW::Q))));
assignments.push_back(stringf("next(%s) := %s;", lvalue(cell->getPort(TW::Q)), rvalue(cell->getPort(TW::D))));
continue;
}
if (cell->type.in(ID($_BUF_), ID($_NOT_)))
{
string op = cell->type == ID($_NOT_) ? "!" : "";
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(ID::Y)), op, rvalue(cell->getPort(ID::A))));
definitions.push_back(stringf("%s := %s%s;", lvalue(cell->getPort(TW::Y)), op, rvalue(cell->getPort(TW::A))));
continue;
}
@ -519,57 +519,57 @@ struct SmvWorker
if (cell->type.in(ID($_XNOR_))) op = "xnor";
if (cell->type.in(ID($_ANDNOT_), ID($_ORNOT_)))
definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
definitions.push_back(stringf("%s := %s %s (!%s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
else
if (cell->type.in(ID($_NAND_), ID($_NOR_)))
definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
definitions.push_back(stringf("%s := !(%s %s %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
else
definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), op.c_str(), rvalue(cell->getPort(ID::B))));
definitions.push_back(stringf("%s := %s %s %s;", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), op.c_str(), rvalue(cell->getPort(TW::B))));
continue;
}
if (cell->type == ID($_MUX_))
{
definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
definitions.push_back(stringf("%s := bool(%s) ? %s : %s;", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A))));
continue;
}
if (cell->type == ID($_NMUX_))
{
definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::S)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::A))));
definitions.push_back(stringf("%s := !(bool(%s) ? %s : %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::S)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::A))));
continue;
}
if (cell->type == ID($_AOI3_))
{
definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C))));
definitions.push_back(stringf("%s := !((%s & %s) | %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C))));
continue;
}
if (cell->type == ID($_OAI3_))
{
definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C))));
definitions.push_back(stringf("%s := !((%s | %s) & %s);", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C))));
continue;
}
if (cell->type == ID($_AOI4_))
{
definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D))));
definitions.push_back(stringf("%s := !((%s & %s) | (%s & %s));", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D))));
continue;
}
if (cell->type == ID($_OAI4_))
{
definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(ID::Y)),
rvalue(cell->getPort(ID::A)), rvalue(cell->getPort(ID::B)), rvalue(cell->getPort(ID::C)), rvalue(cell->getPort(ID::D))));
definitions.push_back(stringf("%s := !((%s | %s) & (%s | %s));", lvalue(cell->getPort(TW::Y)),
rvalue(cell->getPort(TW::A)), rvalue(cell->getPort(TW::B)), rvalue(cell->getPort(TW::C)), rvalue(cell->getPort(TW::D))));
continue;
}

150
backends/verilog/verilog_backend.cc
View file

@ -991,7 +991,7 @@ std::string cellname(RTLIL::Cell *cell)
{
if (!norename && cell->name[0] == '$' && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_)))
{
RTLIL::SigSpec sig = cell->getPort(ID::Q);
RTLIL::SigSpec sig = cell->getPort(TW::Q);
if (GetSize(sig) != 1 || sig.is_fully_const())
goto no_special_reg_name;
@ -1026,7 +1026,7 @@ no_special_reg_name:
void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op)
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = %s ", op);
dump_attributes(f, "", cell->attributes, " ");
dump_cell_expr_port(f, cell, "A", true);
@ -1036,7 +1036,7 @@ void dump_cell_expr_uniop(std::ostream &f, std::string indent, RTLIL::Cell *cell
void dump_cell_expr_binop(std::ostream &f, std::string indent, RTLIL::Cell *cell, std::string op)
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" %s ", op);
@ -1100,7 +1100,7 @@ void dump_cell_expr_check(std::ostream &f, std::string indent, const RTLIL::Cell
f << stringf("%s" "%s" "cover (", indent, label);
else
log_abort();
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(");\n");
}
@ -1108,7 +1108,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{
if (cell->type == ID($_NOT_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
f << stringf("~");
dump_attributes(f, "", cell->attributes, " ");
@ -1118,9 +1118,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
}
if (cell->type.in(ID($_BUF_), ID($buf))) {
if (cell->type == ID($buf) && cell->getPort(ID::A).has_const(State::Sz)) {
RTLIL::SigSpec a = cell->getPort(ID::A);
RTLIL::SigSpec y = cell->getPort(ID::Y);
if (cell->type == ID($buf) && cell->getPort(TW::A).has_const(State::Sz)) {
RTLIL::SigSpec a = cell->getPort(TW::A);
RTLIL::SigSpec y = cell->getPort(TW::Y);
a.extend_u0(GetSize(y));
if (a.has_const(State::Sz)) {
@ -1146,7 +1146,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
return true;
}
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "A", false);
f << stringf(";\n");
@ -1155,7 +1155,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
if (cell->type.in(ID($_NAND_), ID($_NOR_), ID($_XNOR_)))
f << stringf("~(");
@ -1180,7 +1180,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($_MUX_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_cell_expr_port(f, cell, "S", false);
f << stringf(" ? ");
@ -1194,7 +1194,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($_NMUX_)) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = !(");
dump_cell_expr_port(f, cell, "S", false);
f << stringf(" ? ");
@ -1208,7 +1208,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.in(ID($_AOI3_), ID($_OAI3_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << (cell->type == ID($_AOI3_) ? " & " : " | ");
@ -1223,7 +1223,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.in(ID($_AOI4_), ID($_OAI4_))) {
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ~((");
dump_cell_expr_port(f, cell, "A", false);
f << (cell->type == ID($_AOI4_) ? " & " : " | ");
@ -1295,15 +1295,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// assign Y = $signed(_2_) / $signed(_1_);
if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) {
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
std::string buf_a = next_auto_id();
std::string buf_b = next_auto_id();
std::string buf_num = next_auto_id();
int size_a = GetSize(sig_a);
int size_b = GetSize(sig_b);
int size_y = GetSize(cell->getPort(ID::Y));
int size_y = GetSize(cell->getPort(TW::Y));
int size_max = std::max(size_a, std::max(size_b, size_y));
// intentionally one wider than maximum width
@ -1329,7 +1329,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = $signed(%s) / ", buf_num);
dump_attributes(f, "", cell->attributes, " ");
f << stringf("$signed(%s);\n", buf_b);
@ -1347,11 +1347,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
// assign Y = (A[-1] == B[-1]) || truncated == 0 ? $signed(truncated) : $signed(B) + $signed(truncated);
if (cell->getParam(ID::A_SIGNED).as_bool() && cell->getParam(ID::B_SIGNED).as_bool()) {
SigSpec sig_a = cell->getPort(ID::A);
SigSpec sig_b = cell->getPort(ID::B);
SigSpec sig_a = cell->getPort(TW::A);
SigSpec sig_b = cell->getPort(TW::B);
std::string temp_id = next_auto_id();
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(ID::A))-1, temp_id);
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(TW::A))-1, temp_id);
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" %% ");
dump_attributes(f, "", cell->attributes, " ");
@ -1359,7 +1359,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(";\n");
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = (");
dump_sigspec(f, sig_a.extract(sig_a.size()-1));
f << stringf(" == ");
@ -1378,7 +1378,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($shift))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
if (cell->getParam(ID::B_SIGNED).as_bool())
{
@ -1386,17 +1386,17 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf(" < 0 ? ");
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" << - ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(" : ");
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" >> ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
}
else
{
dump_cell_expr_port(f, cell, "A", true);
f << stringf(" >> ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
}
f << stringf(";\n");
return true;
@ -1405,16 +1405,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($shiftx))
{
std::string temp_id = next_auto_id();
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(ID::A))-1, temp_id);
dump_sigspec(f, cell->getPort(ID::A));
f << stringf("%s" "wire [%d:0] %s = ", indent, GetSize(cell->getPort(TW::A))-1, temp_id);
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(";\n");
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = %s[", temp_id);
if (cell->getParam(ID::B_SIGNED).as_bool())
f << stringf("$signed(");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
if (cell->getParam(ID::B_SIGNED).as_bool())
f << stringf(")");
f << stringf(" +: %d", cell->getParam(ID::Y_WIDTH).as_int());
@ -1425,14 +1425,14 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($mux))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_sigspec(f, cell->getPort(ID::S));
dump_sigspec(f, cell->getPort(TW::S));
f << stringf(" ? ");
dump_attributes(f, "", cell->attributes, " ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(" : ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(";\n");
return true;
}
@ -1440,7 +1440,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($pmux))
{
int width = cell->parameters[ID::WIDTH].as_int();
int s_width = cell->getPort(ID::S).size();
int s_width = cell->getPort(TW::S).size();
std::string func_name = cellname(cell);
f << stringf("%s" "function [%d:0] %s;\n", indent, width-1, func_name);
@ -1486,13 +1486,13 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "endfunction\n", indent);
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = %s(", func_name);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(", ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(", ");
dump_sigspec(f, cell->getPort(ID::S));
dump_sigspec(f, cell->getPort(TW::S));
f << stringf(");\n");
return true;
}
@ -1500,11 +1500,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($tribuf))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(" ? ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(" : %d'bz;\n", cell->parameters.at(ID::WIDTH).as_int());
return true;
}
@ -1512,9 +1512,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($slice))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(" >> %d;\n", cell->parameters.at(ID::OFFSET).as_int());
return true;
}
@ -1522,11 +1522,11 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($concat))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = { ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(" , ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(" };\n");
return true;
}
@ -1534,12 +1534,12 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($lut))
{
f << stringf("%s" "assign ", indent);
dump_sigspec(f, cell->getPort(ID::Y));
dump_sigspec(f, cell->getPort(TW::Y));
f << stringf(" = ");
dump_const(f, cell->parameters.at(ID::LUT));
f << stringf(" >> ");
dump_attributes(f, "", cell->attributes, " ");
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(";\n");
return true;
}
@ -1552,16 +1552,16 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
int width = cell->getParam(ID::WIDTH).as_int() ;
if (width == 1) {
f << stringf("%s" "tran(", indent);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(", ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(");\n");
} else {
auto tran_id = next_auto_id();
f << stringf("%s" "tran %s[%d:0](", indent, tran_id, width - 1);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(", ");
dump_sigspec(f, cell->getPort(ID::B));
dump_sigspec(f, cell->getPort(TW::B));
f << stringf(");\n");
}
return true;
@ -1794,9 +1794,9 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type.in(ID($assert), ID($assume), ID($cover)))
{
f << stringf("%s" "always%s if (", indent, systemverilog ? "_comb" : " @*");
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") %s(", cell->type.c_str()+1);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(");\n");
return true;
}
@ -1805,10 +1805,10 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
{
f << stringf("%s" "specify\n%s ", indent, indent);
SigSpec en = cell->getPort(ID::EN);
SigSpec en = cell->getPort(TW::EN);
if (en != State::S1) {
f << stringf("if (");
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") ");
}
@ -1816,7 +1816,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($specify3) && cell->getParam(ID::EDGE_EN).as_bool())
f << (cell->getParam(ID::EDGE_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort(ID::SRC));
dump_sigspec(f, cell->getPort(TW::SRC));
f << " ";
if (cell->getParam(ID::SRC_DST_PEN).as_bool())
@ -1825,15 +1825,15 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->type == ID($specify3)) {
f << "(";
dump_sigspec(f, cell->getPort(ID::DST));
dump_sigspec(f, cell->getPort(TW::DST));
f << " ";
if (cell->getParam(ID::DAT_DST_PEN).as_bool())
f << (cell->getParam(ID::DAT_DST_POL).as_bool() ? "+": "-");
f << ": ";
dump_sigspec(f, cell->getPort(ID::DAT));
dump_sigspec(f, cell->getPort(TW::DAT));
f << ")";
} else {
dump_sigspec(f, cell->getPort(ID::DST));
dump_sigspec(f, cell->getPort(TW::DST));
}
bool bak_decimal = decimal;
@ -1868,21 +1868,21 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (cell->getParam(ID::SRC_PEN).as_bool())
f << (cell->getParam(ID::SRC_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort(ID::SRC));
dump_sigspec(f, cell->getPort(TW::SRC));
if (cell->getPort(ID::SRC_EN) != State::S1) {
if (cell->getPort(TW::SRC_EN) != State::S1) {
f << " &&& ";
dump_sigspec(f, cell->getPort(ID::SRC_EN));
dump_sigspec(f, cell->getPort(TW::SRC_EN));
}
f << ", ";
if (cell->getParam(ID::DST_PEN).as_bool())
f << (cell->getParam(ID::DST_POL).as_bool() ? "posedge ": "negedge ");
dump_sigspec(f, cell->getPort(ID::DST));
dump_sigspec(f, cell->getPort(TW::DST));
if (cell->getPort(ID::DST_EN) != State::S1) {
if (cell->getPort(TW::DST_EN) != State::S1) {
f << " &&& ";
dump_sigspec(f, cell->getPort(ID::DST_EN));
dump_sigspec(f, cell->getPort(TW::DST_EN));
}
bool bak_decimal = decimal;
@ -1920,7 +1920,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "always @*\n", indent);
f << stringf("%s" " if (", indent);
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(")\n");
dump_cell_expr_print(f, indent + " ", cell);
@ -1936,7 +1936,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
f << stringf("%s" "always @*\n", indent);
f << stringf("%s" " if (", indent);
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") begin\n");
std::string flavor = cell->getParam(ID::FLAVOR).decode_string();
@ -1945,7 +1945,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
fmt.parse_rtlil(cell);
if (!fmt.parts.empty()) {
f << stringf("%s" " if (!", indent);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(")\n");
dump_cell_expr_print(f, indent + " ", cell);
}
@ -2047,7 +2047,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
if (siminit && cell->is_builtin_ff() && cell->hasPort(ID::Q) && !cell->type.in(ID($ff), ID($_FF_))) {
std::stringstream ss;
dump_reg_init(ss, cell->getPort(ID::Q));
dump_reg_init(ss, cell->getPort(TW::Q));
if (!ss.str().empty()) {
f << stringf("%sinitial %s.Q", indent, cell_name);
f << ss.str();
@ -2079,7 +2079,7 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec
});
for (auto cell : cells) {
f << stringf("%s" " if (", indent);
dump_sigspec(f, cell->getPort(ID::EN));
dump_sigspec(f, cell->getPort(TW::EN));
f << stringf(") begin\n");
if (cell->type == ID($print)) {
@ -2091,7 +2091,7 @@ void dump_sync_effect(std::ostream &f, std::string indent, const RTLIL::SigSpec
fmt.parse_rtlil(cell);
if (!fmt.parts.empty()) {
f << stringf("%s" " if (!", indent);
dump_sigspec(f, cell->getPort(ID::A));
dump_sigspec(f, cell->getPort(TW::A));
f << stringf(")\n");
dump_cell_expr_print(f, indent + " ", cell);
}
@ -2402,14 +2402,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (auto cell : module->cells())
{
if (cell->type.in(ID($print), ID($check)) && cell->getParam(ID::TRG_ENABLE).as_bool()) {
sync_effect_cells[make_pair(cell->getPort(ID::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell);
sync_effect_cells[make_pair(cell->getPort(TW::TRG), cell->getParam(ID::TRG_POLARITY))].push_back(cell);
continue;
}
if (!cell->is_builtin_ff() || !cell->hasPort(ID::Q) || cell->type.in(ID($ff), ID($_FF_)))
continue;
RTLIL::SigSpec sig = cell->getPort(ID::Q);
RTLIL::SigSpec sig = cell->getPort(TW::Q);
if (sig.is_chunk()) {
RTLIL::SigChunk chunk = sig.as_chunk();