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extract: signorm fix

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This commit is contained in:
Emil J. Tywoniak 2026-07-22 00:05:24 +02:00
parent aeb61402f6
commit f56d90c9c2
1 changed files with 6 additions and 11 deletions
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17
passes/techmap/extract.cc
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@ -184,6 +184,8 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
if (max_fanout > 0)
for (auto cell : mod->cells())
{
if (cell->type == TW($input_port))
continue;
if (!sel || sel->selected(mod, cell))
for (auto &conn : cell->connections()) {
RTLIL::SigSpec conn_sig = conn.second;
@ -199,6 +201,8 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
{
if (sel && !sel->selected(mod, cell))
continue;
if (cell->type == TW($input_port))
continue;
std::string type = cell->type.str();
if (sel == nullptr && type.compare(0, 2, "\\$") == 0)
@ -253,6 +257,8 @@ bool module2graph(SubCircuit::Graph &graph, RTLIL::Module *mod, bool constports,
// mark external signals (used in non-selected cells)
for (auto cell : mod->cells())
{
if (cell->type == TW($input_port))
continue;
if (sel && !sel->selected(mod, cell))
for (auto &conn : cell->connections())
{
@ -565,13 +571,6 @@ struct ExtractPass : public Pass {
}
extra_args(args, argidx, design);
// Subgraph isomorphism is over the cells as they stand, so the index's
// own marker cells would have to appear in both needle and haystack
// for a match: a needle input is a module port, hence an $input_port
// node, where the haystack has whatever actually drives the net.
// Nothing would ever match again.
design->sigNormalize(false);
if (!nodefaultswaps) {
solver.addSwappablePorts("$and", "\\A", "\\B");
solver.addSwappablePorts("$or", "\\A", "\\B");
@ -625,10 +624,6 @@ struct ExtractPass : public Pass {
if (filename.size() <= 3 || filename.compare(filename.size()-3, std::string::npos, ".il") != 0) {
Pass::call(map, "proc");
Pass::call(map, "opt_clean");
// Those leave the map design indexed, and the needles
// are built from its cells; see the note by the
// sigNormalize call on the haystack design above.
map->sigNormalize(false);
}
}
}