verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.

tests/verilog/signed_concat.ys

@@ -0,0 +1,7 @@
+read_verilog signed_concat.v
+hierarchy
+proc
+flatten gate
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert