verilog: indirect AST_CONCAT and AST_TO_UNSIGNED port connections

- AST_CONCAT and AST_TO_UNSIGNED are always unsigned, but may generate
  RTLIL that exclusively reference a signed wire.
- AST_CONCAT may also contain a memory write.

tests/simple/memwr_port_connection.sv

@@ -5,9 +5,11 @@ module producer(
 endmodule
 
 module top(
-    output logic [3:0] out
+    output logic [3:0] out0, out1
 );
-    logic [3:0] v[0:0];
-    producer p(v[0]);
-    assign out = v[0];
+    logic [3:0] v[1:0];
+    producer p0(v[0]);
+    producer p1({v[1]});
+    assign out0 = v[0];
+    assign out1 = v[1];
 endmodule