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quicklogic: PolarPro 3 support

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Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com>
Co-authored-by: Maciej Kurc <mkurc@antmicro.com>
Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com>
Co-authored-by: Lalit Sharma <lsharma@quicklogic.com>
Co-authored-by: kkumar23 <kkumar@quicklogic.com>
This commit is contained in:
Lofty 2021-03-17 02:34:30 +00:00 • committed by Marcelina Kościelnicka
parent 8740fdf1d7
commit f4298b057a
20 changed files with 1033 additions and 0 deletions
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53
techlibs/quicklogic/pp3_lut_map.v Normal file
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module \$lut (
A, Y
);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
LUT1 #(
.EQN(""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O(Y),
.I0(A[0])
);
end else if (WIDTH == 2) begin
LUT2 #(
.EQN(""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O(Y),
.I0(A[0]),
.I1(A[1])
);
end else if (WIDTH == 3) begin
LUT3 #(
.EQN(""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O(Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2])
);
end else if (WIDTH == 4) begin
LUT4 #(
.EQN(""),
.INIT(LUT)
) _TECHMAP_REPLACE_ (
.O(Y),
.I0(A[0]),
.I1(A[1]),
.I2(A[2]),
.I3(A[3])
);
end else begin
wire _TECHMAP_FAIL_ = 1;
end
endgenerate
endmodule