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https://github.com/YosysHQ/yosys
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f4298b057a
Co-authored-by: Grzegorz Latosiński <glatosinski@antmicro.com> Co-authored-by: Maciej Kurc <mkurc@antmicro.com> Co-authored-by: Tarachand Pagarani <tpagarani@quicklogic.com> Co-authored-by: Lalit Sharma <lsharma@quicklogic.com> Co-authored-by: kkumar23 <kkumar@quicklogic.com>
54 lines
928 B
Verilog
54 lines
928 B
Verilog
module \$lut (
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A, Y
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);
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parameter WIDTH = 0;
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parameter LUT = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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if (WIDTH == 1) begin
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LUT1 #(
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.EQN(""),
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.INIT(LUT)
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) _TECHMAP_REPLACE_ (
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.O(Y),
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.I0(A[0])
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);
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end else if (WIDTH == 2) begin
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LUT2 #(
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.EQN(""),
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.INIT(LUT)
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) _TECHMAP_REPLACE_ (
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.O(Y),
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.I0(A[0]),
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.I1(A[1])
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);
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end else if (WIDTH == 3) begin
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LUT3 #(
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.EQN(""),
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.INIT(LUT)
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) _TECHMAP_REPLACE_ (
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.O(Y),
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.I0(A[0]),
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.I1(A[1]),
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.I2(A[2])
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);
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end else if (WIDTH == 4) begin
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LUT4 #(
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.EQN(""),
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.INIT(LUT)
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) _TECHMAP_REPLACE_ (
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.O(Y),
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.I0(A[0]),
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.I1(A[1]),
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.I2(A[2]),
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.I3(A[3])
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);
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end else begin
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wire _TECHMAP_FAIL_ = 1;
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end
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endgenerate
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endmodule
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