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Merge remote-tracking branch 'origin/master' into xc7mux

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This commit is contained in:
Eddie Hung 2019-06-20 10:18:01 -07:00
commit f374e0ab7e
29 changed files with 236 additions and 47 deletions
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3
tests/aiger/.gitignore vendored
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@ -1,2 +1 @@
*.log
*.out
/*_ref.v

10
tests/aiger/run-test.sh
View file

@ -10,8 +10,9 @@ for aag in *.aag; do
# Since ABC cannot read *.aag, read the *.aig instead
# (which would have been created by the reference aig2aig utility,
# available from http://fmv.jku.at/aiger/)
../../yosys-abc -c "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
../../yosys -p "
echo "Checking $aag."
../../yosys-abc -q "read -c ${aag%.*}.aig; write ${aag%.*}_ref.v"
../../yosys -qp "
read_verilog ${aag%.*}_ref.v
prep
design -stash gold
@ -26,8 +27,9 @@ sat -verify -prove-asserts -show-ports -seq 16 miter
done
for aig in *.aig; do
../../yosys-abc -c "read -c $aig; write ${aig%.*}_ref.v"
../../yosys -p "
echo "Checking $aig."
../../yosys-abc -q "read -c $aig; write ${aig%.*}_ref.v"
../../yosys -qp "
read_verilog ${aig%.*}_ref.v
prep
design -stash gold

16
tests/simple/arrays02.sv Normal file
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@ -0,0 +1,16 @@
module uut_arrays02(clock, we, addr, wr_data, rd_data);
input clock, we;
input [3:0] addr, wr_data;
output [3:0] rd_data;
reg [3:0] rd_data;
reg [3:0] memory [16];
always @(posedge clock) begin
if (we)
memory[addr] <= wr_data;
rd_data <= memory[addr];
end
endmodule

22
tests/simple/defvalue.sv Normal file
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@ -0,0 +1,22 @@
module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2);
cnt #(1) foo (.clock, .cnt(cnt1), .delta);
cnt #(2) bar (.clock, .cnt(cnt2));
endmodule
module cnt #(
parameter integer initval = 0
) (
input clock,
output logic [3:0] cnt = initval,
`ifdef __ICARUS__
input [3:0] delta
`else
input [3:0] delta = 10
`endif
);
`ifdef __ICARUS__
assign (weak0, weak1) delta = 10;
`endif
always @(posedge clock)
cnt <= cnt + delta;
endmodule

29
tests/tools/autotest.sh
View file

@ -89,8 +89,7 @@ done
compile_and_run() {
exe="$1"; output="$2"; shift 2
ext=${1##*.}
if [ "$ext" == "sv" ]; then
if [ "${2##*.}" == "sv" ]; then
language_gen="-g2012"
else
language_gen="-g2005"
@ -142,23 +141,25 @@ do
cd ${bn}.out
fn=$(basename $fn)
bn=$(basename $bn)
refext=v
rm -f ${bn}_ref.fir
if [[ "$ext" == "v" ]]; then
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.${refext}"
else
cp ../${fn} ${bn}_ref.${ext}
refext=$ext
cp ../${fn} ${bn}_ref.${refext}
fi
if [ ! -f ../${bn}_tb.v ]; then
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.v
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext}
else
cp ../${bn}_tb.v ${bn}_tb.v
fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.${refext} $libs \
"$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
@ -175,25 +176,25 @@ do
test_count=$(( test_count + 1 ))
}
if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.v; then
if [ "$frontend" = "verific" -o "$frontend" = "verific_gates" ] && grep -q VERIFIC-SKIP ${bn}_ref.${refext}; then
touch ../${bn}.skip
return
fi
if [ -n "$scriptfiles" ]; then
test_passes -f "$frontend $include_opts" ${bn}_ref.v $scriptfiles
test_passes -f "$frontend $include_opts" ${bn}_ref.${refext} $scriptfiles
elif [ -n "$scriptopt" ]; then
test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.v
test_passes -f "$frontend $include_opts" -p "$scriptopt" ${bn}_ref.${refext}
elif [ "$frontend" = "verific" ]; then
test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -all; opt; memory;;"
test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -all; opt; memory;;"
elif [ "$frontend" = "verific_gates" ]; then
test_passes -p "verific -vlog2k ${bn}_ref.v; verific -import -gates -all; opt; memory;;"
test_passes -p "verific -vlog2k ${bn}_ref.${refext}; verific -import -gates -all; opt; memory;;"
else
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.v
test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.v
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.${refext}
test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext}
if [ -n "$firrtl2verilog" ]; then
if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then
"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.v
"$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep -nordff; proc; opt; memory; opt; fsm; opt -full -fine; pmuxtree" ${bn}_ref.${refext}
$firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v
test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt; memory; opt; fsm; opt -full -fine" ${bn}_ref.fir.v
fi

3
tests/various/.gitignore vendored
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@ -1 +1,2 @@
*.log
/*.log
/*.out