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Merge branch 'xaig' into xc7mux

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This commit is contained in:
Eddie Hung 2019-06-19 09:20:31 -07:00
commit 4e8f0fbce8
4 changed files with 9 additions and 21 deletions
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3
frontends/aiger/aigerparse.cc
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@ -22,9 +22,6 @@
// Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
// http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
#ifdef _WIN32
#include <libgen.h>
#endif
// https://stackoverflow.com/a/46137633
#ifdef _MSC_VER
#include <stdlib.h>

13
kernel/rtlil.cc
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@ -1565,21 +1565,14 @@ void RTLIL::Module::remove(const pool<RTLIL::Wire*> &wires)
void RTLIL::Module::remove(RTLIL::Cell *cell)
{
auto it = cells_.find(cell->name);
log_assert(it != cells_.end());
remove(it);
}
dict<RTLIL::IdString, RTLIL::Cell*>::iterator RTLIL::Module::remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it)
{
RTLIL::Cell *cell = it->second;
while (!cell->connections_.empty())
cell->unsetPort(cell->connections_.begin()->first);
auto it = cells_.find(cell->name);
log_assert(it != cells_.end());
log_assert(refcount_cells_ == 0);
it = cells_.erase(it);
cells_.erase(it);
delete cell;
return it;
}
void RTLIL::Module::rename(RTLIL::Wire *wire, RTLIL::IdString new_name)

1
kernel/rtlil.h
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@ -1040,7 +1040,6 @@ public:
// Removing wires is expensive. If you have to remove wires, remove them all at once.
void remove(const pool<RTLIL::Wire*> &wires);
void remove(RTLIL::Cell *cell);
dict<RTLIL::IdString, RTLIL::Cell*>::iterator remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it);
void rename(RTLIL::Wire *wire, RTLIL::IdString new_name);
void rename(RTLIL::Cell *cell, RTLIL::IdString new_name);

13
passes/techmap/abc9.cc
View file

@ -510,16 +510,15 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
vector<RTLIL::Cell*> boxes;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
RTLIL::Cell* cell = it->second;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) {
RTLIL::Cell *cell = it->second;
if (cell->type.in("$_AND_", "$_NOT_", "$__ABC_FF_")) {
it = module->remove(it);
module->remove(cell);
continue;
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id"))
boxes.emplace_back(it->second);
++it;
boxes.emplace_back(cell);
}
std::map<std::string, int> cell_stats;
@ -620,8 +619,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
}
}
for (auto cell : boxes)
module->remove(cell);
for (auto cell : boxes)
module->remove(cell);
// Copy connections (and rename) from mapped_mod to module
for (auto conn : mapped_mod->connections()) {