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ql_dsp: Add outer loop

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This commit is contained in:
Martin Povišer 2025-03-11 10:34:09 +01:00
parent fde681623c
commit f157a868a3
2 changed files with 25 additions and 16 deletions
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29
techlibs/quicklogic/ql_dsp.cc
View file

@ -70,6 +70,8 @@ bool promote(Module *m, Cell *cell) {
return true; return true;
} }
bool did_something;
#include "ql_dsp_pm.h" #include "ql_dsp_pm.h"
struct QlDspPass : Pass { struct QlDspPass : Pass {
@ -85,19 +87,24 @@ struct QlDspPass : Pass {
extra_args(args, argidx, d); extra_args(args, argidx, d);
for (auto module : d->selected_modules()) { for (auto module : d->selected_modules()) {
{ did_something = true;
ql_dsp_pm pm(module, module->selected_cells());
pm.run_ql_dsp_pack_regs();
}
while (did_something)
{ {
ql_dsp_pm pm(module, module->selected_cells()); // TODO: could be optimized by more reuse of the pmgen object
pm.run_ql_dsp_cascade(); did_something = false;
} {
ql_dsp_pm pm(module, module->selected_cells());
{ pm.run_ql_dsp_pack_regs();
ql_dsp_pm pm(module, module->selected_cells()); }
pm.run_ql_dsp_pack_regs(); {
ql_dsp_pm pm(module, module->selected_cells());
pm.run_ql_dsp_cascade();
}
{
ql_dsp_pm pm(module, module->selected_cells());
pm.run_ql_dsp_pack_regs();
}
} }
} }
} }

12
techlibs/quicklogic/ql_dsp.pmg
View file

@ -34,6 +34,7 @@ code argD clock_inferred clock reset
log("%s: inferring Z path register from flip-flop %s\n", log_id(dsp), log_id(dff)); log("%s: inferring Z path register from flip-flop %s\n", log_id(dsp), log_id(dff));
dsp->connections_[\output_select_i][2] = RTLIL::S1; dsp->connections_[\output_select_i][2] = RTLIL::S1;
dsp->setPort(\z_o, dffQ); dsp->setPort(\z_o, dffQ);
did_something = true;
} }
} }
endcode endcode
@ -52,6 +53,7 @@ code argQ clock_inferred clock reset
log("%s: inferring B path register from flip-flop %s\n", log_id(dsp), log_id(dff)); log("%s: inferring B path register from flip-flop %s\n", log_id(dsp), log_id(dff));
dsp->parameters[\B_REG] = true; dsp->parameters[\B_REG] = true;
dsp->setPort(\b_i, dffD); dsp->setPort(\b_i, dffD);
did_something = true;
} }
} }
endcode endcode
@ -70,6 +72,7 @@ code argQ clock_inferred clock reset
log("%s: inferring A path register from flip-flop %s\n", log_id(dsp), log_id(dff)); log("%s: inferring A path register from flip-flop %s\n", log_id(dsp), log_id(dff));
dsp->parameters[\A_REG] = true; dsp->parameters[\A_REG] = true;
dsp->setPort(\a_i, dffD); dsp->setPort(\a_i, dffD);
did_something = true;
} }
} }
endcode endcode
@ -236,9 +239,6 @@ match add
filter port(add, \B).extract(0, width) == port(dsp2, \z_o).extract(0, width) filter port(add, \B).extract(0, width) == port(dsp2, \z_o).extract(0, width)
endmatch endmatch
code
endcode
code code
const int z_width = 50; const int z_width = 50;
@ -265,7 +265,9 @@ code
dsp2->setParam(\SHIFT_REG, Const(0, 6)); dsp2->setParam(\SHIFT_REG, Const(0, 6));
dsp2->setParam(\SATURATE, Const(0, 1)); dsp2->setParam(\SATURATE, Const(0, 1));
dsp2->setParam(\ZCIN_REG, Const(1, 1)); dsp2->setParam(\ZCIN_REG, Const(1, 1));
dsp2->setPort(\z_o, {port(dsp2, \z_o).extract_end(port(add, \Y).size()), port(add, \Y)}); dsp2->setPort(\z_o, {port(dsp2, \z_o).extract_end(port(add, \Y).size()), port(add, \Y)});
module->remove(add);
did_something = true;
autoremove(add);
accept;
endcode endcode