From f157a868a329789dc0a017670309912ff48c2360 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Martin=20Povi=C5=A1er?= <povik@cutebit.org>
Date: Tue, 11 Mar 2025 10:34:09 +0100
Subject: [PATCH] ql_dsp: Add outer loop

---
 techlibs/quicklogic/ql_dsp.cc  | 29 ++++++++++++++++++-----------
 techlibs/quicklogic/ql_dsp.pmg | 12 +++++++-----
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/techlibs/quicklogic/ql_dsp.cc b/techlibs/quicklogic/ql_dsp.cc
index 8b53dffcb..760e76cf8 100644
--- a/techlibs/quicklogic/ql_dsp.cc
+++ b/techlibs/quicklogic/ql_dsp.cc
@@ -70,6 +70,8 @@ bool promote(Module *m, Cell *cell) {
 	return true;
 }
 
+bool did_something;
+
 #include "ql_dsp_pm.h"
 
 struct QlDspPass : Pass {
@@ -85,19 +87,24 @@ struct QlDspPass : Pass {
 		extra_args(args, argidx, d);
 
 		for (auto module : d->selected_modules()) {
-			{
-				ql_dsp_pm pm(module, module->selected_cells());
-				pm.run_ql_dsp_pack_regs();
-			}
+			did_something = true;
 
+			while (did_something)
 			{
-				ql_dsp_pm pm(module, module->selected_cells());
-				pm.run_ql_dsp_cascade();
-			}
-
-			{
-				ql_dsp_pm pm(module, module->selected_cells());
-				pm.run_ql_dsp_pack_regs();
+				// TODO: could be optimized by more reuse of the pmgen object
+				did_something = false;
+				{
+					ql_dsp_pm pm(module, module->selected_cells());
+					pm.run_ql_dsp_pack_regs();
+				}
+				{
+					ql_dsp_pm pm(module, module->selected_cells());
+					pm.run_ql_dsp_cascade();
+				}
+				{
+					ql_dsp_pm pm(module, module->selected_cells());
+					pm.run_ql_dsp_pack_regs();
+				}
 			}
 		}
 	}
diff --git a/techlibs/quicklogic/ql_dsp.pmg b/techlibs/quicklogic/ql_dsp.pmg
index 44c2377d0..1dc1907b7 100644
--- a/techlibs/quicklogic/ql_dsp.pmg
+++ b/techlibs/quicklogic/ql_dsp.pmg
@@ -34,6 +34,7 @@ code argD clock_inferred clock reset
 			log("%s: inferring Z path register from flip-flop %s\n", log_id(dsp), log_id(dff));
 			dsp->connections_[\output_select_i][2] = RTLIL::S1;
 			dsp->setPort(\z_o, dffQ);
+			did_something = true;
 		}
 	}
 endcode
@@ -52,6 +53,7 @@ code argQ clock_inferred clock reset
 			log("%s: inferring B path register from flip-flop %s\n", log_id(dsp), log_id(dff));
 			dsp->parameters[\B_REG] = true;
 			dsp->setPort(\b_i, dffD);
+			did_something = true;
 		}
 	}
 endcode
@@ -70,6 +72,7 @@ code argQ clock_inferred clock reset
 			log("%s: inferring A path register from flip-flop %s\n", log_id(dsp), log_id(dff));
 			dsp->parameters[\A_REG] = true;
 			dsp->setPort(\a_i, dffD);
+			did_something = true;
 		}
 	}
 endcode
@@ -236,9 +239,6 @@ match add
 	filter port(add, \B).extract(0, width) == port(dsp2, \z_o).extract(0, width)
 endmatch
 
-code
-endcode
-
 code
 	const int z_width = 50;
 
@@ -265,7 +265,9 @@ code
 	dsp2->setParam(\SHIFT_REG, Const(0, 6));
 	dsp2->setParam(\SATURATE, Const(0, 1));
 	dsp2->setParam(\ZCIN_REG, Const(1, 1));
-
 	dsp2->setPort(\z_o, {port(dsp2, \z_o).extract_end(port(add, \Y).size()), port(add, \Y)});
-	module->remove(add);
+
+	did_something = true;
+	autoremove(add);
+	accept;
 endcode