mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-12-20 19:23:45 +00:00
Code Activity

Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order

Browse source 
cellaigs: fix function argument evaluation order
This commit is contained in:
Emil J 2025-12-12 10:00:09 +01:00 • committed by GitHub
commit f003eca615
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
45 changed files with 820 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

24
passes/tests/test_cell.cc
View file

@ -1143,7 +1143,29 @@ struct TestCellPass : public Pass {
else
uut = create_gold_module(design, cell_type, cell_types.at(cell_type), constmode, muxdiv);
if (!write_prefix.empty()) {
Pass::call(design, stringf("write_rtlil %s_%s_%05d.il", write_prefix, cell_type.c_str()+1, i));
string writer = "write_rtlil";
string suffix = "il";
if (techmap_cmd.compare("aigmap") == 0) {
// try to convert to aiger
Pass::call(design, techmap_cmd);
bool is_unconverted = false;
for (auto *mod : design->selected_modules())
for (auto *cell : mod->selected_cells())
if (!cell->type.in(ID::$_NOT_, ID::$_AND_)) {
is_unconverted = true;
break;
}
if (is_unconverted) {
// skip unconverted cells
log_warning("Skipping %s\n", cell_type);
delete design;
break;
} else {
writer = "write_aiger -ascii";
suffix = "aag";
}
}
Pass::call(design, stringf("%s %s_%s_%05d.%s", writer, write_prefix, cell_type.c_str()+1, i, suffix));
} else if (edges) {
Pass::call(design, "dump gold");
run_edges_test(design, verbose);