mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-07-20 14:15:49 +00:00
Code Activity

techlibs: fix twines

Browse source
This commit is contained in:
Emil J. Tywoniak 2026-06-23 16:00:19 +02:00
parent ffde59d21e
commit ecfced8f0d
4 changed files with 9 additions and 9 deletions
Download patch file Download diff file Expand all files Collapse all files

2
techlibs/quicklogic/ql_dsp_io_regs.cc
View file

@ -88,7 +88,7 @@ struct QlDspIORegs : public Pass {
int out_sel_i = sigmap(cell->getPort(TW::output_select)).as_int();
// Get the feedback port
if (!cell->hasPort(TW(feedback)))
if (!cell->hasPort(TW::feedback))
log_error("Missing 'feedback' port on %s", cell);
SigSpec feedback = sigmap(cell->getPort(TW::feedback));

4
techlibs/quicklogic/ql_dsp_macc.cc
View file

@ -113,7 +113,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
RTLIL::SigSpec rst;
RTLIL::SigSpec ena;
if (st.ff->hasPort(TW(ARST))) {
if (st.ff->hasPort(TW::ARST)) {
if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
rst = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::ARST));
} else {
@ -123,7 +123,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
rst = RTLIL::SigSpec(RTLIL::S0);
}
if (st.ff->hasPort(TW(EN))) {
if (st.ff->hasPort(TW::EN)) {
if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
ena = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::EN));
} else {