diff --git a/techlibs/coolrunner2/coolrunner2_sop.cc b/techlibs/coolrunner2/coolrunner2_sop.cc
index 539a9d38e..298ecefd8 100644
--- a/techlibs/coolrunner2/coolrunner2_sop.cc
+++ b/techlibs/coolrunner2/coolrunner2_sop.cc
@@ -63,13 +63,13 @@ struct Coolrunner2SopPass : public Pass {
 				if (cell->type.in(ID(FDCP), ID(FDCP_N), ID(FDDCP), ID(FTCP), ID(FTCP_N), ID(FTDCP),
 							ID(FDCPE), ID(FDCPE_N), ID(FDDCPE), ID(LDCP), ID(LDCP_N)))
 				{
-					if (cell->hasPort(TW(PRE)))
+					if (cell->hasPort(TW::PRE))
 						special_pterms_no_inv[sigmap(cell->getPort(TW::PRE)[0])].insert(
 							make_tuple(cell, ID(PRE)));
 					if (cell->hasPort(TW::CLR))
 						special_pterms_no_inv[sigmap(cell->getPort(TW::CLR)[0])].insert(
 							make_tuple(cell, ID::CLR));
-					if (cell->hasPort(TW(CE)))
+					if (cell->hasPort(TW::CE))
 						special_pterms_no_inv[sigmap(cell->getPort(TW::CE)[0])].insert(
 							make_tuple(cell, ID(CE)));
 
diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index b49ff4af9..4c91120a5 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -39,7 +39,7 @@ static void nx_carry_chain(Module *module)
 	{
 		if (cell->type == ID(NX_CY_1BIT)) {
 			if (cell->getParam(ID(first)).as_int() == 1) continue;
-			if (!cell->hasPort(TW(CI)))
+			if (!cell->hasPort(TW::CI))
 				log_error("Not able to find connected carry.\n");
 			SigBit ci = sigmap(cell->getPort(TW::CI).as_bit());
 			carry[ci] = cell;
@@ -65,7 +65,7 @@ static void nx_carry_chain(Module *module)
 					//log_error("Not able to find connected carry.\n");
 				current = carry[co];
 				chain.push_back(current);
-				if (!current->hasPort(TW(CO))) break;
+				if (!current->hasPort(TW::CO)) break;
 				co = sigmap(current->getPort(TW::CO).as_bit());
 			}
 			carry_chains[cell] = chain;
@@ -117,7 +117,7 @@ static void nx_carry_chain(Module *module)
 					cell->setPort(TW::B1, State::S0);
 					j = 1;
 				} else {
-					if (c.second.at(i)->hasPort(TW(CO)))
+					if (c.second.at(i)->hasPort(TW::CO))
 						cell->setPort(TW::CO, c.second.at(i)->getPort(TW::CO));
 				}
 				cnt++;
@@ -125,7 +125,7 @@ static void nx_carry_chain(Module *module)
 			cell->setPort(names_A[j], get_bit_or_zero(c.second.at(i)->getPort(TW::A)));
 			cell->setPort(names_B[j], get_bit_or_zero(c.second.at(i)->getPort(TW::B)));
 			
-			if (c.second.at(i)->hasPort(TW(S))) 
+			if (c.second.at(i)->hasPort(TW::S)) 
 				cell->setPort(names_S[j], c.second.at(i)->getPort(TW::S));
 
 			j = (j + 1) % 4;
diff --git a/techlibs/quicklogic/ql_dsp_io_regs.cc b/techlibs/quicklogic/ql_dsp_io_regs.cc
index 23fa93a82..b27e0962d 100644
--- a/techlibs/quicklogic/ql_dsp_io_regs.cc
+++ b/techlibs/quicklogic/ql_dsp_io_regs.cc
@@ -88,7 +88,7 @@ struct QlDspIORegs : public Pass {
 			int out_sel_i = sigmap(cell->getPort(TW::output_select)).as_int();
 
 			// Get the feedback port
-			if (!cell->hasPort(TW(feedback)))
+			if (!cell->hasPort(TW::feedback))
 				log_error("Missing 'feedback' port on %s", cell);
 			SigSpec feedback = sigmap(cell->getPort(TW::feedback));
 
diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc
index 3a967ea5c..6da0a3bed 100644
--- a/techlibs/quicklogic/ql_dsp_macc.cc
+++ b/techlibs/quicklogic/ql_dsp_macc.cc
@@ -113,7 +113,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
     RTLIL::SigSpec rst;
     RTLIL::SigSpec ena;
 
-    if (st.ff->hasPort(TW(ARST))) {
+    if (st.ff->hasPort(TW::ARST)) {
         if (st.ff->getParam(ID(ARST_POLARITY)).as_int() != 1) {
             rst = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::ARST));
         } else {
@@ -123,7 +123,7 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
         rst = RTLIL::SigSpec(RTLIL::S0);
     }
 
-    if (st.ff->hasPort(TW(EN))) {
+    if (st.ff->hasPort(TW::EN)) {
         if (st.ff->getParam(ID(EN_POLARITY)).as_int() != 1) {
             ena = pm.module->Not(NEW_TWINE, st.ff->getPort(TW::EN));
         } else {