mirror of
				https://github.com/YosysHQ/yosys
				synced 2025-10-31 03:32:29 +00:00 
			
		
		
		
	Fix indentation
This commit is contained in:
		
							parent
							
								
									6ac315d65f
								
							
						
					
					
						commit
						ebef91880d
					
				
					 1 changed files with 2 additions and 2 deletions
				
			
		|  | @ -947,8 +947,8 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, co | |||
| 	} | ||||
| 
 | ||||
| 	for (auto cell : module->cells()) | ||||
| 	for (auto &port_it : cell->connections()) | ||||
| 		mark_port(port_it.second); | ||||
| 		for (auto &port_it : cell->connections()) | ||||
| 			mark_port(port_it.second); | ||||
| 
 | ||||
| 	if (clk_sig.size() != 0) | ||||
| 		mark_port(clk_sig); | ||||
|  |  | |||
		Loading…
	
	Add table
		Add a link
		
	
		Reference in a new issue