mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-08-23 19:47:55 +00:00
Code Activity

Fix indentation

Browse source
This commit is contained in:
Robert O'Callahan 2025-07-15 04:19:09 +00:00
parent 6ac315d65f
commit ebef91880d
1 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

4
passes/techmap/abc.cc
View file

@ -947,8 +947,8 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, co
}
for (auto cell : module->cells())
for (auto &port_it : cell->connections())
mark_port(port_it.second);
for (auto &port_it : cell->connections())
mark_port(port_it.second);
if (clk_sig.size() != 0)
mark_port(clk_sig);