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https://github.com/YosysHQ/yosys
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Make module
a parameter of the function so we can change its constness in context
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parent
2a9d37fb12
commit
6ac315d65f
1 changed files with 12 additions and 14 deletions
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@ -143,7 +143,6 @@ struct AbcModuleState {
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int map_autoidx = 0;
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SigMap assign_map;
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RTLIL::Module *module = nullptr;
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std::vector<gate_t> signal_list;
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dict<RTLIL::SigBit, int> signal_map;
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FfInitVals initvals;
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@ -165,13 +164,13 @@ struct AbcModuleState {
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int map_signal(RTLIL::SigBit bit, gate_type_t gate_type = G(NONE), int in1 = -1, int in2 = -1, int in3 = -1, int in4 = -1);
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void mark_port(RTLIL::SigSpec sig);
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void extract_cell(RTLIL::Cell *cell, bool keepff);
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void extract_cell(RTLIL::Module *module, RTLIL::Cell *cell, bool keepff);
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std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr);
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void dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edges, pool<int> &workpool, std::vector<int> &in_counts);
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void handle_loops();
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void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, const std::vector<RTLIL::Cell*> &cells,
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void handle_loops(RTLIL::Module *module);
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void abc_module(RTLIL::Design *design, RTLIL::Module *module, const std::vector<RTLIL::Cell*> &cells,
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bool dff_mode, std::string clk_str);
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void extract(RTLIL::Design *design);
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void extract(RTLIL::Design *design, RTLIL::Module *module);
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void finish();
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};
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@ -220,7 +219,7 @@ void AbcModuleState::mark_port(RTLIL::SigSpec sig)
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signal_list[signal_map[bit]].is_port = true;
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}
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void AbcModuleState::extract_cell(RTLIL::Cell *cell, bool keepff)
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void AbcModuleState::extract_cell(RTLIL::Module *module, RTLIL::Cell *cell, bool keepff)
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{
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if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
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FfData ff(&initvals, cell);
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@ -491,7 +490,7 @@ void AbcModuleState::dump_loop_graph(FILE *f, int &nr, dict<int, pool<int>> &edg
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fprintf(f, "}\n");
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}
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void AbcModuleState::handle_loops()
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void AbcModuleState::handle_loops(RTLIL::Module *module)
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{
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// http://en.wikipedia.org/wiki/Topological_sorting
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// (Kahn, Arthur B. (1962), "Topological sorting of large networks")
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@ -751,10 +750,9 @@ struct abc_output_filter
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}
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};
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void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_module, const std::vector<RTLIL::Cell*> &cells,
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void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *module, const std::vector<RTLIL::Cell*> &cells,
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bool dff_mode, std::string clk_str)
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{
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module = current_module;
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initvals.set(&assign_map, module);
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map_autoidx = autoidx++;
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@ -938,7 +936,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
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had_init = false;
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for (auto c : cells)
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extract_cell(c, config.keepff);
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extract_cell(module, c, config.keepff);
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if (undef_bits_lost)
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log("Replacing %d occurrences of constant undef bits with constant zero bits\n", undef_bits_lost);
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@ -964,7 +962,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
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if (srst_sig.size() != 0)
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mark_port(srst_sig);
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handle_loops();
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handle_loops(module);
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buffer = stringf("%s/input.blif", tempdir_name.c_str());
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f = fopen(buffer.c_str(), "wt");
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@ -1207,7 +1205,7 @@ void AbcModuleState::abc_module(RTLIL::Design *design, RTLIL::Module *current_mo
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log("Don't call ABC as there is nothing to map.\n");
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}
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void AbcModuleState::extract(RTLIL::Design *design)
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void AbcModuleState::extract(RTLIL::Design *design, RTLIL::Module *module)
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{
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if (!did_run_abc) {
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return;
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@ -2087,7 +2085,7 @@ struct AbcPass : public Pass {
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AbcModuleState state(config);
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state.assign_map.set(mod);
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state.abc_module(design, mod, mod->selected_cells(), dff_mode, clk_str);
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state.extract(design);
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state.extract(design, mod);
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state.finish();
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continue;
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}
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@ -2256,7 +2254,7 @@ struct AbcPass : public Pass {
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state.srst_polarity = std::get<6>(it.first);
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state.srst_sig = assign_map(std::get<7>(it.first));
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state.abc_module(design, mod, it.second, !state.clk_sig.empty(), "$");
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state.extract(design);
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state.extract(design, mod);
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state.finish();
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}
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}
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