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This commit is contained in:
Akash Levy 2024-07-18 17:27:36 -07:00
commit 2c4849805a
5 changed files with 23 additions and 17 deletions
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2
.gitcommit
View file

@ -1 +1 @@
$Format:%h$
$Format:%H$

9
Makefile
View file

@ -147,14 +147,14 @@ ifeq ($(OS), Haiku)
CXXFLAGS += -D_DEFAULT_SOURCE
endif
YOSYS_VER := 0.43+11
YOSYS_VER := 0.43+22
# Note: We arrange for .gitcommit to contain the (short) commit hash in
# tarballs generated with git-archive(1) using .gitattributes. The git repo
# will have this file in its unexpanded form tough, in which case we fall
# back to calling git directly.
TARBALL_GIT_REV := $(shell cat $(YOSYS_SRC)/.gitcommit)
ifeq ($(TARBALL_GIT_REV),$$Format:%h$$)
ifneq ($(findstring Format:,$(TARBALL_GIT_REV)),)
GIT_REV := $(shell GIT_DIR=$(YOSYS_SRC)/.git git rev-parse --short=9 HEAD || echo UNKNOWN)
else
GIT_REV := $(TARBALL_GIT_REV)
@ -585,6 +585,7 @@ S =
endif
$(eval $(call add_include_file,kernel/binding.h))
$(eval $(call add_include_file,kernel/bitpattern.h))
$(eval $(call add_include_file,kernel/cellaigs.h))
$(eval $(call add_include_file,kernel/celledges.h))
$(eval $(call add_include_file,kernel/celltypes.h))
@ -784,10 +785,10 @@ check-git-abc:
exit 1; \
elif git -C "$(YOSYS_SRC)" submodule status abc 2>/dev/null | grep -q '^ '; then \
exit 0; \
elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && ! grep -q '\$$Format:%[hH]\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
echo "'abc' comes from a tarball. Continuing."; \
exit 0; \
elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%h\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
elif [ -f "$(YOSYS_SRC)/abc/.gitcommit" ] && grep -q '\$$Format:%[hH]\$$' "$(YOSYS_SRC)/abc/.gitcommit"; then \
echo "Error: 'abc' is not configured as a git submodule."; \
echo "To resolve this:"; \
echo "1. Back up your changes: Save any modifications from the 'abc' directory to another location."; \

17
techlibs/gowin/cells_sim.v
View file

@ -867,8 +867,12 @@ module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
parameter INIT = 0;
endmodule
(* blackbox, keep *)
module GSR (input GSRI);
wire GSRO = GSRI;
endmodule
(* blackbox, keep *)
module BANDGAP (input BGEN);
endmodule
(* abc9_box, lib_whitebox *)
@ -1901,3 +1905,14 @@ output OSCOUT;
parameter FREQ_DIV = 100;
parameter REGULATOR_EN = 1'b0;
endmodule
(* blackbox *)
module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
parameter DCS_MODE = "RISING";
endmodule

2
techlibs/gowin/cells_xtra.py
View file

@ -13,7 +13,7 @@ class State(Enum):
IN_MODULE = auto()
IN_PARAMETER = auto()
_skip = { 'ALU', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
_skip = { 'ALU', 'BANDGAP', 'DFF', 'DFFC', 'DFFCE', 'DFFE', 'DFFN', 'DFFNC', 'DFFNCE',
'DFFNE', 'DFFNP', 'DFFNPE', 'DFFNR', 'DFFNRE', 'DFFNS', 'DFFNSE',
'DFFP', 'DFFPE', 'DFFR', 'DFFRE', 'DFFS', 'DFFSE', 'DP', 'DPX9',
'ELVDS_OBUF', 'GND', 'GSR', 'IBUF', 'IDDR', 'IDDRC', 'IDES10',

10
techlibs/gowin/cells_xtra.v
View file

@ -1564,12 +1564,6 @@ parameter IDLE = 4'd0,
RD_S2 = 4'd12;
endmodule
module DCS (...);
input CLK0, CLK1, CLK2, CLK3, SELFORCE;
input [3:0] CLKSEL;
output CLKOUT;
endmodule
module DQCE (...);
input CLKIN;
input CE;
@ -1687,10 +1681,6 @@ endmodule
module ADC (...);
endmodule
module BANDGAP (...);
input BGEN;
endmodule
module CLKDIV2 (...);
parameter GSREN = "false";
input HCLKIN, RESETN;