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test_cell: Add $bweqx, kinda

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It fails in sat, and in `ConstEval::eval()`.  But it's pseudo supported in test_cell at least.

Also fix `RTLIL::Cell::fixup_parameters()` for $bweqx.
This commit is contained in:
Krystine Sherwin 2025-03-31 16:39:13 +13:00
parent 1a3f6c9d50
commit eb5abf9c12
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2 changed files with 11 additions and 6 deletions
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2
kernel/rtlil.cc
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@ -4063,7 +4063,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:")) type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
return; return;
if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux) || type == ID($bwmux)) { if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux) || type == ID($bwmux) || type == ID($bweqx)) {
parameters[ID::WIDTH] = GetSize(connections_[ID::Y]); parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
if (type.in(ID($pmux), ID($bmux))) if (type.in(ID($pmux), ID($bmux)))
parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]); parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);

15
passes/tests/test_cell.cc
View file

@ -429,17 +429,20 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
cell->setPort(ID::Y, wire); cell->setPort(ID::Y, wire);
} }
if (cell_type == ID($bwmux)) if (cell_type.in(ID($bwmux), ID($bweqx)))
{ {
int a_size = GetSize(cell->getPort(ID::A)); int a_size = GetSize(cell->getPort(ID::A));
wire = module->addWire(ID::B); wire = module->addWire(ID::B);
wire->width = a_size; wire->width = a_size;
wire->port_output = true; wire->port_output = true;
cell->setPort(ID::B, wire); cell->setPort(ID::B, wire);
wire = module->addWire(ID::S); if (cell_type == ID($bwmux))
wire->width = a_size; {
wire->port_output = true; wire = module->addWire(ID::S);
cell->setPort(ID::S, wire); wire->width = a_size;
wire->port_output = true;
cell->setPort(ID::S, wire);
}
wire = module->addWire(ID::Y); wire = module->addWire(ID::Y);
wire->width = a_size; wire->width = a_size;
wire->port_output = true; wire->port_output = true;
@ -1112,6 +1115,8 @@ struct TestCellPass : public Pass {
cell_types[ID($pmux)] = "*"; cell_types[ID($pmux)] = "*";
if (noeval) if (noeval)
cell_types[ID($bwmux)] = "A"; cell_types[ID($bwmux)] = "A";
if (nosat && noeval)
cell_types[ID($bweqx)] = "A";
cell_types[ID($slice)] = "A"; cell_types[ID($slice)] = "A";
cell_types[ID($concat)] = "AB"; cell_types[ID($concat)] = "AB";