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test_cell: Support more cell types
Still unsupported: - x-prop cells ($eqx, $nex, $bweqx) - wide muxes (`$_MUX16_` and friends) - $pmux Partially supported: - $bwmux is not supported in `ConstEval::eval()`, works with `-noeval` - $buf has no mapping in techmap.v so is unusable with `techmap -assert` (i.e. the default) - $pow has `_TECHMAP_FAIL_` in techmap.v, `-simlib` works for some iterations but fails for others, `-aigmap` works fine Fix `CellTypes::eval() for `$_NMUX_`. Fix `RTLIL::Cell::fixup_parameters()` for $concat and $bwmux.
This commit is contained in:
Krystine Sherwin
parent
833721bfc4
commit
1a3f6c9d50
3 changed files with 140 additions and 14 deletions
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@ -589,6 +589,8 @@ struct CellTypes
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{
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if (cell->type.in(ID($mux), ID($_MUX_)))
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return const_mux(arg1, arg2, arg3);
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if (cell->type == ID($_NMUX_))
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return eval_not(const_mux(arg1, arg2, arg3));
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if (cell->type == ID($bwmux))
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return const_bwmux(arg1, arg2, arg3);
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if (cell->type == ID($pmux))
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@ -4063,9 +4063,9 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
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type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
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return;
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if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux)) {
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if (type == ID($buf) || type == ID($mux) || type == ID($pmux) || type == ID($bmux) || type == ID($bwmux)) {
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parameters[ID::WIDTH] = GetSize(connections_[ID::Y]);
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if (type != ID($buf) && type != ID($mux))
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if (type.in(ID($pmux), ID($bmux)))
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parameters[ID::S_WIDTH] = GetSize(connections_[ID::S]);
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check();
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return;
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@ -4115,7 +4115,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
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parameters[ID::B_WIDTH] = GetSize(connections_[ID::B]);
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}
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if (connections_.count(ID::Y))
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if (connections_.count(ID::Y) && type != ID($concat))
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parameters[ID::Y_WIDTH] = GetSize(connections_[ID::Y]);
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if (connections_.count(ID::Q))
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@ -72,6 +72,29 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(ID::Y, wire);
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}
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if (cell_type.in(ID($_MUX_), ID($_NMUX_)))
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{
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wire = module->addWire(ID::A);
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wire->width = 1;
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wire->port_input = true;
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cell->setPort(ID::A, wire);
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wire = module->addWire(ID::B);
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wire->width = 1;
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wire->port_input = true;
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cell->setPort(ID::B, wire);
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wire = module->addWire(ID::S);
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wire->width = 1;
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wire->port_input = true;
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cell->setPort(ID::S, wire);
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wire = module->addWire(ID::Y);
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wire->width = 1;
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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}
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if (cell_type == ID($bmux))
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{
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int width = 1 + xorshift32(8 * bloat_factor);
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@ -274,14 +297,19 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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if (cell_type_flags.find('A') != std::string::npos) {
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wire = module->addWire(ID::A);
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wire->width = 1 + xorshift32(8 * bloat_factor);
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if (cell_type_flags.find('b') != std::string::npos)
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wire->width = 1;
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else
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wire->width = 1 + xorshift32(8 * bloat_factor);
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wire->port_input = true;
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cell->setPort(ID::A, wire);
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}
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if (cell_type_flags.find('B') != std::string::npos) {
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wire = module->addWire(ID::B);
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if (cell_type_flags.find('h') != std::string::npos)
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if (cell_type_flags.find('b') != std::string::npos)
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wire->width = 1;
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else if (cell_type_flags.find('h') != std::string::npos)
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wire->width = 1 + xorshift32(6 * bloat_factor);
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else
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wire->width = 1 + xorshift32(8 * bloat_factor);
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@ -289,6 +317,26 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(ID::B, wire);
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}
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if (cell_type_flags.find('C') != std::string::npos) {
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wire = module->addWire(ID::C);
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if (cell_type_flags.find('b') != std::string::npos)
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wire->width = 1;
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else
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wire->width = 1 + xorshift32(8 * bloat_factor);
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wire->port_input = true;
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cell->setPort(ID::C, wire);
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}
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if (cell_type_flags.find('D') != std::string::npos) {
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wire = module->addWire(ID::D);
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if (cell_type_flags.find('b') != std::string::npos)
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wire->width = 1;
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else
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wire->width = 1 + xorshift32(8 * bloat_factor);
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wire->port_input = true;
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cell->setPort(ID::D, wire);
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}
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if (cell_type_flags.find('S') != std::string::npos && xorshift32(2)) {
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if (cell_type_flags.find('A') != std::string::npos)
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cell->parameters[ID::A_SIGNED] = true;
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@ -305,7 +353,10 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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if (cell_type_flags.find('Y') != std::string::npos) {
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wire = module->addWire(ID::Y);
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wire->width = 1 + xorshift32(8 * bloat_factor);
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if (cell_type_flags.find('b') != std::string::npos)
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wire->width = 1;
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else
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wire->width = 1 + xorshift32(8 * bloat_factor);
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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}
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@ -346,6 +397,55 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
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cell->setPort(ID::CO, wire);
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}
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if (cell_type == ID($slice))
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{
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int a_size = GetSize(cell->getPort(ID::A));
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int y_size = 1;
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if (a_size > 1)
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y_size += (xorshift32(8 * bloat_factor) % (a_size - 1));
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wire = module->addWire(ID::Y);
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wire->width = y_size;
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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if (a_size > y_size)
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cell->setParam(ID::OFFSET, (xorshift32(8 * bloat_factor) % (a_size - y_size)));
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else
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cell->setParam(ID::OFFSET, 0);
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}
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if (cell_type == ID($concat))
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{
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wire = module->addWire(ID::Y);
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wire->width = GetSize(cell->getPort(ID::A)) + GetSize(cell->getPort(ID::B));
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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}
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if (cell_type == ID($buf))
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{
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wire = module->addWire(ID::Y);
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wire->width = GetSize(cell->getPort(ID::A));
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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}
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if (cell_type == ID($bwmux))
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{
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int a_size = GetSize(cell->getPort(ID::A));
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wire = module->addWire(ID::B);
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wire->width = a_size;
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wire->port_output = true;
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cell->setPort(ID::B, wire);
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wire = module->addWire(ID::S);
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wire->width = a_size;
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wire->port_output = true;
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cell->setPort(ID::S, wire);
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wire = module->addWire(ID::Y);
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wire->width = a_size;
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wire->port_output = true;
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cell->setPort(ID::Y, wire);
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}
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if (constmode)
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{
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auto conn_list = cell->connections();
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@ -650,9 +750,9 @@ static void run_eval_test(RTLIL::Design *design, const CellType *ct, bool verbos
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// Simple (A -> Y) and (A,B -> Y) cells
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if (has_a && !has_c && !has_d && !has_s && !has_x && has_y)
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result = CellTypes::eval(cell, in_map[ID::A], in_map[ID::B], &err);
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// (A,B,C -> Y) cells
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else if (has_a && has_b && has_c && !has_d && !has_s && !has_x && has_y)
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result = CellTypes::eval(cell, in_map[ID::A], in_map[ID::B], in_map[ID::B], &err);
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// (A,B,C -> Y) and (A,B,C,D -> Y) cells
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else if (has_a && has_b && has_c && !has_s && !has_x && has_y)
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result = CellTypes::eval(cell, in_map[ID::A], in_map[ID::B], in_map[ID::C], in_map[ID::D], &err);
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// (A,S -> Y) cells
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else if (has_a && !has_b && !has_c && !has_d && has_s && !has_x && has_y)
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result = CellTypes::eval(cell, in_map[ID::A], in_map[ID::S], &err);
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@ -961,6 +1061,8 @@ struct TestCellPass : public Pass {
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cell_types[ID($not)] = "ASY";
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cell_types[ID($pos)] = "ASY";
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cell_types[ID($neg)] = "ASY";
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if (techmap_cmd.compare("techmap -assert") != 0)
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cell_types[ID($buf)] = "A";
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cell_types[ID($and)] = "ABSY";
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cell_types[ID($or)] = "ABSY";
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@ -996,7 +1098,8 @@ struct TestCellPass : public Pass {
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cell_types[ID($mod)] = "ABSY";
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cell_types[ID($divfloor)] = "ABSY";
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cell_types[ID($modfloor)] = "ABSY";
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// cell_types[ID($pow)] = "ABsY";
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if (nosat && techmap_cmd.compare("aigmap") == 0)
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cell_types[ID($pow)] = "ABsY";
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cell_types[ID($logic_not)] = "ASY";
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cell_types[ID($logic_and)] = "ABSY";
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@ -1005,12 +1108,13 @@ struct TestCellPass : public Pass {
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cell_types[ID($mux)] = "*";
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cell_types[ID($bmux)] = "*";
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cell_types[ID($demux)] = "*";
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if (edges) {
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if (edges)
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cell_types[ID($pmux)] = "*";
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}
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if (noeval)
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cell_types[ID($bwmux)] = "A";
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// cell_types[ID($slice)] = "A";
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// cell_types[ID($concat)] = "A";
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cell_types[ID($slice)] = "A";
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cell_types[ID($concat)] = "AB";
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cell_types[ID($lut)] = "*";
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cell_types[ID($sop)] = "*";
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@ -1019,6 +1123,26 @@ struct TestCellPass : public Pass {
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cell_types[ID($macc)] = "*";
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cell_types[ID($fa)] = "*";
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cell_types[ID($_BUF_)] = "AYb";
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cell_types[ID($_NOT_)] = "AYb";
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cell_types[ID($_AND_)] = "ABYb";
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cell_types[ID($_NAND_)] = "ABYb";
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cell_types[ID($_OR_)] = "ABYb";
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cell_types[ID($_NOR_)] = "ABYb";
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cell_types[ID($_XOR_)] = "ABYb";
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cell_types[ID($_XNOR_)] = "ABYb";
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cell_types[ID($_ANDNOT_)] = "ABYb";
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cell_types[ID($_ORNOT_)] = "ABYb";
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cell_types[ID($_MUX_)] = "*";
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cell_types[ID($_NMUX_)] = "*";
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// cell_types[ID($_MUX4_)] = "*";
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// cell_types[ID($_MUX8_)] = "*";
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// cell_types[ID($_MUX16_)] = "*";
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cell_types[ID($_AOI3_)] = "ABCYb";
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cell_types[ID($_OAI3_)] = "ABCYb";
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cell_types[ID($_AOI4_)] = "ABCDYb";
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cell_types[ID($_OAI4_)] = "ABCDYb";
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if (list_all) {
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log("test_cell supports the following cell types:\n");
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for (auto it : cell_types)
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