mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-11 00:22:07 +00:00
Code Activity

analogdevices: Use dump_meminit

Browse source 
Add `INIT_FILE` and `SIM_INIT_BEHAVIOR` parameters.
Add `init any` to non-full ADI ram blocks.
This commit is contained in:
Krystine Sherwin 2025-11-10 17:23:41 +13:00
parent 7f8334e781
commit eb2b57b084
No known key found for this signature in database
4 changed files with 25 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

7
techlibs/analogdevices/brams.txt
View file

@ -220,6 +220,9 @@ ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ {
}
}
# supports any initialization value, but need to export memory files
init any;
option "MODE" "SDP" {
ifdef IS_T16FFC forbid;
port sw "A" {
@ -274,6 +277,10 @@ ifdef IS_T40LP {
option "MODE" "SP2" cost 2209;
}
}
# supports any initialization value, but need to export memory files
init any;
option "MODE" "SP2" {
port srsw "A" {
clock anyedge;

12
techlibs/analogdevices/brams_map.v
View file

@ -20,10 +20,12 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...);
`ifdef IS_T16FFC
localparam NODE = "T16FFC_Gen2.4";
`endif
// localparam BRAM_MODE = "SDP_2048x36_BP";
localparam BRAM_MODE = (OPTION_ERR!="NONE") ? {OPTION_MODE, "_", OPTION_SIZE, "_", OPTION_ERR} :
{OPTION_MODE, "_", OPTION_SIZE};
localparam PBITS = (OPTION_ERR=="BP") ? PORT_A_WR_EN_WIDTH : 1;
parameter INIT_FILE = "";
localparam INIT_BEHAVIOR = (INIT_FILE == "" || INIT_FILE == "X") ? "UNINITIALIZED" :
INIT_FILE == "0" ? "ALL_ZERO" : "INIT_FILE";
// libmap ports
input PORT_A_CLK;
@ -49,10 +51,12 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...);
#(
.TARGET_NODE(NODE),
.BRAM_MODE(BRAM_MODE),
.INIT_FILE_A(INIT_BEHAVIOR == "INIT_FILE" ? INIT_FILE : ""),
.QA_REG((OPTION_ERR=="ECC") ? 1 : 0),
.QB_REG((OPTION_ERR=="ECC") ? 1 : 0),
.CLKA_INV(!PORT_A_CLK_POL),
.CLKB_INV(!PORT_B_CLK_POL),
.SIM_INIT_BEHAVIOR(INIT_BEHAVIOR),
.DATA_WIDTH(WIDTH),
.ADDR_WIDTH(ABITS),
.WE_WIDTH(PORT_A_WR_EN_WIDTH),
@ -145,6 +149,9 @@ module $__ANALOGDEVICES_BLOCKRAM_HALF_ (...);
parameter WIDTH = 40;
parameter ABITS = 13;
// non libmap params
parameter INIT_FILE = "";
// libmap ports
input PORT_A_CLK;
input PORT_A_CLK_EN;
@ -205,6 +212,9 @@ module $__ANALOGDEVICES_BLOCKRAM_QUARTER_ (...);
parameter WIDTH = 40;
parameter ABITS = 13;
// non libmap params
parameter INIT_FILE = "";
// libmap ports
input PORT_A_CLK;
input PORT_A_CLK_EN;

6
techlibs/analogdevices/cells_sim.v
View file

@ -1105,10 +1105,13 @@ endmodule
module RBRAM #(
parameter TARGET_NODE = "T40LP_Gen2.4",
parameter BRAM_MODE = "SDP_1024x40",
parameter INIT_FILE_A = "",
parameter INIT_FILE_B = "",
parameter QA_REG = 0,
parameter QB_REG = 0,
parameter CLKA_INV = 0,
parameter CLKB_INV = 0,
parameter SIM_INIT_BEHAVIOR = "UNINITIALIZED",
parameter DATA_WIDTH = 40,
parameter ADDR_WIDTH = 12,
parameter WE_WIDTH = 20,
@ -1145,10 +1148,13 @@ endmodule
module RBRAM2 #(
parameter TARGET_NODE = "T16FFC_Gen2.4",
parameter BRAM_MODE = "SDP_2048x40",
parameter INIT_FILE_A = "",
parameter INIT_FILE_B = "",
parameter QA_REG = 0,
parameter QB_REG = 0,
parameter CLKA_INV = 0,
parameter CLKB_INV = 0,
parameter SIM_INIT_BEHAVIOR = "UNINITIALIZED",
parameter DATA_WIDTH = 40,
parameter ADDR_WIDTH = 13,
parameter WE_WIDTH = 20,

1
techlibs/analogdevices/synth_analogdevices.cc
View file

@ -366,6 +366,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
params += " -no-auto-block";
}
run("memory_libmap" + params);
run("dump_meminit t:$__ANALOGDEVICES_BLOCKRAM_*");
run("techmap -map " + lutrams_map);
run("techmap -map " + brams_map);
}