diff --git a/techlibs/analogdevices/brams.txt b/techlibs/analogdevices/brams.txt
index 10cdadefb..477c361e3 100644
--- a/techlibs/analogdevices/brams.txt
+++ b/techlibs/analogdevices/brams.txt
@@ -220,6 +220,9 @@ ram block $__ANALOGDEVICES_BLOCKRAM_HALF_ {
 		}
 	}
 
+	# supports any initialization value, but need to export memory files
+	init any;
+
 	option "MODE" "SDP" {
 		ifdef IS_T16FFC forbid;
 		port sw "A" {
@@ -274,6 +277,10 @@ ifdef IS_T40LP {
 				option "MODE" "SP2" cost 2209;
 			}
 		}
+
+		# supports any initialization value, but need to export memory files
+		init any;
+
 		option "MODE" "SP2" {
 			port srsw "A" {
 				clock anyedge;
diff --git a/techlibs/analogdevices/brams_map.v b/techlibs/analogdevices/brams_map.v
index f1acaaf78..0a6bb96f7 100644
--- a/techlibs/analogdevices/brams_map.v
+++ b/techlibs/analogdevices/brams_map.v
@@ -20,10 +20,12 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...);
 `ifdef IS_T16FFC
 	localparam NODE = "T16FFC_Gen2.4";
 `endif
-	// localparam BRAM_MODE = "SDP_2048x36_BP";
 	localparam BRAM_MODE = (OPTION_ERR!="NONE") ? {OPTION_MODE, "_", OPTION_SIZE, "_", OPTION_ERR} :
 							{OPTION_MODE, "_", OPTION_SIZE};
 	localparam PBITS = 	(OPTION_ERR=="BP") ? PORT_A_WR_EN_WIDTH : 1;
+	parameter INIT_FILE = "";
+	localparam INIT_BEHAVIOR = (INIT_FILE == "" || INIT_FILE == "X") ? "UNINITIALIZED" :
+								INIT_FILE == "0" ? "ALL_ZERO" : "INIT_FILE";
 
 	// libmap ports
 	input PORT_A_CLK;
@@ -49,10 +51,12 @@ module $__ANALOGDEVICES_BLOCKRAM_FULL_ (...);
 	#(
 		.TARGET_NODE(NODE),
 		.BRAM_MODE(BRAM_MODE),
+		.INIT_FILE_A(INIT_BEHAVIOR == "INIT_FILE" ? INIT_FILE : ""),
 		.QA_REG((OPTION_ERR=="ECC") ? 1 : 0),
 		.QB_REG((OPTION_ERR=="ECC") ? 1 : 0),
 		.CLKA_INV(!PORT_A_CLK_POL),
 		.CLKB_INV(!PORT_B_CLK_POL),
+		.SIM_INIT_BEHAVIOR(INIT_BEHAVIOR),
 		.DATA_WIDTH(WIDTH),
 		.ADDR_WIDTH(ABITS),
 		.WE_WIDTH(PORT_A_WR_EN_WIDTH),
@@ -145,6 +149,9 @@ module $__ANALOGDEVICES_BLOCKRAM_HALF_ (...);
 	parameter WIDTH = 40;
 	parameter ABITS = 13;
 
+	// non libmap params
+	parameter INIT_FILE = "";
+
 	// libmap ports
 	input PORT_A_CLK;
 	input PORT_A_CLK_EN;
@@ -205,6 +212,9 @@ module $__ANALOGDEVICES_BLOCKRAM_QUARTER_ (...);
 	parameter WIDTH = 40;
 	parameter ABITS = 13;
 
+	// non libmap params
+	parameter INIT_FILE = "";
+
 	// libmap ports
 	input PORT_A_CLK;
 	input PORT_A_CLK_EN;
diff --git a/techlibs/analogdevices/cells_sim.v b/techlibs/analogdevices/cells_sim.v
index 402c421fa..1448e0147 100644
--- a/techlibs/analogdevices/cells_sim.v
+++ b/techlibs/analogdevices/cells_sim.v
@@ -1105,10 +1105,13 @@ endmodule
 module RBRAM #(
     parameter TARGET_NODE = "T40LP_Gen2.4",
     parameter BRAM_MODE = "SDP_1024x40",
+    parameter INIT_FILE_A = "",
+    parameter INIT_FILE_B = "",
     parameter QA_REG = 0,
     parameter QB_REG = 0,
     parameter CLKA_INV = 0,
     parameter CLKB_INV = 0,
+    parameter SIM_INIT_BEHAVIOR = "UNINITIALIZED",
     parameter DATA_WIDTH = 40,
     parameter ADDR_WIDTH = 12,
     parameter WE_WIDTH = 20,
@@ -1145,10 +1148,13 @@ endmodule
 module RBRAM2 #(
     parameter TARGET_NODE = "T16FFC_Gen2.4",
     parameter BRAM_MODE = "SDP_2048x40",
+    parameter INIT_FILE_A = "",
+    parameter INIT_FILE_B = "",
     parameter QA_REG = 0,
     parameter QB_REG = 0,
     parameter CLKA_INV = 0,
     parameter CLKB_INV = 0,
+    parameter SIM_INIT_BEHAVIOR = "UNINITIALIZED",
     parameter DATA_WIDTH = 40,
     parameter ADDR_WIDTH = 13,
     parameter WE_WIDTH = 20,
diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc
index abb95ea33..f73fbaa80 100644
--- a/techlibs/analogdevices/synth_analogdevices.cc
+++ b/techlibs/analogdevices/synth_analogdevices.cc
@@ -366,6 +366,7 @@ struct SynthAnalogDevicesPass : public ScriptPass
 					params += " -no-auto-block";
 			}
 			run("memory_libmap" + params);
+			run("dump_meminit t:$__ANALOGDEVICES_BLOCKRAM_*");
 			run("techmap -map " + lutrams_map);
 			run("techmap -map " + brams_map);
 		}