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fixed tests

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This commit is contained in:
Miodrag Milanovic 2023-08-23 10:54:29 +02:00
parent 75fd706487
commit ea50d96135
10 changed files with 20 additions and 21 deletions
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2
tests/arch/machxo2/logic.ys
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@ -1,7 +1,7 @@
read_verilog ../common/logic.v
hierarchy -top top
proc
equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check
equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 9 t:LUT4