diff --git a/tests/arch/machxo2/add_sub.ys b/tests/arch/machxo2/add_sub.ys index 97ee90fbb..6897363aa 100644 --- a/tests/arch/machxo2/add_sub.ys +++ b/tests/arch/machxo2/add_sub.ys @@ -1,7 +1,7 @@ read_verilog ../common/add_sub.v hierarchy -top top proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 10 t:LUT4 diff --git a/tests/arch/machxo2/adffs.ys b/tests/arch/machxo2/adffs.ys index a9f8980c6..f1134a6ac 100644 --- a/tests/arch/machxo2/adffs.ys +++ b/tests/arch/machxo2/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -async2sync -assert -map +/machxo2/cells_sim.v synth_machxo2 -noiopad # equivalency check +equiv_opt -async2sync -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF diff --git a/tests/arch/machxo2/counter.ys b/tests/arch/machxo2/counter.ys index 54ee80066..11560b551 100644 --- a/tests/arch/machxo2/counter.ys +++ b/tests/arch/machxo2/counter.ys @@ -2,7 +2,7 @@ read_verilog ../common/counter.v hierarchy -top top proc flatten -equiv_opt -assert -multiclock -map +/machxo2/cells_sim.v synth_machxo2 -ccu2 -noiopad # equivalency check +equiv_opt -assert -multiclock -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 4 t:CCU2D diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys index 29dcafe23..663a64294 100644 --- a/tests/arch/machxo2/dffs.ys +++ b/tests/arch/machxo2/dffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top dff proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -12,8 +12,8 @@ select -assert-none t:TRELLIS_FF t:TRELLIS_IO %% t:* %D design -load read hierarchy -top dffe proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module -select -assert-count 2 t:TRELLIS_FF t:LUT4 +select -assert-count 1 t:TRELLIS_FF t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 t:TRELLIS_IO %% t:* %D diff --git a/tests/arch/machxo2/fsm.ys b/tests/arch/machxo2/fsm.ys index a61357fcd..70e1a632b 100644 --- a/tests/arch/machxo2/fsm.ys +++ b/tests/arch/machxo2/fsm.ys @@ -3,7 +3,7 @@ hierarchy -top fsm proc flatten -equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 +equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut miter -equiv -make_assert -flatten gold gate miter sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter diff --git a/tests/arch/machxo2/logic.ys b/tests/arch/machxo2/logic.ys index 0cf57310c..5c7995305 100644 --- a/tests/arch/machxo2/logic.ys +++ b/tests/arch/machxo2/logic.ys @@ -1,7 +1,7 @@ read_verilog ../common/logic.v hierarchy -top top proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 9 t:LUT4 diff --git a/tests/arch/machxo2/lutram.ys b/tests/arch/machxo2/lutram.ys index dc6b86fd3..8f1918587 100644 --- a/tests/arch/machxo2/lutram.ys +++ b/tests/arch/machxo2/lutram.ys @@ -2,7 +2,7 @@ read_verilog ../common/lutram.v hierarchy -top lutram_1w1r proc memory -nomap -equiv_opt -run :prove -map +/machxo2/cells_sim.v synth_machxo2 -noiopad +equiv_opt -run :prove -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut memory opt -full diff --git a/tests/arch/machxo2/mux.ys b/tests/arch/machxo2/mux.ys index 27bffbe63..4fa1bd2fc 100644 --- a/tests/arch/machxo2/mux.ys +++ b/tests/arch/machxo2/mux.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top mux2 proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module select -assert-count 1 t:LUT4 @@ -12,7 +12,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 2 t:LUT4 @@ -22,7 +22,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 5 t:LUT4 @@ -32,7 +32,7 @@ select -assert-none t:LUT4 t:TRELLIS_IO %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-max 12 t:LUT4 diff --git a/tests/arch/machxo2/shifter.ys b/tests/arch/machxo2/shifter.ys index bff881fb7..f6440c025 100644 --- a/tests/arch/machxo2/shifter.ys +++ b/tests/arch/machxo2/shifter.ys @@ -2,7 +2,7 @@ read_verilog ../common/shifter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/arch/machxo2/tribuf.ys b/tests/arch/machxo2/tribuf.ys index 840979439..08c86008d 100644 --- a/tests/arch/machxo2/tribuf.ys +++ b/tests/arch/machxo2/tribuf.ys @@ -2,9 +2,8 @@ read_verilog ../common/tribuf.v hierarchy -top tristate proc flatten -equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +equiv_opt -assert -map +/lattice/cells_sim_xo2.v -map +/simcells.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd tristate # Constrain all select calls below inside the top module -select -assert-count 3 t:TRELLIS_IO -select -assert-count 1 t:LUT4 -select -assert-none t:TRELLIS_IO t:LUT4 %% t:* %D +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D