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Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
opt_expr: improve performance on $alu and $sub
This commit is contained in:
Eddie Hung
GitHub
commit
e79bc45975
2 changed files with 114 additions and 19 deletions
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@ -651,10 +651,14 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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int i;
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for (i = 0; i < GetSize(sig_y); i++) {
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if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
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module->connect(sig_y[i], sig_a[i]);
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else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
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module->connect(sig_y[i], sig_b[i]);
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RTLIL::SigBit b = sig_b.at(i, State::Sx);
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RTLIL::SigBit a = sig_a.at(i, State::Sx);
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if (b == State::S0 && a != State::Sx)
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module->connect(sig_y[i], a);
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else if (sub && b == State::S1 && a == State::S1)
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module->connect(sig_y[i], State::S0);
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else if (!sub && a == State::S0 && b != State::Sx)
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module->connect(sig_y[i], b);
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else
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break;
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}
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@ -668,7 +672,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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}
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}
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if (cell->type == "$alu")
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if (cell->type == ID($alu))
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{
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RTLIL::SigSpec sig_a = assign_map(cell->getPort(ID::A));
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RTLIL::SigSpec sig_b = assign_map(cell->getPort(ID::B));
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@ -678,9 +682,6 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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RTLIL::SigSpec sig_y = cell->getPort(ID::Y);
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RTLIL::SigSpec sig_co = cell->getPort(ID(CO));
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if (sig_ci.wire || sig_bi.wire)
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goto next_cell;
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bool sub = (sig_ci == State::S1 && sig_bi == State::S1);
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// If not a subtraction, yet there is a carry or B is inverted
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@ -690,14 +691,21 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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int i;
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for (i = 0; i < GetSize(sig_y); i++) {
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if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx) {
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module->connect(sig_x[i], sub ? module->Not(NEW_ID, sig_a[i]).as_bit() : sig_a[i]);
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RTLIL::SigBit b = sig_b.at(i, State::Sx);
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RTLIL::SigBit a = sig_a.at(i, State::Sx);
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if (b == State::S0 && a != State::Sx) {
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module->connect(sig_y[i], sig_a[i]);
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module->connect(sig_x[i], sub ? module->Not(NEW_ID, a).as_bit() : a);
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module->connect(sig_co[i], sub ? State::S1 : State::S0);
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}
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else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx) {
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module->connect(sig_x[i], sig_b[i]);
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module->connect(sig_y[i], sig_b[i]);
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else if (sub && b == State::S1 && a == State::S1) {
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module->connect(sig_y[i], State::S0);
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module->connect(sig_x[i], module->Not(NEW_ID, a));
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module->connect(sig_co[i], State::S0);
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}
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else if (!sub && a == State::S0 && b != State::Sx) {
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module->connect(sig_y[i], b);
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module->connect(sig_x[i], b);
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module->connect(sig_co[i], State::S0);
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}
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else
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@ -1032,12 +1040,26 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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bool identity_wrt_b = false;
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bool arith_inverse = false;
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if (cell->type.in(ID($add), ID($sub), ID($or), ID($xor)))
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if (cell->type.in(ID($add), ID($sub), ID($alu), ID($or), ID($xor)))
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{
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RTLIL::SigSpec a = assign_map(cell->getPort(ID::A));
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RTLIL::SigSpec b = assign_map(cell->getPort(ID::B));
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if (cell->type != ID($sub) && a.is_fully_const() && a.as_bool() == false)
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bool sub = cell->type == ID($sub);
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if (cell->type == ID($alu)) {
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RTLIL::SigBit sig_ci = assign_map(cell->getPort(ID(CI)));
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RTLIL::SigBit sig_bi = assign_map(cell->getPort(ID(BI)));
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sub = (sig_ci == State::S1 && sig_bi == State::S1);
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// If not a subtraction, yet there is a carry or B is inverted
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// then no optimisation is possible as carry will not be constant
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if (!sub && (sig_ci != State::S0 || sig_bi != State::S0))
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goto next_cell;
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}
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if (!sub && a.is_fully_const() && a.as_bool() == false)
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identity_wrt_b = true;
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if (b.is_fully_const() && b.as_bool() == false)
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@ -1075,17 +1097,27 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (identity_wrt_a || identity_wrt_b)
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{
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if (identity_wrt_a)
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cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
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cover_list("opt.opt_expr.identwrt.a", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
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if (identity_wrt_b)
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cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
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cover_list("opt.opt_expr.identwrt.b", "$add", "$sub", "$alu", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
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log_debug("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
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cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
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if (cell->type == ID($alu)) {
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int y_width = GetSize(cell->getPort(ID(Y)));
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module->connect(cell->getPort(ID(X)), RTLIL::Const(State::S0, y_width));
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module->connect(cell->getPort(ID(CO)), RTLIL::Const(State::S0, y_width));
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cell->unsetPort(ID(BI));
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cell->unsetPort(ID(CI));
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cell->unsetPort(ID(X));
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cell->unsetPort(ID(CO));
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}
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if (!identity_wrt_a) {
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cell->setPort(ID::A, cell->getPort(ID::B));
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cell->parameters.at(ID(A_WIDTH)) = cell->parameters.at(ID(B_WIDTH));
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cell->parameters.at(ID(A_SIGNED)) = cell->parameters.at(ID(B_SIGNED));
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cell->setParam(ID(A_WIDTH), cell->getParam(ID(B_WIDTH)));
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cell->setParam(ID(A_SIGNED), cell->getParam(ID(B_SIGNED)));
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}
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cell->type = arith_inverse ? ID($neg) : ID($pos);
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63
tests/opt/opt_expr_alu.ys
Normal file
63
tests/opt/opt_expr_alu.ys
Normal file
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@ -0,0 +1,63 @@
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b0} + 1'b1;
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endmodule
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EOT
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alumacc
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b1} + 1'b1;
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endmodule
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EOT
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alumacc
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select -assert-count 1 t:$alu
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select -assert-count none t:$alu t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [1:0] y);
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assign y = {a,1'b1} - 1'b1;
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endmodule
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EOT
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [3:0] y);
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assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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design -reset
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read_verilog <<EOT
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module test(input a, output [3:0] y);
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assign y = {a,3'b101} - 1'b1;
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endmodule
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EOT
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alumacc
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equiv_opt opt_expr -fine
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design -load postopt
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select -assert-count 1 t:$pos
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select -assert-count none t:$pos t:* %D
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