mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-11-04 05:19:11 +00:00
Code Activity

Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu

Browse source 
opt_expr: improve performance on $alu and $sub
This commit is contained in:
Eddie Hung 2020-04-01 14:11:09 -07:00 • committed by GitHub
commit e79bc45975
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
2 changed files with 114 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

63
tests/opt/opt_expr_alu.ys Normal file
View file

@ -0,0 +1,63 @@
read_verilog <<EOT
module test(input a, output [1:0] y);
assign y = {a,1'b0} + 1'b1;
endmodule
EOT
alumacc
equiv_opt opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
design -reset
read_verilog <<EOT
module test(input a, output [1:0] y);
assign y = {a,1'b1} + 1'b1;
endmodule
EOT
alumacc
select -assert-count 1 t:$alu
select -assert-count none t:$alu t:* %D
design -reset
read_verilog <<EOT
module test(input a, output [1:0] y);
assign y = {a,1'b1} - 1'b1;
endmodule
EOT
equiv_opt opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
design -reset
read_verilog <<EOT
module test(input a, output [3:0] y);
assign y = {a,3'b101} - 1'b1;
endmodule
EOT
equiv_opt opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D
design -reset
read_verilog <<EOT
module test(input a, output [3:0] y);
assign y = {a,3'b101} - 1'b1;
endmodule
EOT
alumacc
equiv_opt opt_expr -fine
design -load postopt
select -assert-count 1 t:$pos
select -assert-count none t:$pos t:* %D