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Add test: 'Warning: ignoring initial value on non-register: \o'

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Eddie Hung 2019-12-11 11:26:54 -08:00
parent 613334d9dc
commit e75ca29b19
1 changed files with 10 additions and 0 deletions
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10
tests/sat/initval.ys
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@ -2,3 +2,13 @@ read_verilog -sv initval.v
proc;; proc;;
sat -seq 10 -prove-asserts sat -seq 10 -prove-asserts
design -reset
read_verilog -icells <<EOT
module top(input clk, i, output o, p);
(* init = 1'bx *)
wire p = o;
$_DFF_P_ dff (.C(clk), .D(i), .Q(o));
endmodule
EOT
sat -seq 1