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sta: assume input-less modules to be constant drivers and don't warn ...

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if no timing arcs. Also handle undefined modules with a warning
This commit is contained in:
Eddie Hung 2020-04-03 14:20:57 -07:00
parent 9cf172b7a9
commit e6642d2928
3 changed files with 53 additions and 3 deletions
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9
kernel/timinginfo.h
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@ -52,6 +52,7 @@ struct TimingInfo
{ {
dict<BitBit, int> comb; dict<BitBit, int> comb;
dict<NameBit, std::pair<int,NameBit>> arrival, required; dict<NameBit, std::pair<int,NameBit>> arrival, required;
bool has_inputs;
}; };
dict<RTLIL::IdString, ModuleTiming> data; dict<RTLIL::IdString, ModuleTiming> data;
@ -167,6 +168,14 @@ struct TimingInfo
} }
} }
for (auto port_name : module->ports) {
auto wire = module->wire(port_name);
if (wire->port_input) {
t.has_inputs = true;
break;
}
}
return t; return t;
} }

9
passes/cmds/sta.cc
View file

@ -60,10 +60,13 @@ struct StaWorker
for (auto cell : module->cells()) for (auto cell : module->cells())
{ {
Module *inst_module = design->module(cell->type); Module *inst_module = design->module(cell->type);
log_assert(inst_module); if (!inst_module) {
log_warning("Cell type '%s' not recognised! Ignoring.\n", log_id(cell->type));
continue;
}
if (!inst_module->get_blackbox_attribute()) { if (!inst_module->get_blackbox_attribute()) {
log_warning("Module '%s' is not a black- nor white-box!\n", log_id(cell->type)); log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", log_id(cell->type));
continue; continue;
} }
@ -73,7 +76,7 @@ struct StaWorker
if (!timing.count(derived_type)) { if (!timing.count(derived_type)) {
auto &t = timing.setup_module(inst_module); auto &t = timing.setup_module(inst_module);
if (t.comb.empty() && t.arrival.empty() && t.required.empty()) if (t.has_inputs && t.comb.empty() && t.arrival.empty() && t.required.empty())
log_warning("Module '%s' has no timing arcs!\n", log_id(cell->type)); log_warning("Module '%s' has no timing arcs!\n", log_id(cell->type));
} }

38
tests/various/sta.ys
View file

@ -40,4 +40,42 @@ endmodule
EOT EOT
sta sta
design -reset
read_verilog -specify <<EOT
module buffer(input i, output o);
specify
(i => o) = 10;
endspecify
endmodule
module top(input i, output o, p);
buffer b(.i(i), .o(o));
const0 c(.o(p));
endmodule
EOT
logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1
sta
design -reset
read_verilog -specify <<EOT
module buffer(input i, output o);
specify
(i => o) = 10;
endspecify
endmodule
module const0(output o);
endmodule
module top(input i, output o, p);
buffer b(.i(i), .o(o));
const0 c(.o(p));
endmodule
EOT
sta
logger -expect-no-warnings logger -expect-no-warnings