diff --git a/kernel/timinginfo.h b/kernel/timinginfo.h
index c08f6c9d8..580d36b1a 100644
--- a/kernel/timinginfo.h
+++ b/kernel/timinginfo.h
@@ -52,6 +52,7 @@ struct TimingInfo
 	{
 		dict<BitBit, int> comb;
 		dict<NameBit, std::pair<int,NameBit>> arrival, required;
+		bool has_inputs;
 	};
 
 	dict<RTLIL::IdString, ModuleTiming> data;
@@ -167,6 +168,14 @@ struct TimingInfo
 			}
 		}
 
+		for (auto port_name : module->ports) {
+			auto wire = module->wire(port_name);
+			if (wire->port_input) {
+				t.has_inputs = true;
+				break;
+			}
+		}
+
 		return t;
 	}
 
diff --git a/passes/cmds/sta.cc b/passes/cmds/sta.cc
index d71816fde..d79cb949a 100644
--- a/passes/cmds/sta.cc
+++ b/passes/cmds/sta.cc
@@ -60,10 +60,13 @@ struct StaWorker
 		for (auto cell : module->cells())
 		{
 			Module *inst_module = design->module(cell->type);
-			log_assert(inst_module);
+			if (!inst_module) {
+				log_warning("Cell type '%s' not recognised! Ignoring.\n", log_id(cell->type));
+				continue;
+			}
 
 			if (!inst_module->get_blackbox_attribute()) {
-				log_warning("Module '%s' is not a black- nor white-box!\n", log_id(cell->type));
+				log_warning("Cell type '%s' is not a black- nor white-box! Ignoring.\n", log_id(cell->type));
 				continue;
 			}
 
@@ -73,7 +76,7 @@ struct StaWorker
 
 			if (!timing.count(derived_type)) {
 				auto &t = timing.setup_module(inst_module);
-				if (t.comb.empty() && t.arrival.empty() && t.required.empty())
+				if (t.has_inputs && t.comb.empty() && t.arrival.empty() && t.required.empty())
 					log_warning("Module '%s' has no timing arcs!\n", log_id(cell->type));
 			}
 
diff --git a/tests/various/sta.ys b/tests/various/sta.ys
index 3944b5e7d..cfb6ff2be 100644
--- a/tests/various/sta.ys
+++ b/tests/various/sta.ys
@@ -40,4 +40,42 @@ endmodule
 EOT
 
 sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+const0 c(.o(p));
+endmodule
+EOT
+
+logger -expect warning "Cell type 'const0' not recognised! Ignoring\." 1 
+sta
+
+
+design -reset
+read_verilog -specify <<EOT
+module buffer(input i, output o);
+specify
+(i => o) = 10;
+endspecify
+endmodule
+module const0(output o);
+endmodule
+
+module top(input i, output o, p);
+buffer b(.i(i), .o(o));
+const0 c(.o(p));
+endmodule
+EOT
+
+sta
+
 logger -expect-no-warnings