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sta: assume input-less modules to be constant drivers and don't warn ...

if no timing arcs. Also handle undefined modules with a warning
This commit is contained in:
Eddie Hung 2020-04-03 14:20:57 -07:00
parent 9cf172b7a9
commit e6642d2928
3 changed files with 53 additions and 3 deletions

View file

@ -52,6 +52,7 @@ struct TimingInfo
{
dict<BitBit, int> comb;
dict<NameBit, std::pair<int,NameBit>> arrival, required;
bool has_inputs;
};
dict<RTLIL::IdString, ModuleTiming> data;
@ -167,6 +168,14 @@ struct TimingInfo
}
}
for (auto port_name : module->ports) {
auto wire = module->wire(port_name);
if (wire->port_input) {
t.has_inputs = true;
break;
}
}
return t;
}