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sta: assume input-less modules to be constant drivers and don't warn ...
if no timing arcs. Also handle undefined modules with a warning
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9cf172b7a9
commit
e6642d2928
3 changed files with 53 additions and 3 deletions
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@ -52,6 +52,7 @@ struct TimingInfo
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{
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dict<BitBit, int> comb;
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dict<NameBit, std::pair<int,NameBit>> arrival, required;
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bool has_inputs;
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};
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dict<RTLIL::IdString, ModuleTiming> data;
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@ -167,6 +168,14 @@ struct TimingInfo
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}
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}
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for (auto port_name : module->ports) {
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auto wire = module->wire(port_name);
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if (wire->port_input) {
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t.has_inputs = true;
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break;
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}
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}
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return t;
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}
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