3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-02-20 23:44:44 +00:00
This commit is contained in:
Dhaval 2026-02-12 01:15:58 -08:00 committed by GitHub
commit e5252c3ac1
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
2 changed files with 26 additions and 2 deletions

View file

@ -109,6 +109,7 @@ int verific_verbose;
bool verific_import_pending;
string verific_error_msg;
int verific_sva_fsm_limit;
bool verific_no_split_complex_ports = false; // disable splitting of complex ports
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
vector<string> verific_incdirs, verific_libdirs, verific_libexts;
@ -3061,8 +3062,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg);
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
if (!verific_no_split_complex_ports)
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
VerificExtNets worker;
for (auto nl : nl_todo)
@ -3697,6 +3699,11 @@ struct VerificPass : public Pass {
break;
}
if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") {
verific_no_split_complex_ports = true;
goto check_error;
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F"))
{