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verific: support single_bit_vector

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This commit is contained in:
Emil J. Tywoniak 2025-05-12 13:23:02 +02:00
parent 5e72464a15
commit e5171d6aa1
2 changed files with 19 additions and 5 deletions
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4
frontends/verific/verific.cc
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@ -1557,6 +1557,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
wire->upto = portbus->IsUp();
import_attributes(wire->attributes, portbus, nl, portbus->Size());
if (portbus->Size() == 1)
wire->set_bool_attribute(ID::single_bit_vector);
SetIter si ;
Port *port ;
FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
@ -1755,6 +1757,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
break;
}
import_attributes(wire->attributes, netbus, nl, netbus->Size());
if (netbus->Size() == 1)
wire->set_bool_attribute(ID::single_bit_vector);
RTLIL::Const initval = Const(State::Sx, GetSize(wire));
bool initval_valid = false;

20
tests/verilog/sbvector.ys
View file

@ -4,17 +4,27 @@ module foo(
input [0:0] i1,
input i2
);
assign o = i1 ^ i2;
wire [0:0] w1 = i1 ^ i2;
wire w2 = ~i1;
assign o = w1 ^ w2;
endmodule
EOT
logger -expect log "wire width 1 input 2 \\i1" 1
logger -expect log "wire input 3 \\i2" 1
dump
logger -check-expected
hierarchy
proc
select -assert-count 1 w:i1
select -assert-count 1 w:i1 a:single_bit_vector %i
select -assert-count 1 w:i2
select -assert-count 0 w:i2 a:single_bit_vector %i
select -assert-count 1 w:w1
select -assert-count 1 w:w1 a:single_bit_vector %i
select -assert-count 1 w:w2
select -assert-count 0 w:w2 a:single_bit_vector %i
write_verilog verilog_sbvector.out
!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
!grep -qF 'input [0:0] i1;' verilog_sbvector.out
!grep -qF 'wire i2;' verilog_sbvector.out
!grep -qF 'input i2;' verilog_sbvector.out
!grep -qF 'wire [0:0] w1;' verilog_sbvector.out
!grep -qF 'wire w2;' verilog_sbvector.out