From e5171d6aa1468c5f9b5a2b4c43a370541f1d2ac1 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 12 May 2025 13:23:02 +0200 Subject: [PATCH] verific: support single_bit_vector --- frontends/verific/verific.cc | 4 ++++ tests/verilog/sbvector.ys | 20 +++++++++++++++----- 2 files changed, 19 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 95bede420..411804566 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1557,6 +1557,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex()); wire->upto = portbus->IsUp(); import_attributes(wire->attributes, portbus, nl, portbus->Size()); + if (portbus->Size() == 1) + wire->set_bool_attribute(ID::single_bit_vector); SetIter si ; Port *port ; FOREACH_PORT_OF_PORTBUS(portbus, si, port) { @@ -1755,6 +1757,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma break; } import_attributes(wire->attributes, netbus, nl, netbus->Size()); + if (netbus->Size() == 1) + wire->set_bool_attribute(ID::single_bit_vector); RTLIL::Const initval = Const(State::Sx, GetSize(wire)); bool initval_valid = false; diff --git a/tests/verilog/sbvector.ys b/tests/verilog/sbvector.ys index 3481f6f45..ab8092700 100644 --- a/tests/verilog/sbvector.ys +++ b/tests/verilog/sbvector.ys @@ -4,17 +4,27 @@ module foo( input [0:0] i1, input i2 ); - assign o = i1 ^ i2; + wire [0:0] w1 = i1 ^ i2; + wire w2 = ~i1; + assign o = w1 ^ w2; endmodule EOT -logger -expect log "wire width 1 input 2 \\i1" 1 -logger -expect log "wire input 3 \\i2" 1 -dump -logger -check-expected +hierarchy +proc +select -assert-count 1 w:i1 +select -assert-count 1 w:i1 a:single_bit_vector %i +select -assert-count 1 w:i2 +select -assert-count 0 w:i2 a:single_bit_vector %i +select -assert-count 1 w:w1 +select -assert-count 1 w:w1 a:single_bit_vector %i +select -assert-count 1 w:w2 +select -assert-count 0 w:w2 a:single_bit_vector %i write_verilog verilog_sbvector.out !grep -qF 'wire [0:0] i1;' verilog_sbvector.out !grep -qF 'input [0:0] i1;' verilog_sbvector.out !grep -qF 'wire i2;' verilog_sbvector.out !grep -qF 'input i2;' verilog_sbvector.out +!grep -qF 'wire [0:0] w1;' verilog_sbvector.out +!grep -qF 'wire w2;' verilog_sbvector.out