mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2026-05-20 17:09:45 +00:00
Code Activity

Fixed not intentional log_signal removal

Browse source
This commit is contained in:
Miodrag Milanovic 2026-05-15 12:34:54 +02:00
parent 965a3e67f0
commit e4a3b44e8e
2 changed files with 2 additions and 2 deletions
Download patch file Download diff file Expand all files Collapse all files

2
backends/aiger2/aiger.cc
View file

@ -1048,7 +1048,7 @@ struct XAigerWriter : AigerWriter {
} else if (!is_input && !inputs) {
for (auto &bit : conn.second) {
if (!bit.wire || (bit.wire->port_input && !bit.wire->port_output))
log_error("Bad connection %s/%s ~ %s\n", box, conn.first.unescape(), conn.second);
log_error("Bad connection %s/%s ~ %s\n", box, conn.first.unescape(), log_signal(conn.second));
ensure_pi(bit, cursor);